JPH05167088A - Variable capacitance diode and fabrication thereof - Google Patents

Abstract

PURPOSE:To set a capacitance variation ratio to be greater by employing a buried diffusion layer formed at a boundary between a semiconductor substrate and an epitaxial layer to which a PN junction depletion layer extends as an N<-> conductivity type diffusion layer by diffusing a P conductivity type impurity element into an N conductivity type semiconductor substrate. CONSTITUTION:A P conductivity type dopant ion-implanted into a semiconductor substrate 2 is cancelled out by the conductivity type of the semiconductor substrate 2 into N<->, N<--> conductivity type ion implanted layer laying a relatively high specific resistance characteristic. A relatively low specific resistance N<-> conductivity type epitaxial layer 3 is formed on the semiconductor substrate 2 through an epitaxial growth process. The semiconductor substrate 1 is rendered to a thermal oxidization processing to form a thermal oxide film 7 on the principal surface of the semiconductor substrate 1, and an opening part 7, is formed for the successive diffusion process through an etching process. An N conductivity type dopant is introduced by ion implantation from the opening part 7, with the thermal oxide film 7 taken as a mask, and successively an N<++> conductivity type diffusion layer 5 is formed though an annealing process and a diffusion process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable capacitance diode in which a capacitance characteristic having a large capacitance variation ratio can be set without depending on the impurity concentration of an epitaxial layer in which a variable capacitance element is formed, and a manufacturing method thereof. It is a thing.

[0002]

2. Description of the Related Art Generally, in a varactor diode, since it is desired to have a large varactor ratio, it is necessary to increase the resistivity of the epitaxial layer by vapor phase epitaxy by forming a small amount of its impurity concentration. ing. Further, in order to meet the demand for obtaining a variable capacitance diode having a small chip size and a relatively large capacitance, an epitaxial layer having an extremely high specific resistance must be used. FIG. 4 is a sectional view of a conventional variable capacitance diode. In the figure,
The N ⁻ conductive type epitaxial layer 3 ₁ having a relatively high specific resistance is formed on the N ⁺⁺ conductive type semiconductor substrate 2 having a low specific resistance by a vapor phase growth method using a small amount of an impurity element as a dopant to form the semiconductor substrate 1 ₁ . Form. An opening 7 ₁ is provided in a thermal oxide film 7 such as a silicon dioxide film of the semiconductor substrate 1 ₁ , and an N-conductivity type impurity element is diffused through the opening 7 ₁ to obtain a low specific resistance N.
⁺⁺ A conductive type diffusion layer 5 is formed. Subsequently, a P ⁺⁺ conductivity type diffusion layer 6 is formed so as to cover the diffusion layer 5, and the PN junction J ₁
To form. A conductive film 8 of aluminum or the like is deposited on the main surface of the diffusion layer 6 to form a variable capacitance diode.

[0003]

In the conventional variable capacitance diode, when the junction area is increased in order to increase the capacitance, the minimum capacitance value of the junction also increases, and as a result, the capacitance variable ratio increases. There is a drawback that cannot be done. As a method of remedying this drawback, the resistivity of the epitaxial layer must be set to an extremely high value of 60 Ωcm or more. However, in order to control the resistivity of the epitaxial layer to such a value, it is necessary to control the inflow of a very small amount of dopant, and it is extremely difficult to maintain stable production. FIG. 5 is a diagram showing the relationship between the resistivity of the epitaxial layer and its yield.
The horizontal axis of FIG. 5 represents the specific resistance value, and the vertical axis represents the yield of the epitaxial layer. As is clear from the figure, when the specific resistance is increased to 60 Ωcm or more, the yield is deteriorated. Therefore, it can be understood that it is extremely difficult to stably produce the variable capacitance diode if an epitaxial layer having such a high specific resistance is to be formed. The present invention has been made in order to solve the above-mentioned problems, and the capacitance variable ratio can be set large even if the epitaxial layer in which the variable capacitance junction is formed has a relatively low specific resistance. The object is to provide a variable capacitance diode.

[0004]

In a variable capacitance diode of the present invention, a first conductivity type semiconductor substrate is formed with a first conductivity type epitaxial layer, a PN junction is formed in the epitaxial layer, and the PN junction is formed. A first conductivity type first diffusion layer having a resistivity higher than that of the epitaxial layer by diffusing an impurity element of the second conductivity type at the boundary between the first conductivity type semiconductor substrate and the epitaxial layer immediately below the junction. Is formed.

[0005]

In the variable capacitance diode of the present invention, the buried diffusion layer formed at the boundary between the epitaxial layer where the depletion layer of the PN junction extends and the semiconductor substrate is connected to the semiconductor substrate of N conductivity type by the P conductivity type. The capacitance variable ratio is set to a large value by diffusing the impurity element to form an N ⁻ conductivity type diffusion layer.

[0006]

1 is a sectional view showing an embodiment of a variable capacitance diode of the present invention. In the figure, reference numeral 1 is a semiconductor substrate in which an N ⁺ conductive type epitaxial layer 3 having a relatively low specific resistance is formed on a low specific resistance N ⁺⁺ conductive type semiconductor substrate 2. At the boundary between the semiconductor substrate 2 and the epitaxial layer 3, a buried type N ⁻ conductive type diffusion layer 4 having a relatively high specific resistance is formed. A low resistivity N ⁺⁺ conductivity type diffusion layer 5 is formed on the epitaxial layer 3, and a P ⁺⁺ conductivity type diffusion layer 6 is formed so as to cover the N ⁺⁺ conductivity type diffusion layer 5. , The main PN junction J ₁ is formed. Immediately below the PN junction J ₁ , the buried diffusion layer 4 is in contact with the diffusion layer 5.
A part of the thermal oxide film (silicon dioxide film) covering the main surface of diffusion layer 6 formed in the heat treatment step is removed, and conductor film 8 is deposited on the main surface of diffusion layer 6. .. In the embodiment of FIG. 1, the specific resistance A ₁ of the epitaxial layer 3 is set lower than the specific resistance A ₂ of the buried diffusion layer 4.
In this way, in the region where the depletion layer of the PN junction J ₁ mainly extends,
By implanting the P conductivity type dopant into the N ⁺⁺ conductivity type semiconductor substrate 2, the N ⁻ conductivity type diffusion layer 4 having a relatively high specific resistance can be formed. Therefore, the specific resistance A ₁ of the epitaxial layer 3 is reduced. And the specific resistance A ₂ of the diffusion layer 4 is A ₁ <
Since it can be set to A ₂ , the specific resistance A of the epitaxial layer 3 is
_{Even if 1} is a low specific resistance, a large capacitance variable ratio can be set.

Next, with reference to FIG. 1, a method of manufacturing the variable capacitance diode of the present invention will be described based on the manufacturing process. The first manufacturing process is performed on the N conductive type semiconductor substrate 2
Then, a P-conductivity type impurity element (dopant) is implanted by ion implantation using a silicon dioxide film formed by heat treatment as a mask, and an annealing process is performed to form a buried diffusion layer 4 of N ⁻ , N ⁻ conductivity type. This is a step of forming an ion implantation layer. In the first production process, N P conductivity type dopant ion implanted into the semiconductor substrate 2 having a relatively high resistivity characteristic offset by the conductivity type of the semiconductor substrate 2 ^-, N ^- conductivity type It becomes the ion-implanted layer.
The ion-implanted layer serving as the diffusion layer 4 may be formed not only by the ion-implantation method but also by a deposit drive-in process. The second manufacturing process is a vapor phase growth process in which the N ⁺ conductivity type epitaxial layer 3 having a relatively low specific resistance is formed on the semiconductor substrate 2 by an epitaxial growth method. By the second step, the ion implantation layer is diffused to form the N ⁻ and N ⁻ conductive type diffusion layers 4. In the third manufacturing process, the semiconductor substrate 1 is subjected to thermal oxidation treatment to form a thermal oxide film (silicon dioxide film) 7 on the main surface of the semiconductor substrate 1, and an etching process is performed to perform the next diffusion process. This is a step of forming the opening 7 ₁ . or,
Without using the aperture ₇₁ of the thermal oxide film as a mask, if performed by ion implantation, without this step, by masking the reticle or resist film or the like in the next step by ion implantation, an annealing step After that, a diffusion layer is formed. Fourth
The manufacturing process, by ion implantation through the opening ₇₁ of the thermal oxide film 7 as a mask, implantation of N conductivity type dopant, followed, after the annealing step and the diffusion step, the diffusion layer 5 of the N ⁺⁺ conductivity type It is a process of forming. By this diffusion step, the diffusion layer 4 which is a buried layer comes close to the diffusion layer 5. In the fifth manufacturing process, the silicon dioxide film deposited on the main surface of the opening 7 ₁ is removed by etching, and then a P conductivity type dopant is implanted by an ion implantation process to form a P ⁺⁺ conductivity type diffusion layer 6. Then, a PN junction is formed with the N ^{+ +} conductivity type diffusion layer 5. Further, a P-conductivity type dopant may be implanted by ion implantation without removing the silicon dioxide film. In the sixth manufacturing process, after removing the silicon dioxide film deposited on the main surface of the opening 7 ₁ by heat treatment by etching,
This is an electrode forming step of forming the conductive film 8 by vapor deposition.

The variable capacitance diode shown in FIG. 1 is formed through the first to sixth manufacturing steps as described above. According to this manufacturing process, since the diffusion layer 4 can have a relatively high specific resistance, the epitaxial layer is heavily doped with an N-conductivity type dopant and is used in a normal variable capacitance diode. The specific resistance can be set lower than the specific resistance of the layer. Of course, in these manufacturing steps, it is clear that the reticle or the resist film may be masked in the ion implantation step without using the silicon dioxide film.

FIG. 2 is a sectional view showing another embodiment of the variable capacitance diode of the present invention, and its structure is the same as that of FIG. However, the relationship between the specific resistances of the epitaxial layer 3 ₁ and the diffusion layer 4 ₁ in FIG. 2 is higher than that in the embodiment of FIG. 1, and the epitaxial layer 3 ₁ has a relatively high N ⁻ conductivity type. It is a semiconductor layer with a specific resistance. Also, the diffusion layer 4
Reference numeral ₁ denotes a diffusion layer having a high specific resistance N ⁻ , and the specific resistance of the diffusion layer 4 ₁ is set to a higher value than the specific resistance of the epitaxial layer 3 ₁ .

FIG. 3 is the same in other configurations except that the diffusion layer 4 of FIG. 1 is a diffusion layer 4 ₂ embedded in a pot shape. Regarding the specific resistance relationship between the diffusion layer 4 ₂ and the epitaxial layer 3 ₂ , the diffusion layer 4 ₂ is set to a high value. With such a structure, the minimum capacitance value of the variable capacitance diode can be reduced. Of course, Figure 2
It is also possible to set the relationship between the conductivity type concentration or the specific resistance value of the epitaxial layer 3 ₁ and the diffusion layer 4 ₁ as in the above embodiment. That is, in the variable capacitance diode of the present invention, the diffusion layers 4, 4 ₁ , 4 ₂ which are regions where the void layer mainly extends can be set higher than the specific resistance of the epitaxial layers 3, 3 ₁ , 3 _2. Therefore, even if the epitaxial layers 3, 3 ₁ , and 3 ₂ have low specific resistance, the epitaxial layers 3, 3 ₁ and 3 ₂ can have capacitance characteristics with a large capacitance variable ratio.

[0011]

The variable capacitance diode of the present invention is
^The buried diffusion layer formed at the boundary between the ⁺ (N ⁻ ) conductivity type epitaxial layer and the N ⁺⁺ conductivity type semiconductor substrate is enhanced by ion-implanting the P conductivity type dopant into the semiconductor substrate. Since an N ⁻ (N ⁻ ) conductivity type buried diffusion layer having a specific resistance is formed, the epitaxial layer may be a semiconductor layer having a relatively low specific resistance. Therefore, even if the epitaxial layer is a semiconductor layer having a relatively low resistivity which is easy to manufacture, the impurity concentration of the diffusion layer in which the main depletion layer of the varactor diode is formed should be high. Therefore, there is an advantage that it is possible to provide a variable capacitance diode capable of setting a large capacitance change without using an epitaxial layer having a characteristic of high specific resistance.
Further, as shown in FIG. 5, the yield of the epitaxial layer deteriorates as the specific resistance becomes higher than 10 Ωcm.
The variable-capacitance diode of the present invention also has the effect of improving the yield because the epitaxial layer may have a low specific resistance. Moreover, since the concentration of the dopant for forming the epitaxial layer can be increased, there is also an advantage that the manufacturing cost of the variable capacitance diode can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a variable capacitance diode of the present invention.

FIG. 2 is a sectional view showing another embodiment of the variable capacitance diode of the present invention.

FIG. 3 is a sectional view showing another embodiment of the variable capacitance diode of the present invention.

FIG. 4 is a cross-sectional view showing an example of a conventional variable capacitance diode.

FIG. 5 is a diagram showing a yield of an epitaxial layer with respect to a specific resistance.

[Explanation of symbols]

1 Semiconductor Base 2 Semiconductor Substrate 3,3 _1, 3 ₂ Epitaxial Layer 4,4 _1, 4 ₂ Diffusion Layer 5 N ⁺⁺ Conductive Diffusion Layer 6 P ⁺⁺ Conductive Diffusion Layer 7 Thermal Oxide Film 7 ₁ Opening 8 Conductor film

Claims (5)

[Claims] 1. In a variable capacitance diode, a PN junction is formed in a first conductivity type epitaxial layer formed on a first conductivity type semiconductor substrate, and a first conductivity type semiconductor substrate immediately below the PN junction is formed. The first conductivity type first diffusion layer having a resistivity higher than that of the epitaxial layer is formed by diffusing an impurity element of the second conductivity type at the boundary with the epitaxial layer of the first conductivity type. Variable capacitance diode. 2. In a variable capacitance diode, a semiconductor substrate of a first conductivity type, a first conductivity type epitaxial layer formed on the semiconductor substrate, and a boundary between the semiconductor substrate and the epitaxial layer A first diffusion layer of a first conductivity type having a resistivity lower than that of the epitaxial layer formed by diffusing an impurity element of a two conductivity type, and a resistivity of the same conductivity type as the epitaxial layer Low, the second diffusion layer of the first conductivity type that reaches the first diffusion layer, the third diffusion layer of the second conductivity type that covers the second diffusion layer and forms a PN junction, A variable capacitance diode comprising a conductor film deposited on the main surface of a third diffusion layer. 3. The variable capacitance diode according to claim 2, wherein the first diffusion layers are arranged in a pot shape. 4. A method of manufacturing a variable capacitance diode, wherein an impurity element of a second conductivity type is ion-implanted into a semiconductor substrate of a first conductivity type and diffused through an annealing process to obtain a first conductivity of a high specific resistance. First diffusion step of forming a diffusion layer of the first type, and an epitaxial layer doped with an impurity element of the first conductivity type is vapor-phase grown on the semiconductor substrate on which the first diffusion layer is formed to form a semiconductor substrate. A step of heat treating the semiconductor substrate to form a thermal oxide film on its main surface, and forming an opening in the thermal oxide film by etching;
A second diffusion that forms a second diffusion layer of the first conductivity type so as to be closer to the first diffusion layer through a thermal diffusion process by diffusing an impurity element at a higher concentration than the epitaxial layer through the opening. A step of removing the thermal oxide film formed in the opening, diffusing an impurity element of the second conductivity type so as to cover the second diffusion layer, and forming a second diffusion layer of the first conductivity type. And a third diffusion step of forming a third diffusion layer of the second conductivity type forming a PN junction, and a step of removing the thermal oxide film formed in the opening to form a conductive film. A method of manufacturing a variable capacitance diode having a feature. 5. A method of manufacturing a variable capacitance diode, wherein a second conductivity type impurity element is ion-implanted into a first conductivity type semiconductor substrate and diffused through an annealing process to obtain a high conductivity first conductivity type. First diffusion step of forming a diffusion layer of the first type, and an epitaxial layer doped with an impurity element of the first conductivity type is vapor-phase grown on the semiconductor substrate on which the first diffusion layer is formed to form a semiconductor substrate. A step of heat-treating the semiconductor substrate, ion-implanting an impurity element into the main surface of the semiconductor substrate at a concentration higher than that of the epitaxial layer using a reticle or a resist film as a mask, and performing a diffusion step so that the impurity element comes close to the first diffusion layer. A second diffusion step of forming a second diffusion layer of the first conductivity type, and a second diffusion step using a reticle or a resist film as a mask after removing the thermal oxide film formed on the main surface of the semiconductor substrate. A third diffusion step of ion-implanting and diffusing a second conductivity type impurity element so as to cover the second diffusion layer to form a second conductivity type third diffusion layer that forms a PN junction with the second diffusion layer; And a step of removing a thermal oxide film on the main surface of the third diffusion layer to form a conductive film.