JPH05166754A - Manufacture or semiconductor device - Google Patents
Manufacture or semiconductor deviceInfo
- Publication number
- JPH05166754A JPH05166754A JP33517191A JP33517191A JPH05166754A JP H05166754 A JPH05166754 A JP H05166754A JP 33517191 A JP33517191 A JP 33517191A JP 33517191 A JP33517191 A JP 33517191A JP H05166754 A JPH05166754 A JP H05166754A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- selective growth
- film
- contact hole
- tungsten
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は半導体装置の製造方法
に関し、さらに詳しくは、MOSトランジスタ、バイポ
ーラトランジスタ等のLSIにおける深さの異なるコン
タクトホールに同時にタングステンを埋め込むコンタク
ト埋め込み技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a contact embedding technique for simultaneously embedding tungsten in contact holes having different depths in LSIs such as MOS transistors and bipolar transistors.
【0002】[0002]
【従来の技術及び発明が解決しようとする課題】従来こ
の種の埋め込み方法は、図6に示すように、上下の絶縁
膜41,42からなる層間絶縁膜間に深さの異なるコン
タクトホール43,44をタングステン膜45で埋め込
む方法が採用されている。しかし、 (i)タングステンは、コンタクトホール43,44の
底部から選択的に成長するから、浅いコンタクトホール
44にタングステン膜45が埋め込まれても深いコンタ
クトホール43は未だタングステンが埋め込まれておら
ず、コンタクトホール43,44上の平坦化が難しい。 (ii)しかもタングステン膜45は、Si膜やWSi膜
あるいはポリシリコン膜の下地膜46によって成長膜厚
が異なり、膜厚の成長が不均一である。 (iii)図7に示すように、絶縁膜53に設けたコンタク
トホール54の下地が、例えばn+ 層52を有するSi
基板51であると、タングステン膜55の選択成長時に
Siとの反応を抑制することができずに接合リークを引
き起こすおそれがある。 (iv)また、タングステンの堆積比が遅くなり、単位時
間にウェハを処理する枚数が、いわゆるスループットが
悪くなるおそれがある。2. Description of the Related Art In the conventional filling method of this type, as shown in FIG. 6, contact holes 43 having different depths are formed between interlayer insulating films composed of upper and lower insulating films 41, 42. A method of embedding 44 with a tungsten film 45 is adopted. However, (i) since tungsten selectively grows from the bottoms of the contact holes 43 and 44, even if the tungsten film 45 is embedded in the shallow contact hole 44, the deep contact hole 43 is not yet embedded with tungsten, It is difficult to flatten the contact holes 43 and 44. (Ii) Moreover, the growth thickness of the tungsten film 45 varies depending on the underlying film 46 of the Si film, the WSi film, or the polysilicon film, and the growth of the film thickness is uneven. (Iii) As shown in FIG. 7, the base of the contact hole 54 provided in the insulating film 53 is, for example, Si having the n + layer 52.
When the substrate 51 is used, the reaction with Si cannot be suppressed during the selective growth of the tungsten film 55, which may cause a junction leak. (Iv) In addition, the deposition rate of tungsten becomes slow, and the number of wafers processed per unit time may deteriorate so-called throughput.
【0003】[0003]
【課題を解決するための手段及びその作用】この発明
は、トランジスタの上層配線と下層配線、及び/又は半
導体基板の不純物拡散層とを導通させるためのコンタク
トホールに導電材料を選択的に成長させるに際して、コ
ンタクトホールを含む半導体基板上の全面に、導電材料
の成長が可能で導電膜の選択成長の種となる選択成長下
地層を積層し、続いて、イオン注入及び熱処理を順次付
してコンタクトホールの側壁を除く選択成長下地層の部
分を、導電材料の成長を抑制しうる非選択成長下地層に
形成し、しかる後、導電材料の選択成長を行ってコンタ
クトホールを導電膜で埋め込むことからなる半導体装置
の製造方法である。すなわち、この発明は、コンタクト
ホールの側壁にのみ選択成長の種となる選択成長下地層
を積層し、側壁から導電膜を選択成長するようにしたも
のである。この発明において、例えば図3で3つの深さ
の異なるコンタクトホール31,32,33を同時にタ
ングステンで埋め込むに際して、各コンタクトホール3
1,32,33の側壁に選択成長下地層34,35,3
6の部分が形成される。一方、各コンタクトホール3
1,32,33の底部や各コンタクトホール間の平坦部
38には非選択成長下地層34a,34b、35a,3
5b、36a,36bが形成される。この非選択成長下
地層は、例えばイオン注入を行うことで形成される。す
なわち、半導体基板上の全面に形成される選択成長下地
層にコンタクトホールの側壁には注入されないようにし
てイオン注入が行われる。その結果、選択成長下地層の
一部が、導電膜の選択成長の種とならない非選択成長下
地層に変質する。そして、続いて、導電材料の選択成長
を行う。この際、選択成長の途中では、図3に示すよう
に各コンタクトホール31,32,33の側壁から導電
膜39aが選択成長する。しかる後、図4に示すように
各コンタクトホール31,32,33を導電膜39で埋
め込まれて選択成長が完了する。これに対して、図5に
示すように、従来は導電膜がコンタクトホール61,
6,63の底部から選択的に成長するから、コンタクト
ホール62では満足のいく導電膜65の埋め込みが行わ
れるにもかかわらず、これより浅いコンタクトホール6
3では導電膜66のはみ出しが発生し、また、最も深い
コンタクトホール61では導電膜64の埋め込み不足が
起こるから、コンタクトホール上の平坦化が難しかっ
た。この発明ではこれらの問題点が解消される。According to the present invention, a conductive material is selectively grown in a contact hole for electrically connecting an upper wiring and a lower wiring of a transistor and / or an impurity diffusion layer of a semiconductor substrate. At this time, a selective growth underlayer, which is capable of growing a conductive material and is a seed for selective growth of a conductive film, is stacked on the entire surface of the semiconductor substrate including the contact holes, and then ion implantation and heat treatment are sequentially applied to the contact. Since the part of the selective growth underlayer other than the side wall of the hole is formed as a non-selective growth underlayer capable of suppressing the growth of the conductive material, the conductive material is selectively grown to fill the contact hole with the conductive film. Another method of manufacturing a semiconductor device. That is, according to the present invention, a selective growth underlayer serving as a seed for selective growth is stacked only on the side wall of the contact hole, and the conductive film is selectively grown from the side wall. In the present invention, for example, when three contact holes 31, 32, 33 having different depths are simultaneously filled with tungsten in FIG.
Selective growth underlayers 34, 35, 3 on the sidewalls of 1, 32, 33
6 parts are formed. On the other hand, each contact hole 3
The non-selective growth underlayers 34a, 34b, 35a, 3 are formed on the bottom portions of 1, 32, 33 and the flat portion 38 between the contact holes.
5b, 36a, 36b are formed. This non-selective growth base layer is formed by performing ion implantation, for example. That is, ion implantation is performed so that the selective growth underlayer formed on the entire surface of the semiconductor substrate is not implanted into the sidewall of the contact hole. As a result, a part of the selective growth underlayer changes into a non-selective growth underlayer that does not become a seed for selective growth of the conductive film. Then, the conductive material is selectively grown. At this time, during the selective growth, as shown in FIG. 3, the conductive film 39a is selectively grown from the sidewalls of the contact holes 31, 32, and 33. Then, as shown in FIG. 4, the contact holes 31, 32, and 33 are filled with a conductive film 39 to complete the selective growth. On the other hand, as shown in FIG.
Since the growth selectively occurs from the bottoms of the contact holes 6 and 63, the contact holes 62 are shallower than the contact holes 6 although the conductive film 65 is sufficiently filled.
In Example 3, the conductive film 66 protruded, and the conductive film 64 was insufficiently embedded in the deepest contact hole 61, so that it was difficult to flatten the contact hole. The present invention solves these problems.
【0004】[0004]
【実施例】以下この発明の実施例について説明する。な
お、これによってこの発明は限定を受けるものではな
い。MOSトランジスタのゲート1及びそのSi基板2
の不純物拡散層3とを導通させるための浅いコンタクト
ホール4及び深いコンタクトホール5にタングステン
(導電材料)を選択的に成長させるに際して、まず、図
1に示すように、コンタクトホール4,5を含むSi基
板2上の全面に、選択成長の種となるTi層(選択成長
下地層)6を積層する。この際、Ti層の膜厚を500
〜1000Åに形成するのが好ましい。又、浅いコンタ
クトホール4の深さは0.3μmであり、開口径は0.
3μmであり、深いコンタクトホール5のそれは1.0
〜2.0μmが好ましいが、本実施例では1.5μmで
あり、開口径は0.3μmである。続いて、イオン注入
及び熱処理を順次付してコンタクトホール4,5の側壁
4a,5aに積層されたTi層6を除くTi層6の部分
を、非選択成長下地層7に形成する(図1参照)。この
際、イオン注入を注入角0度で行って窒素イオンを10
〜50keVの注入エネルギで、かつ1015〜1016c
m-2のイオン注入量で行われる。その結果、非選択成長
下地層7としてTiN膜を形成する。このTiN膜はT
i層6の表層(数10Å程度)だけに形成しても良い。
また、窒素イオンの代わりに酸素イオンを用いても良
い。図1の本実施例では側壁4a,5a以外の領域のT
i層6の表層に非選択成長下地層としてのTiN膜7が
形成されているものが示されている。また、熱処理はR
TA処理を用い、N2 の雰囲気下で、300〜700℃
の熱処理温度が数分の短時間で付される。また、炉アニ
ールでも良い。続いて、タングステンの選択成長を行っ
てコンタクトホール4.5をタングステン膜(導電膜)
8で埋め込む(図2参照)。この際、WF6 とH2 を約
250℃〜300℃で反応させてコンタクトホール4,
5の側壁4a,5aのTi層6上にのみタングステン膜
を形成する。このように本実施例では、下地のゲート1
及びそのSi基板2の不純物拡散層3の存在に関係な
く、かつコンタクトサイズの略半分の膜厚でコンタクト
ホール5をタングステン膜(導電膜)8で埋め込むこと
ができる。Embodiments of the present invention will be described below. The present invention is not limited to this. Gate 1 of MOS transistor and its Si substrate 2
In selectively growing tungsten (conductive material) in the shallow contact hole 4 and the deep contact hole 5 for electrically connecting to the impurity diffusion layer 3 of the above, first, as shown in FIG. 1, the contact holes 4 and 5 are included. On the entire surface of the Si substrate 2, a Ti layer (selective growth underlayer) 6 serving as a seed for selective growth is laminated. At this time, the thickness of the Ti layer is 500
It is preferable to form it in the range of 1000 Å. The depth of the shallow contact hole 4 is 0.3 μm, and the opening diameter is 0.
3 μm, that of deep contact hole 5 is 1.0
˜2.0 μm is preferable, but in this embodiment, it is 1.5 μm, and the opening diameter is 0.3 μm. Subsequently, ion implantation and heat treatment are sequentially applied to form a portion of the Ti layer 6 excluding the Ti layer 6 laminated on the sidewalls 4a and 5a of the contact holes 4 and 5 in the non-selective growth underlayer 7 (FIG. 1). reference). At this time, the ion implantation is performed at an implantation angle of 0 degree so that the nitrogen ions are 10 times.
Implant energy of ~ 50 keV and 10 15 ~ 10 16 c
The ion implantation amount is m −2 . As a result, a TiN film is formed as the non-selective growth underlayer 7. This TiN film is T
The i-layer 6 may be formed only on the surface layer (several tens of liters).
Further, oxygen ions may be used instead of nitrogen ions. In this embodiment shown in FIG. 1, T in the region other than the sidewalls 4a and 5a is
It is shown that the TiN film 7 as a non-selective growth underlayer is formed on the surface of the i layer 6. Also, the heat treatment is R
300 to 700 ° C. under N 2 atmosphere using TA treatment
The heat treatment temperature is applied in a short time of several minutes. Furnace annealing may also be used. Then, selective growth of tungsten is performed to form the contact hole 4.5 in a tungsten film (conductive film).
8 (see FIG. 2). At this time, WF 6 and H 2 are reacted at about 250 ° C. to 300 ° C.
The tungsten film is formed only on the Ti layer 6 on the side walls 4a and 5a of the metal film 5. As described above, in this embodiment, the underlying gate 1
Also, regardless of the presence of the impurity diffusion layer 3 of the Si substrate 2, the contact hole 5 can be filled with the tungsten film (conductive film) 8 with a film thickness of about half the contact size.
【0005】[0005]
【発明の効果】以上のようにこの発明によれば、コンタ
クトホールの側壁にのみ選択成長の種となる選択成長下
地層を積層し、側壁から導電膜を選択成長するようにし
たので、下地膜によって成長膜厚が異っても異なる深さ
のコンタクトホール上の平坦化が可能になる。しかもコ
ンタクトホールの下地が、例えば半導体基板の不純物拡
散層であっても導電膜の選択成長時にSiとの反応を抑
制して接合リークを引き起こすおそれがなくなる。ま
た、スループットが悪くなるおそれはなくなる。As described above, according to the present invention, the selective growth underlayer serving as a seed for selective growth is laminated only on the side wall of the contact hole, and the conductive film is selectively grown from the side wall. Thus, even if the grown film thickness is different, it is possible to flatten the contact hole at different depths. Moreover, even if the base of the contact hole is, for example, an impurity diffusion layer of the semiconductor substrate, there is no possibility of suppressing the reaction with Si during selective growth of the conductive film and causing a junction leak. In addition, there is no fear that throughput will deteriorate.
【図1】この発明の一実施例の製造方法の第1ステップ
を示す構成説明図である。FIG. 1 is a structural explanatory view showing a first step of a manufacturing method according to an embodiment of the present invention.
【図2】上記実施例における製造方法の第2ステップを
示す構成説明図である。FIG. 2 is a structural explanatory view showing a second step of the manufacturing method in the above embodiment.
【図3】この発明の製造方法の原理を示す製造工程説明
図である。FIG. 3 is a manufacturing process explanatory view showing the principle of the manufacturing method of the present invention.
【図4】図3の工程に続くこの発明の製造方法の原理を
示す製造工程説明図である。FIG. 4 is a manufacturing process explanatory view showing the principle of the manufacturing method of the invention following the process of FIG. 3;
【図5】従来の製造方法の原理を示す製造工程説明図で
ある。FIG. 5 is a manufacturing process explanatory view showing the principle of a conventional manufacturing method.
【図6】従来の製造方法の1ステップを示す構成説明図
である。FIG. 6 is a configuration explanatory view showing one step of a conventional manufacturing method.
【図7】従来の製造方法の1ステップを示す構成説明図
である。FIG. 7 is a structural explanatory view showing one step of a conventional manufacturing method.
1 ゲート 2 Si基板 3 不純物拡散層 4 浅いコンタクトホール 5 深いコンタクトホール 6 Ti層(選択成長下地層) 7 TiN層(非選択成長下地層) 8 タングステン膜(導電膜) 1 gate 2 Si substrate 3 impurity diffusion layer 4 shallow contact hole 5 deep contact hole 6 Ti layer (selective growth underlayer) 7 TiN layer (non-selective growth underlayer) 8 tungsten film (conductive film)
Claims (4)
び/又はゲート及び半導体基板の不純物拡散層とを導通
させるためのコンタクトホールに導電材料を選択的に成
長させるに際して、コンタクトホールを含む半導体基板
上の全面に、導電材料の成長が可能で導電膜の選択成長
の種となる選択成長下地層を積層し、続いて、イオン注
入及び熱処理を順次付してコンタクトホールの側壁を除
く選択成長下地層の部分を、導電材料の成長を抑制しう
る非選択成長下地層に形成し、しかる後、導電材料の選
択成長を行ってコンタクトホールを導電膜で埋め込むこ
とからなる半導体装置の製造方法。1. When a conductive material is selectively grown in a contact hole for electrically connecting an upper layer wiring and a lower layer wiring of a transistor, and / or a gate and an impurity diffusion layer of a semiconductor substrate, a semiconductor substrate including a contact hole is formed. A selective growth underlayer that allows growth of a conductive material and serves as a seed for selective growth of a conductive film is laminated on the entire surface of the substrate, and then ion implantation and heat treatment are sequentially performed to remove the sidewalls of the contact holes. Is formed in a non-selective growth underlayer capable of suppressing the growth of the conductive material, and then the conductive material is selectively grown to fill the contact hole with the conductive film.
長下地層がTi層、タングステン層又はSi層である請
求項1による半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the conductive film is a tungsten film and the selective growth underlayer is a Ti layer, a tungsten layer or a Si layer.
層である請求項1による半導体装置の製造方法。3. The non-selective growth underlayer is a TiO 2 layer or TiN.
The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a layer.
法で行われる請求項3による半導体装置の製造方法。4. The RTA in which the heat treatment is a short-time anneal.
The method for manufacturing a semiconductor device according to claim 3, which is performed by a method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33517191A JPH05166754A (en) | 1991-12-18 | 1991-12-18 | Manufacture or semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33517191A JPH05166754A (en) | 1991-12-18 | 1991-12-18 | Manufacture or semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05166754A true JPH05166754A (en) | 1993-07-02 |
Family
ID=18285556
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33517191A Pending JPH05166754A (en) | 1991-12-18 | 1991-12-18 | Manufacture or semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05166754A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100400040B1 (en) * | 2000-05-31 | 2003-09-29 | 삼성전자주식회사 | Metal wiring method of semiconductor device |
CN103681466A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Method for making interconnected structure |
JP2022504574A (en) * | 2018-10-10 | 2022-01-13 | 東京エレクトロン株式会社 | A method of filling a concave feature in a semiconductor device with a low resistivity metal |
-
1991
- 1991-12-18 JP JP33517191A patent/JPH05166754A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100400040B1 (en) * | 2000-05-31 | 2003-09-29 | 삼성전자주식회사 | Metal wiring method of semiconductor device |
CN103681466A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Method for making interconnected structure |
JP2022504574A (en) * | 2018-10-10 | 2022-01-13 | 東京エレクトロン株式会社 | A method of filling a concave feature in a semiconductor device with a low resistivity metal |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5326722A (en) | Polysilicon contact | |
US4558507A (en) | Method of manufacturing semiconductor device | |
CN100461414C (en) | Semiconductor device and manufacturing method thereof | |
JPH01133368A (en) | Method of forming polycrystalline silicon gate fet | |
JPH04211121A (en) | Semiconductor device and fabrication thereof | |
JPS63170969A (en) | Nonvolatile memory | |
US9608106B2 (en) | Semiconductor device and method for forming the same | |
JPH0465122A (en) | Manufacture of semiconductor device | |
JP2004281781A (en) | Semiconductor substrate, manufacturing method therefor, semiconductor device and manufacturing method therefor | |
US8044470B2 (en) | Semiconductor device and method of fabricating the same | |
JPH10125909A (en) | Manufacture of semiconductor device | |
JP2519837B2 (en) | Semiconductor integrated circuit and manufacturing method thereof | |
JP2892421B2 (en) | Method for manufacturing semiconductor device | |
JP2002124649A (en) | Semiconductor integrated circuit device and the manufacturing method therefor | |
JPH05166754A (en) | Manufacture or semiconductor device | |
KR100745066B1 (en) | Method for fabricating metal plug of semiconductor device | |
JP3125429B2 (en) | Semiconductor device and manufacturing method thereof | |
JPS62290147A (en) | Manufacture of semiconductor device | |
JPH05152449A (en) | Manufacture of semiconductor device | |
JPH0756866B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
KR100705252B1 (en) | Semiconductor device and manufacturging method thereof | |
JP2718450B2 (en) | Method for manufacturing semiconductor device | |
JPS63271972A (en) | Manufacture of thin film transistor | |
JP2002118262A (en) | Semiconductor device and its fabricating method | |
JP2003347308A (en) | Semiconductor device and manufacturing method thereof |