JPH0516660B2 - - Google Patents

Info

Publication number
JPH0516660B2
JPH0516660B2 JP25975284A JP25975284A JPH0516660B2 JP H0516660 B2 JPH0516660 B2 JP H0516660B2 JP 25975284 A JP25975284 A JP 25975284A JP 25975284 A JP25975284 A JP 25975284A JP H0516660 B2 JPH0516660 B2 JP H0516660B2
Authority
JP
Japan
Prior art keywords
temperature
manufacturing
lifetime
semiconductor device
speed semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP25975284A
Other languages
Japanese (ja)
Other versions
JPS61137332A (en
Inventor
Tadao Takano
Seiichi Myagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nihon Inter Electronics Corp
Original Assignee
Nihon Inter Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nihon Inter Electronics Corp filed Critical Nihon Inter Electronics Corp
Priority to JP25975284A priority Critical patent/JPS61137332A/en
Publication of JPS61137332A publication Critical patent/JPS61137332A/en
Publication of JPH0516660B2 publication Critical patent/JPH0516660B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、シリコン半導体基板に注入される
キヤリヤのライフタイムを短縮するためにライフ
タイムキラーとして重金属を拡散する工程を有す
る高速半導体装置の製造方法の改良に関するもの
である。
[Detailed Description of the Invention] [Industrial Application Field] This invention relates to the manufacturing of high-speed semiconductor devices, which includes a step of diffusing heavy metals as a lifetime killer to shorten the lifetime of carriers implanted into a silicon semiconductor substrate. It concerns an improvement in the method.

[従来の技術] 所謂スイツチング電源装置の小型化、高効率化
等のために二次側整流素子の高速、高効率化が要
求され低順方向電圧降下、高速回復特性を有する
素子を得る目的で、シヨツトキー素子や高速整流
素子が用いられているが、さらに高速化、高効率
化を求めて素子自体の改良が続けられている。こ
のような素子の改良は一般に高不純物濃度シリコ
ン半導体基板上に必要な厚みを有するエピタキシ
ヤル層を成長させた素材にキヤリヤのライフタイ
ムを短縮するためにライフタイムリキラーとして
金(Au)、白金(Pt)等の重金属の拡散が行なわ
れる。
[Prior Art] In order to reduce the size and improve efficiency of so-called switching power supplies, high speed and high efficiency secondary side rectifying elements are required, and for the purpose of obtaining elements with low forward voltage drop and high speed recovery characteristics. , Schottky elements and high-speed rectifier elements are used, but improvements to the elements themselves continue to be made in pursuit of even higher speeds and higher efficiency. Improvements in such devices are generally made by growing an epitaxial layer with a required thickness on a highly impurity-concentrated silicon semiconductor substrate, and adding gold (Au) or platinum (as a lifetime rekiller) to shorten the carrier lifetime. Diffusion of heavy metals such as Pt) takes place.

[発明の解決しようとする問題点] 上記の場合、高不純物濃度のエピタキシヤル基
板であることや浅くて高濃度の拡散層のために動
作の目的となる活性領域は結晶中の欠陥部ないし
は異常点に上記重金属の析出等が発生し易く、こ
のために重金属拡散温度の上昇と共に漏れ電流が
生じこの漏れ電流の大きな素子は使用に耐えない
不良品とするので、収率が低下するという問題点
があつた。
[Problems to be solved by the invention] In the above case, due to the epitaxial substrate having a high impurity concentration and the shallow and high concentration diffusion layer, the active region that is the target of operation may be a defective part or an abnormality in the crystal. The problem is that precipitation of the heavy metals mentioned above is likely to occur at the points, and as a result, leakage current occurs as the heavy metal diffusion temperature rises, and devices with a large leakage current are treated as defective products that cannot be used, resulting in a decrease in yield. It was hot.

この発明は上記のような従来のものの問題点を
解消するためになされたもので、半導体装置の漏
れ電流を低減させ、収率を向上させ得る高速半導
体装置の製造方法を提供することを目的とするも
のである。
This invention was made in order to solve the problems of the conventional ones as described above, and its purpose is to provide a method for manufacturing high-speed semiconductor devices that can reduce leakage current of semiconductor devices and improve yield. It is something to do.

[問題点を解決するための手段] この発明にかかる高速半導体装置の製造方法
は、高速半導体装置の製造工程中に複数回繰り返
される酸化膜形成工程の温度を1100℃以下とし、
かつ1100℃から500乃至600℃までの降温を0.5〜
2℃/分の除冷とする工程と、この工程の後、
550乃至600℃の温度で少くとも1時間以上保持す
る熱処理工程とを含むことを特徴とするものであ
る。
[Means for Solving the Problems] A method for manufacturing a high-speed semiconductor device according to the present invention includes: setting the temperature of the oxide film forming step, which is repeated multiple times during the manufacturing process of the high-speed semiconductor device, to 1100° C. or lower;
And the temperature drop from 1100℃ to 500 to 600℃ is 0.5~
A slow cooling step of 2°C/min, and after this step,
It is characterized by including a heat treatment step of holding at a temperature of 550 to 600° C. for at least one hour.

[作用] 重金属拡散工程以前の前記熱処理工程の付加に
よつて重金属拡散時にライフタイムキラーとして
の重金属不純物の半導体基板の一部への異常集中
や分離析出の核となるような結晶格子の異常点あ
るいは異常応力が発生するのが避けられる。
[Effect] By adding the heat treatment step before the heavy metal diffusion step, abnormal concentration of heavy metal impurities as a lifetime killer in a part of the semiconductor substrate during heavy metal diffusion and abnormal points in the crystal lattice that become the nucleus for separation and precipitation are created. Alternatively, generation of abnormal stress can be avoided.

[実施例] 第1図はこの発明の製造方を説明するための工
程図である。
[Example] FIG. 1 is a process diagram for explaining the manufacturing method of the present invention.

同図Aにおいて、まずN+型高濃度シリコン基
板1にN型エピタキシヤル層2を成長させたもの
を用意し、次いて同図Bに示すように上記エピタ
キシヤル基板3を1050℃の温度で所定時間湿潤酸
素雰囲気(Wet O2)中で加熱し、エピタキシヤ
ル基板3に二酸化珪素(SiO2)皮膜4を形成す
る。
In Figure A, an N + type high concentration silicon substrate 1 on which an N type epitaxial layer 2 is grown is first prepared, and then, as shown in Figure B, the epitaxial substrate 3 is grown at a temperature of 1050°C. A silicon dioxide (SiO 2 ) film 4 is formed on the epitaxial substrate 3 by heating in a moist oxygen atmosphere (Wet O 2 ) for a predetermined time.

次いで、上記SiO2皮膜4の形成後、1050℃か
ら600℃まで0.5〜2℃/分の割合で除冷し、この
発明の特徴である熱処理工程に入る。
Next, after forming the SiO 2 film 4, it is gradually cooled from 1050°C to 600°C at a rate of 0.5 to 2°C/min, and enters a heat treatment process that is a feature of the present invention.

すなわち、600℃までの除冷後、上記基板3を
600℃にて1時間以上、好ましくは30時間程度保
持する。
That is, after slowly cooling the substrate 3 to 600°C,
Hold at 600°C for 1 hour or more, preferably about 30 hours.

次いで、同図Cに示すように通常のホトリソ技
術を用いてSiO2皮膜4に所定の大きさの窓明け
5を行ない、P+型アノード層6を形成すべく
1100℃で所定時間WetO2中でボロン拡散を行な
う。
Next, as shown in Figure C, a window 5 of a predetermined size is formed in the SiO 2 film 4 using a normal photolithography technique to form a P + type anode layer 6.
Boron diffusion is performed in WetO 2 at 1100 °C for a predetermined time.

上記の基板3を再び1100℃から600℃まで0.5〜
2℃/分の割合で除冷し、600℃にて1時間以上、
好ましくは30時間程度保持する熱処理(アニー
ル)を施こす。次いで、同図Dに示すようにN++
層7を形成するために1100℃の温度で所定時間
WetO2中で加熱し、その後、1100℃から600℃ま
で0.5〜2℃/分の割合で除冷する。その後、上
記と同様に600℃にて1時間以上、好ましくは30
時間程度保持する。
The above board 3 is heated again from 1100℃ to 600℃ from 0.5 to
Cool slowly at a rate of 2°C/min and hold at 600°C for over 1 hour.
Heat treatment (annealing) is preferably performed for about 30 hours. Next, as shown in figure D, N ++
A predetermined time at a temperature of 1100°C to form layer 7
Heat in WetO 2 and then slowly cool from 1100°C to 600°C at a rate of 0.5-2°C/min. Then, as above, at 600℃ for 1 hour or more, preferably 30℃.
Hold for about an hour.

上記のアニール工程を経た後、キヤリヤのライ
フタイムを短縮するための重金属、例えば白金
(Pt)、金(Au)を用いて周知の方法により所定
時間キラー拡散を行なう。
After the above annealing step, killer diffusion is performed for a predetermined period of time by a well-known method using heavy metals such as platinum (Pt) and gold (Au) to shorten the lifetime of the carrier.

この発明は上記のようにキラー拡散を行う前の
SiO2皮膜形成後の工程で熱処理を施こすことに
よつて、キラー拡散時のキラー不純物の異常集中
や分離析出の核となるような結晶格子の異常点や
異常応力の発生を避けることができる。
This invention is based on the method described above before performing killer diffusion.
By performing heat treatment in the process after forming the SiO 2 film, it is possible to avoid abnormal concentration of killer impurities during killer diffusion and the generation of abnormal points and abnormal stresses in the crystal lattice that can become nuclei for separation and precipitation. .

次に、第2図にこの発明によつて製造した素子
と従来法によつて製造した素子との漏れ電流を比
較したグラフを示す。同図は縦軸に漏れ電流IR
(mA)、横軸に温度Tc(℃)をとり、実線がこの
発明の製造方法によつて製造した素子、点線が従
来の製造方法によつて製造した素子を示し、また
一点鎖線は漏れ電流(リーク)規格を示す。
Next, FIG. 2 shows a graph comparing leakage current between an element manufactured by the present invention and an element manufactured by a conventional method. In the figure, the vertical axis shows the leakage current I R
(mA), the horizontal axis shows the temperature Tc (°C), the solid line shows the device manufactured by the manufacturing method of this invention, the dotted line shows the device manufactured by the conventional manufacturing method, and the dashed line shows the leakage current. (Leak) Indicates standards.

このグラフから明らかなように所定温度tmま
での範囲内ではこの発明の製造方法による素子の
方が従来法による素子に比較して著しく漏れ電流
が少なくなることが分る。
As is clear from this graph, within the range up to the predetermined temperature tm, the leakage current of the device manufactured by the manufacturing method of the present invention is significantly lower than that of the device manufactured by the conventional method.

[発明の効果] この発明は、上記のように高速半導体装置の製
造工程中に複数回繰り返される酸化膜形成工程後
に所定の条件で熱処理を施こすようにしたので、
キラー拡散時にキラー不純物の異常集中、分離析
出の核となるような結晶格子の異常点、異常応力
の応力の発生等が避けられその結果、漏れ電流の
少ない高速半導体装置を製造することができかつ
収率が向上する。
[Effects of the Invention] According to the present invention, heat treatment is performed under predetermined conditions after the oxide film formation step, which is repeated multiple times during the manufacturing process of high-speed semiconductor devices, as described above.
Abnormal concentration of killer impurities during killer diffusion, abnormal points in the crystal lattice that become nuclei for separation and precipitation, and generation of abnormal stress can be avoided, and as a result, high-speed semiconductor devices with low leakage current can be manufactured. Yield is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の製造方法を説明するための
工程図、第2図はこの発明の製造方法による素子
と従来法による素子の漏れ電流の比較したグラフ
である。 図において、1はシリコン基板、2はエピタキ
シヤル層、4は二酸化珪素皮膜である。
FIG. 1 is a process diagram for explaining the manufacturing method of the present invention, and FIG. 2 is a graph comparing the leakage currents of a device manufactured by the manufacturing method of the present invention and a device manufactured by a conventional method. In the figure, 1 is a silicon substrate, 2 is an epitaxial layer, and 4 is a silicon dioxide film.

Claims (1)

【特許請求の範囲】[Claims] 1 シリコン半導体基板内に注入されたキヤリヤ
のライフタイムを短縮するためにライフタイムキ
ラーとして重金属を拡散する工程を有する高速半
導体装置の製造方法において、高速半導体装置の
製造工程中に複数回繰り返される酸化膜形成工程
の温度を1100℃以下とし、かつ1100℃から550乃
至600℃までの降温を0.5〜2℃/分の除冷とする
工程と、この工程の後、連続して550乃至600℃の
温度で少くとも1時間以上保持する熱処理工程と
を含むことを特徴とする高速半導体装置の製造方
法。
1. In a method for manufacturing a high-speed semiconductor device that includes a step of diffusing heavy metals as a lifetime killer to shorten the lifetime of a carrier injected into a silicon semiconductor substrate, oxidation that is repeated multiple times during the manufacturing process of the high-speed semiconductor device The temperature of the film forming process is set to 1100℃ or less, and the temperature is gradually lowered from 1100℃ to 550 to 600℃ by 0.5 to 2℃/min, and after this step, the temperature is continuously lowered to 550 to 600℃. 1. A method for manufacturing a high-speed semiconductor device, comprising a heat treatment step of holding at a temperature for at least one hour or more.
JP25975284A 1984-12-08 1984-12-08 Manufacture of high speed semiconductor device Granted JPS61137332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25975284A JPS61137332A (en) 1984-12-08 1984-12-08 Manufacture of high speed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25975284A JPS61137332A (en) 1984-12-08 1984-12-08 Manufacture of high speed semiconductor device

Publications (2)

Publication Number Publication Date
JPS61137332A JPS61137332A (en) 1986-06-25
JPH0516660B2 true JPH0516660B2 (en) 1993-03-05

Family

ID=17338458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25975284A Granted JPS61137332A (en) 1984-12-08 1984-12-08 Manufacture of high speed semiconductor device

Country Status (1)

Country Link
JP (1) JPS61137332A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2675011B2 (en) * 1987-08-12 1997-11-12 株式会社日立製作所 Heat treatment apparatus and heat treatment method
US5916368A (en) * 1997-02-27 1999-06-29 The Fairchild Corporation Method and apparatus for temperature controlled spin-coating systems

Also Published As

Publication number Publication date
JPS61137332A (en) 1986-06-25

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