JPH051616B2 - - Google Patents
Info
- Publication number
- JPH051616B2 JPH051616B2 JP58146330A JP14633083A JPH051616B2 JP H051616 B2 JPH051616 B2 JP H051616B2 JP 58146330 A JP58146330 A JP 58146330A JP 14633083 A JP14633083 A JP 14633083A JP H051616 B2 JPH051616 B2 JP H051616B2
- Authority
- JP
- Japan
- Prior art keywords
- bump
- chip
- semiconductor chip
- elliptical
- mounting board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000002844 melting Methods 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 230000005855 radiation Effects 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05555—Shape in top view being circular or elliptic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0614—Circular array, i.e. array with radial symmetry
- H01L2224/06141—Circular array, i.e. array with radial symmetry being uniform, i.e. having a uniform pitch across the array
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0614—Circular array, i.e. array with radial symmetry
- H01L2224/06144—Circular array, i.e. array with radial symmetry covering only portions of the surface to be connected
- H01L2224/06145—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13014—Shape in top view being circular or elliptic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1414—Circular array, i.e. array with radial symmetry
- H01L2224/14141—Circular array, i.e. array with radial symmetry being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1414—Circular array, i.e. array with radial symmetry
- H01L2224/14143—Circular array, i.e. array with radial symmetry with a staggered arrangement, e.g. depopulated array
- H01L2224/14145—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体チツプ、パツケージ、低融点
金属バンプからなるワイヤレス方式のフリツプチ
ツプ型半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a wireless flip-chip semiconductor device comprising a semiconductor chip, a package, and low-melting point metal bumps.
大型コンピユータ用大規模集積回路（LSI）等
の半導体装置は、内部多層微細配線技術の確立と
平行し、その実装面においてもワイヤポンデイン
グ方式からワイヤレス方式の半田等の低融点金属
のバンプ電極を用いたフリツプチツプ方式のボン
デイングによる実装（以下、単にフリツプチツプ
ボンデイングという）による高速高集積化をはか
る要求が高まつてきている。この要求を満すため
には、高信頼度でかつ長寿命のフリツプチツプボ
ンデイング技術を確立する必要がある。
Semiconductor devices such as large-scale integrated circuits (LSIs) for large-scale computers have been developed in parallel with the establishment of internal multilayer fine wiring technology, and their mounting has also changed from wire bonding to wireless methods using low-melting point metal bump electrodes such as solder. There is an increasing demand for high-speed, high-integration implementation using flip-chip bonding (hereinafter simply referred to as flip-chip bonding). In order to meet this requirement, it is necessary to establish flip-chip bonding technology that is highly reliable and has a long life.
そこで、本発明者は、フリツプチツプボンデイ
ング技術について以下に述べるような技術を開発
した。 Therefore, the present inventor has developed a flip-chip bonding technique as described below.
すなわち、半導体チツプ（以下、単にチツプと
いう）側及びパツケージ側に円形の電極を形成
し、両者を半田等の部分球状の低融点金属バンプ
電極（以下、単にバンプという）によつて電気
的、機械的に結合するものである。 That is, circular electrodes are formed on the semiconductor chip (hereinafter simply referred to as the chip) side and the package side, and both are connected electrically and mechanically by partially spherical low-melting point metal bump electrodes such as solder (hereinafter simply referred to as bumps). It is something that connects to each other.
しかし、前記の技術は、以下の欠点を有するこ
とが本発明者により明らかにされた。すなわち、
チツプとパツケージ間の接続部であるバンプの形
状がが部分球状であるため、チツプ又はパツケー
ジに平行な方向に対する強度が等方的となる。そ
のため、バンプの配置分布の中心から最も離れた
バンプは、温度サイクルにおけるチツプとパツケ
ージとの熱膨張率の差によつて発生する応力を受
けて破断不良をおこしやすい欠点があつた。 However, the inventor revealed that the above technique has the following drawbacks. That is,
Since the shape of the bump, which is the connection between the chip and the package, is partially spherical, the strength in the direction parallel to the chip or the package is isotropic. Therefore, the bumps farthest from the center of the bump arrangement distribution have the disadvantage that they are susceptible to stress caused by the difference in coefficient of thermal expansion between the chip and the package during temperature cycles, and are susceptible to failure.
〔発明の目的〕
本発明の目的は、チツプとパツケージとの熱膨
張率の差によつて発生する応力に耐え得ることが
可能なバンプを具備したフリツプチツプ型半導体
装置を提供することにある。[Object of the Invention] An object of the present invention is to provide a flip-chip type semiconductor device having bumps that can withstand stress caused by the difference in coefficient of thermal expansion between the chip and the package.
本発明の前記ならびにその他の目的と新規な特
徴は、本明細書の記述及び添付図面によつて明ら
かになるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なも
のの概要を簡単に説明すれば、下記のとおりであ
る。
A brief overview of typical inventions disclosed in this application is as follows.
すなわち、フリツプチツプ型半導体装置におい
て、チツプとパツケージとの熱膨張率の差によつ
て発生する応力がバンプに加わる方向とほぼ同一
方向に、他の方向に比較して、特に大きな強度を
有するバンプを形成することにより、バンプの破
断不良を防止するようにしたものである。 In other words, in a flip-chip type semiconductor device, a bump having particularly high strength is formed in approximately the same direction as the direction in which stress generated due to the difference in coefficient of thermal expansion between the chip and the package is applied to the bump, compared to other directions. By forming the bump, it is possible to prevent failure of the bump from breaking.
第１図及び第２図は、本発明のフリツプチツプ
型半導体装置の一実施例を説明するための図であ
り、第１図は、そのチツプの平面図、第２図は、
そのチツプをパツケージに実装した場合の側面図
である。
1 and 2 are diagrams for explaining an embodiment of the flip-chip type semiconductor device of the present invention. FIG. 1 is a plan view of the chip, and FIG.
FIG. 3 is a side view of the chip mounted on a package.
本実施例は、バンプを楕円球状にするためにチ
ツプ１の所定表面側に楕円形電極を形成し、その
楕円形電極上に、第１図に示すように、バンプ２
を設ける。そして、パツケージの一部である実装
基板３の所定表面側に設けられている楕円形電極
と前記バンプ２を、第２図に示すように、電気
的、機械的に結合してフリツプチツプ型半導体装
置を構成したものである。 In this embodiment, an elliptical electrode is formed on a predetermined surface side of the chip 1 in order to make the bump into an ellipsoidal shape, and the bump 2 is placed on the elliptical electrode as shown in FIG.
will be established. Then, as shown in FIG. 2, the elliptical electrode provided on a predetermined surface side of the mounting board 3, which is a part of the package, and the bump 2 are electrically and mechanically coupled to form a flip-chip semiconductor device. It is composed of
前記バンプ２の形成は、部分楕円球状をなして
おり、それをチツプ１に平行な面で切ると、その
断面は楕円形状をなしている。また、チツプ１と
垂直な面でかつ前記楕円形状の短軸に沿つた面
（第１図のＡ−Ａ線で切つた面）で前記バンプ２
を切ると、その断面Ａは、第３図に示すような縦
長楕円形状をなしており、チツプ１と垂直な面で
かつ前記楕円形状の長軸に沿つた面（第１図のＢ
−Ｂ線で切つた面）でバンプ２を切ると、その断
面Ｂは、第４図に示すような横長楕円形状をなし
ている。 The bump 2 is formed into a partially elliptical spherical shape, and when it is cut along a plane parallel to the chip 1, its cross section is an ellipse. Further, the bump 2 is formed on a surface perpendicular to the chip 1 and along the short axis of the elliptical shape (a surface cut along line A-A in FIG. 1).
When cut, its cross section A has a vertically elongated elliptical shape as shown in FIG.
- When the bump 2 is cut along the line B), the cross section B has a horizontally elongated elliptical shape as shown in FIG.
また、前記バンプ２の配置は、第１図に示すよ
うに、バンプ２の配置分布の中心４とバンプ２と
を結ぶ直線方向にバンプ２の楕円形状の長軸を合
わせる。すなわち、前記バンプ２の配置分布の中
心４からの放射線上にバンプ２の長軸が一致する
ように各バンプ２を配置する。 Further, as shown in FIG. 1, the arrangement of the bumps 2 is such that the long axis of the elliptical shape of the bumps 2 is aligned with a straight line connecting the bumps 2 and the center 4 of the arrangement distribution of the bumps 2. That is, each bump 2 is arranged so that the long axis of the bump 2 coincides with the radiation from the center 4 of the arrangement distribution of the bumps 2.
なお、前記バンプ２の配置は、必要に応じてチ
ツプ１の外周部のみでなく、前記放射線上のいず
れの位置にも設けて全面バンプを形成することも
可能である。また、中心４はチツプ１の中心（重
心）に一致するようにするのがよい。 Incidentally, the bumps 2 may be arranged not only on the outer periphery of the chip 1 but also at any position on the radiation line to form a full-surface bump, if necessary. Further, it is preferable that the center 4 coincides with the center (center of gravity) of the chip 1.
次に、本実施例のバンプ２の作用について説明
する。 Next, the effect of the bump 2 of this embodiment will be explained.
前記部分楕円球状を有するバンプ２は、チツプ
１と実装基板３との熱膨張係数の差により第５図
に示すような応力F1が断面Ｂに加わる。このバ
ンプ２に加わる応力F1は、第６図に示すバンプ
２と同一体積を有する部分球状のバンプ２Ａに加
わる応力F2に比較して、前記応力F1が加わる方
向におけるバンプ２の強度がバンプ２の長くなつ
た分だけ分散される。なお、バンプ２と実装基板
３との間の応力は第５図、第６図のようにではな
くバンプ２内のみに働くこともありうる。 In the bump 2 having a partially elliptical spherical shape, a stress F1 as shown in FIG. 5 is applied to the cross section B due to the difference in thermal expansion coefficient between the chip 1 and the mounting board 3 . The stress F 1 applied to the bump 2 increases the strength of the bump 2 in the direction in which the stress F 1 is applied, compared to the stress F 2 applied to the partially spherical bump 2A having the same volume as the bump 2 shown in FIG. It is dispersed by the length of bump 2. Note that the stress between the bump 2 and the mounting board 3 may act only within the bump 2 instead of as shown in FIGS. 5 and 6.
これにより、いずれの場合でもバンプ２に加え
られる応力は△Ｆだけ減少させることができるた
め、温度サイクルによるバンプ２の破断不良が生
じにくくなる。 As a result, in any case, the stress applied to the bump 2 can be reduced by ΔF, making it difficult for the bump 2 to break due to temperature cycles.
また、第３図に示すように、バンプ２の断面Ａ
の部分でのバンプ２とチツプ１又はバンプ２と実
装基板３の接触角θ1は、破線で示す部分球状のバ
ンプの接触面θ2より大きくなるので、その強度が
部分球状のバンプより増大しバンプ２の破断不良
が生じにくくなる。 In addition, as shown in FIG. 3, the cross section A of the bump 2
The contact angle θ 1 between the bump 2 and the chip 1 or the bump 2 and the mounting board 3 at the part is larger than the contact surface θ 2 of the partially spherical bump shown by the broken line, so its strength is greater than that of the partially spherical bump. Breakage defects of the bumps 2 are less likely to occur.
チツプとパツケージとの熱膨張率の差等によつ
て生じる応力が加わる方向に、その方向に対して
特に強い強度を有するバンプを設けることによ
り、バンプの破断不良を防止することができ、フ
リツプチツプ型半導体装置の信頼性を向上するこ
とができる。
By providing bumps with particularly strong strength in the direction in which stress is applied due to the difference in coefficient of thermal expansion between the chip and the package, failure of the bumps can be prevented, and flip-chip type The reliability of a semiconductor device can be improved.
熱膨張率差による応力の働く方向以外に働く応
力に対しては、実装基板とバンプとの接触角θを
大きくしているので、従来より強いバンプとする
ことができる。 With respect to stress acting in a direction other than the stress acting direction due to the difference in coefficient of thermal expansion, the contact angle θ between the mounting board and the bump is increased, so the bump can be made stronger than before.
このような効果は、楕円形電極を設けたことに
より容易にかつ同時に得られる。 Such effects can be obtained easily and simultaneously by providing an elliptical electrode.
以上本発明者によつてなされた発明を実施例に
基ずき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しな
い範囲で種々変更可能であることはいうまでもな
い。例えば、バンプの形状及び配置位置等は前記
機能を有するものであればどのようものでもよ
い。 Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and various modifications can be made without departing from the gist thereof. Needless to say. For example, the shape and position of the bump may be any shape as long as it has the above function.
以上の説明では主として本発明者によつてなさ
れた発明をその背景となつた利用分野である大規
模集積回路等の半導体装置の電極形成技術に適用
した場合について説明したが、それに限定される
ものではなく、本発明は、少なくともバンプによ
つて電気的、機械的に接続する場合、熱膨張率の
差による応力が加わることによりバンプの破断不
良防止を必要とする技術分野には適用できる。
The above explanation has mainly been about the case where the invention made by the present inventor is applied to the electrode formation technology of semiconductor devices such as large-scale integrated circuits, which is the background field of application, but the present invention is not limited thereto. Rather, the present invention can be applied at least to technical fields in which it is necessary to prevent failure of bumps from breaking due to stress due to differences in thermal expansion coefficients when electrically and mechanically connected by bumps.
第１図及び第２図は、本発明のフリツプチツプ
型半導体装置の一実施例を説明するための図であ
り、第１図は、そのチツプの平面図、第２図は、
第１図に示すチツプをパツケージに実装した場合
の側面図、第３図及び第４図は、本実施例のバン
プの形成を説明するための図、第５図は、本実施
例のバンプに加わる応力を示す図、第６図は、部
分球状バンプに加わる応力を示す図である。
図中、１…チツプ、２…バンプ、３…実装基
板、４…バンプの配置分布の中心、である。
1 and 2 are diagrams for explaining an embodiment of the flip-chip type semiconductor device of the present invention. FIG. 1 is a plan view of the chip, and FIG.
Figure 1 is a side view of the chip mounted on a package, Figures 3 and 4 are diagrams for explaining the formation of bumps in this example, and Figure 5 is a side view of the chip shown in this example. FIG. 6 is a diagram showing the stress applied to the partially spherical bump. In the figure, 1...chip, 2...bump, 3...mounting board, 4...center of bump arrangement distribution.
Claims (1)
極との間に低融点金属バンプを介在し、前記実装
基板に半導体チツプを実装するフリツプチツプ型
半導体装置において、前記半導体チツプの表面
に、前記低融点金属バンプの配置分布の中心から
の放射線に長軸を一致させた楕円形状の第２電極
を複数形成するとともに、前記実装基板の表面
に、前記半導体チツプの第２電極に対応する楕円
形状の第１電極を複数形成し、前記半導体チツプ
の複数の第２電極の夫々と前記実装基板の複数の
第１電極の夫々との間に、個々に、前記半導体チ
ツプの表面と平行な断面が楕円形状で形成され、
かつこの楕円形状の長軸を前記放射線と一致させ
た低融点金属バンプを形成したことを特徴とする
フリツプチツプ型半導体装置。1. In a flip-chip semiconductor device in which a low melting point metal bump is interposed between a first electrode of a mounting board and a second electrode of a semiconductor chip, and a semiconductor chip is mounted on the mounting board, the low melting point metal bump is provided on the surface of the semiconductor chip. A plurality of elliptical second electrodes whose major axes coincide with the radiation from the center of the distribution of the melting point metal bumps are formed, and an elliptical second electrode corresponding to the second electrode of the semiconductor chip is formed on the surface of the mounting board. A plurality of first electrodes are formed between each of the plurality of second electrodes of the semiconductor chip and each of the plurality of first electrodes of the mounting board, each having an elliptical cross section parallel to the surface of the semiconductor chip. formed in the shape,
A flip-chip type semiconductor device characterized in that a low melting point metal bump is formed in which the long axis of the elliptical shape coincides with the radiation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58146330A JPS6038839A (en) | 1983-08-12 | 1983-08-12 | Flip-chip type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58146330A JPS6038839A (en) | 1983-08-12 | 1983-08-12 | Flip-chip type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6038839A JPS6038839A (en) | 1985-02-28 |
| JPH051616B2 true JPH051616B2 (en) | 1993-01-08 |
Family
ID=15405239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58146330A Granted JPS6038839A (en) | 1983-08-12 | 1983-08-12 | Flip-chip type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6038839A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2563025Y2 (en) * | 1991-09-25 | 1998-02-18 | 小糸工業 株式会社 | Rotational lock mechanism for vehicle turning chair |
| JPH09102517A (en) * | 1995-10-05 | 1997-04-15 | Nec Corp | Semiconductor device |
| US6184581B1 (en) * | 1997-11-24 | 2001-02-06 | Delco Electronics Corporation | Solder bump input/output pad for a surface mount circuit device |
| DE19839760A1 (en) * | 1998-09-01 | 2000-03-02 | Bosch Gmbh Robert | Method for connecting electronic components to a carrier substrate and method for checking such a connection |
| WO2000055652A1 (en) * | 1999-03-17 | 2000-09-21 | Input/Output, Inc. | Calibration of sensors |
| US6518675B2 (en) * | 2000-12-29 | 2003-02-11 | Samsung Electronics Co., Ltd. | Wafer level package and method for manufacturing the same |
| US9093332B2 (en) * | 2011-02-08 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Elongated bump structure for semiconductor devices |
| JP7078821B2 (en) * | 2017-04-28 | 2022-06-01 | 東北マイクロテック株式会社 | Solid-state image sensor |
| WO2022249526A1 (en) * | 2021-05-25 | 2022-12-01 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor package and electronic device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5129867A (en) * | 1974-09-06 | 1976-03-13 | Hitachi Ltd | BONDENGUHOHO |
-
1983
- 1983-08-12 JP JP58146330A patent/JPS6038839A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5129867A (en) * | 1974-09-06 | 1976-03-13 | Hitachi Ltd | BONDENGUHOHO |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6038839A (en) | 1985-02-28 |
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