JPH05160710A - Output circuit - Google Patents

Abstract

PURPOSE:To sufficiently enhance an advantage (high speed property) of a chemical compound semiconductor device by executing level conversion not through a gate so as to decrease a delay time. CONSTITUTION:In the output circuit provided with a logic circuit receiving a logic signal from the inside of an LSI chip and outputting one logic signal, a level setting means setting an L logic level of one logic signal to a prescribed potential larger negatively than the L logic level of the logic signal in the inside of the chip, an open source FET connecting its gate to the output of the level setting means and connecting its source to a load at the outside of the chip, the level setting means is constituted by connecting the FET receiving the logic signal inputted to the logic circuit at its gate and a prescribed resistive element between the output of the logic circuit and a prescribed potential in series.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit interposed between a logic circuit using a compound semiconductor device such as GaAs and an ECL logic circuit. When the logic level of a logic circuit using a compound semiconductor device is lowered by a negative power supply, the L logic level is about -1.5V to -1.2V, and the H logic level is a level determined by the load of the next stage (+0. .6V to 0V), in order to have ECL compatibility, the L logic level is set to the ECL level (-1.6V to-).
Must be set to 1.8V).

[0002]

2. Description of the Related Art FIG. 7A is a block diagram of a conventional output circuit having ECL compatibility. One or a plurality of logic signals (for example, three signals A, B, and C) generated by a gate circuit (not shown) in the chip are, for example, one input having a negative logic, and multiple inputs having a negative sum. It is input to a logic circuit 1 for executing logic, and from this logic circuit 1, a forward voltage (-0.2 V to 0 V) of three diodes is set to an H logic level, V _SS1 (about -1.2 V to -1. A logic signal D whose L level is 5 V) is output. The signal D is input to the level shift circuit 2, and from this level shift circuit 2, the L logic level of the signal D is set to V _SS2 (V _SS2 is a potential larger in the negative direction than V _SS1 and is about −2V). The converted logic signal E is output. The signal E is given to the inverter 3, and the output F of the inverter 3 drives the open source FET (output transistor) 4. _RL represents a termination resistance (usually 50Ω), and V _T represents an ECL termination potential (usually -2V).

Here, the level shift circuit 2 is, for example,
As shown in FIG. 7B, a switching transistor 2a, a diode 2b and a load transistor 2c are connected in series between GND and V _SS2 . Since the switching transistor 2a is turned on when the signal D is H logic, the logic of the signal E is defined by the potential of GND (0 V). On the other hand, when the signal D is L logic, the switching transistor 2a is turned off. Logic is V
It is specified by the potential of _SS2 (about -2V).

[0004]

However, in such a conventional output circuit, since the gates such as the switching transistor 2a and the diode 2c are interposed between the signal D and the signal E, the compound semiconductor is particularly preferable. When applied to a logic circuit composed of devices, there is a problem that the advantage (high speed) of the compound semiconductor device cannot be fully utilized due to the delay of the gate.

Therefore, it is an object of the present invention to perform level conversion without interposing a gate, reduce the delay time, and fully utilize the merit (high speed) of a compound semiconductor device.

[0006]

In order to achieve the above object, the present invention provides a logic circuit for receiving a logic signal from the inside of an LSI chip and outputting one logic signal as shown in FIG. A level setting means for setting the L logic level of the one logic signal to a predetermined potential larger in the negative direction than the L logic level of the logic signal inside the chip; and a gate connected to the output of the level setting means. ,
In an output circuit including an open source FET having a source connected to an external load of the chip, the level setting unit includes an FET that receives at its gate a logic signal input to the logic circuit, and a predetermined resistance element, It is characterized by being connected in series between the output of the logic circuit and a predetermined potential.

[0007]

In the present invention, the output of the logic circuit is directly connected to the gate of the open source FET, and the L logic level of the signal appearing at the connection node is set to a predetermined potential. Therefore, since the gate is not present in the signal path, the delay time due to the gate can be eliminated, and the advantage (high speed) of the compound semiconductor device can be fully utilized.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 6 are diagrams showing an embodiment of the output circuit according to the present invention. First, the configuration will be described. In FIG.
Reference numeral 10 is an LSI chip, 11 is an output circuit, 12 is a gate circuit inside the chip, and the gate circuit 12 is composed of a compound semiconductor device such as GaAs.

Logic signals from the gate circuit 12 (for example, three signals of A, B, C) are GND and V _SS1 (-1.
For example, a negative sum logic (N
It is input to the OR circuit (hereinafter, logic circuit) 13, the output of the logic circuit 13 is connected to the gate of the open source FET (output transistor) 14, and is also connected to the level setting circuit (level setting means) 15. It

The level setting circuit 15 includes FETs 15a to 15c of the same number as the signals A, B and C (here, three) which receive the signals A, B and C at their gates, and these FET1.
5a to 15c sources and V _SS2 (predetermined potential ≈ -2V)
And a resistance element 15d connected between
The drains of the ETs 15a to 15c are connected to the output of the logic circuit 13. _RL is a terminating resistance (usually 50Ω),
V _T represents the termination voltage of ECL (typically -2 V).

From the logic circuit 13, three input signals A,
One signal D corresponding to the logics of B and C is output. The H logic level of this signal D corresponds to the forward voltage of three diodes (-0.2 V to 0 V), and the L logic level corresponds to the potential of V _SS1 (-1.5 V to -1.2 V). To do.
Next, the operation will be described.

In FIG. 3, the logic circuit 13 is a negative logic (inverter) circuit for simplification, and the logic circuit 13 has an L-level circuit.
It is explanatory drawing at the time of inputting the logic signal (for example, signal A of FIG. 2). In this case, FET that receives signal A at its gate
15a is off and its drain-source has a high impedance. Therefore, the H logic level of the signal D appearing at the output of the logic circuit 13 becomes a high potential level corresponding to the GND potential, the output transistor 14 turns on, and the G
As a result of the load current I _L flowing from the ND potential to V _T , a potential corresponding to the H logic level of ECL is generated across the load resistance R _L.

On the other hand, FIG. 4 is an explanatory diagram when the signal A is H logic. In this case, the FET 15a is turned on, and its drain and source are connected with low impedance (corresponding to the channel on resistance R _ON ). Therefore, the output of the logic circuit 13 is connected to V _SS2 via the FET 15a and the resistance element 15d, so that the L logic level of the signal D appearing at the output of the logic circuit 13 is pulled toward V _SS2 .

Here, the FET 15d and the resistance element 15
The current ia flowing through d is obtained by the following equation (1). ia = ΔV _SS / ΣR (1) where ΔV _SS is the potential difference between the original L logic level potential of the signal D (corresponding to V _SS1 ) and the potential of V _SS2 (≈V _SS1 −
V _SS2 ), and ΣR is a combined resistance value (R _ON + R _15d ) of the channel ON resistance R _ON of the FET 15a and the resistance value R _15d of the resistance element 15d. In general, the FET channel on resistance has an extremely small value. The resistance element 15d used in the present embodiment is for ensuring the on / off operation of the FET 15a, and its value (resistance value R _15d )
Can be a very small value. Therefore, R _ON and R _15d
Is a minute value, and the L logic level of the signal D is set by the potential of V _{S S2} .

As described above, in this embodiment, the signal A
When (or B, C ...) Inputs H logic, FET1
5a is turned on and L of the signal D appearing at the output of the logic circuit 13
The logic level changes from V _SS1 equivalent to V _SS2 equivalent. That is, the level conversion is executed without any trouble. Further, in this embodiment, the output of the logic circuit 13 and the output transistor 14 are
And are directly connected to each other with no gate interposed therebetween. Therefore, the delay time of the signal D can be made almost zero, and the advantage (high speed) of the compound semiconductor device used for the internal gate circuit can be fully utilized.

The embodiment of the present invention is not limited to the above embodiment, and various modifications can be considered within the scope of the present invention. For example, as shown in FIG.
15e is used as a resistance element, a fixed resistor 15f is used as shown in FIG. 6 (a), or
As shown in (b), a diode 15g may be used. Incidentally, the logic circuit shown in FIG. 5 is a negative sum logic (NOR) circuit 2 inputs, two enhancement connected in parallel (E) type FET 16a, and 16b and depletion (D) type FET16c, GND and V _SS1 E / D type DCFL (Direct Coupled)
Logic) circuit.

[0017]

According to the present invention, level conversion can be performed without interposing a gate. Therefore, the delay time due to the gate can be eliminated, and the advantage (high speed) of the compound semiconductor device can be fully utilized.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is an explanatory diagram of an operation when a signal A has an L logic level.

FIG. 4 is an operation explanatory diagram when a signal A has an H logic level.

FIG. 5 is another configuration diagram of the embodiment.

FIG. 6 is still another configuration diagram of the level conversion circuit.

FIG. 7 is a configuration diagram of a conventional output circuit and a circuit diagram of a level shift circuit.

[Explanation of symbols]

13: logic circuit 14: output transistor (open source FET) 15: level conversion circuit (level setting means) 15a, 15b, 15c: FET 15d: resistance element 15e: FET (resistance element) 15f: fixed resistance (resistance element) 15 g: diode (resistive element) A, B, C: logic signal D: one logic signal V _SS2 : predetermined potential

Claims (1)

[Claims] 1. A logic circuit which receives a logic signal from the inside of an LSI chip and outputs one logic signal, and an L logic level of the one logic signal is more negative than the L logic level of the logic signal inside the chip. A level setting means for setting a predetermined potential larger in a direction, and an open source FET having a gate connected to an output of the level setting means and a source connected to an external load of the chip, The means includes an FET that receives at its gate a logic signal input to the logic circuit, and a predetermined resistance element,
An output circuit characterized by being connected in series between the output of the logic circuit and a predetermined potential.