JPH05160358A - Latchup-proof semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate effects of a latchup phenomenon on a CMOS semiconductor device under a radiation environment or a high electromagnetic field environment. CONSTITUTION:Optical waveguides 1, 2 and 4 which are composed of oxide films are formed in a CMOS IC. The direction of a light emitted by a latchup phenomenon is turned 90 degrees at the end part of the optical waveguide 4 and inputted to a photoelectric transducer 3. Transistors 5 and 22 are provided on the output side of the photoelectric transducer 3. The electromotive force of the photoelectric transducer 3 is applied to the depletion-type MOS transistor 5 to cut off a power supply current to dissolve the latchup phenomenon. Further, the non-volatile depletion-type MOS transistor 22 is provided in parallel with the depletion-type MOS transistor 5 and stors charge in its floating gate and isolates a semiconductor device from the power supply permanently. A latchup generation signal terminal 27 informs other devices of the generation of the latchup phenomenon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an anti-latch-up semiconductor device, and more particularly, it is used for an electronic device operated under a radiation environment or a high electromagnetic field environment, and particularly, a latch-up resistance of a CMOS structure imparting an anti-latch up property. Regarding semiconductor devices.

[0002]

2. Description of the Related Art As a semiconductor device having a CMOS structure is miniaturized, an excessive current flows between power supply terminals due to an ON state of a parasitic thyristor formed by a combination of a parasitic PNP transistor and an NPN transistor, and the semiconductor device is destroyed. Latch-up that invites
p) Phenomenon occurs.

A conventional non-latch-up semiconductor device that does not take measures against this latch-up phenomenon is
Taking an inverter circuit having an OS structure as an example, its basic structure is as shown in FIGS. 8 and 9.

FIG. 8 is a vertical cross section of an inverter circuit formed by a conventional semiconductor device having a CMOS structure, and FIG.
2 is an equivalent circuit diagram of the semiconductor device having the CMOS structure of FIG.

As shown in FIG. 8, an N-channel MOS transistor 10 and a P-channel MOS transistor 6 are formed on the surface of an N-type bulk material 16, and they are electrically connected as shown in the equivalent circuit of FIG. There is.

In this CMOS structure semiconductor device,
A parasitic PNP transistor 18 formed by the drain side P + region of the P channel MOS transistor 6, the bulk material 16 and the P well 17 of the N channel MOS transistor 10, and the bulk material 19, the P well 17 and the N channel of the N channel MOS transistor 10. A parasitic N formed in the source side N + region of the MOS transistor 10.
The PN transistor 19 is connected as shown in the equivalent circuit of FIG. 10 to form a PNPN structure, and finally forms a parasitic thyristor structure.

When a voltage is applied to this circuit, excessive electron-hole pairs are injected into the depletion layer at the PN junction portion in the semiconductor device due to the effects of radiation exposure and high electromagnetic fields, and positive electrons and holes are injected. FIG. 10 with the light emission phenomenon due to the recombination of holes.
The parasitic thyristor shown in (1) turns on and a latch-up phenomenon occurs.

Further, in the large-scale integrated circuit having the CMOS structure, the distance A20 between the N-channel MOS transistor 10 and the P-channel MOS transistor 6 is set.
Alternatively, the distance B21 between the source side N + region of the N-channel MOS transistor and the P well 17 is reduced due to miniaturization, and the parasitic PNP transistor 1 equivalently shown in FIG.
8 and the space between the base regions of the parasitic NPN transistor 19 are narrowed, and the current amplification factors of the parasitic PNP transistor 18 and the parasitic NPN transistor 19 exceed 1, so that the resistance to the latch-up phenomenon is similarly reduced.

In order to increase such withstand capability, P +, N +
CM using guard band structure and epitaxial substrate
Even when the OS structure is formed, it is impossible to completely remove the parasitic thyristor structure, and the possibility of receiving a disturbance exceeding the latch-up withstand level assumed in the design stage cannot be stochastically avoided. Cannot be completely eliminated.

[0010]

As shown in FIG. 8 described above,
As an example of an inverter circuit having a CMOS structure of a conventional non-latch-up semiconductor device,
In the structure, the drain side P + region of the P channel MOS transistor 6, the N type bulk material 16, and the N channel M
A parasitic PNP transistor 18 formed by the P well 17 of the OS transistor 10, an N-type bulk material 16, N
P well 17 of the channel MOS transistor 10,
The parasitic NPN transistor 19 formed in the source side N + region of the N-channel transistor 10 forms an equivalent circuit shown in FIG. 10 to have a PNPN structure, and finally forms a parasitic thyristor structure, and a voltage is applied to this circuit. In the applied state, due to radiation exposure and high electromagnetic fields, excess electrons and electrons are generated in the depletion layer at the PN junction in the semiconductor device.
By injecting a pair of holes, the parasitic thyristor structure is turned on with a light emission phenomenon caused by the recombination of electrons and holes, and the voltage applied to the circuit causes current to continue to be supplied, resulting in a short circuit state. There is a drawback in that the wiring inside the circuit is melted by the overcurrent, the irrecoverable damage is permanently caused by the generated Joule heat, and the latch-up phenomenon that leads to the destruction cannot be avoided.

Further, due to the latch-up phenomenon, even if the current value does not rise to such an extent that the wiring is blown, the current is always kept flowing, and the function of the circuit constituted by the potential fluctuation in the substrate is caused. It is completely lost and fixed in a permanent malfunction state, and the disadvantage of increased power consumption occurs.

Further, in a large-scale integrated circuit having a CMOS structure, the installation distance between the N-channel MOS transistor 10 and the P-channel MOS transistor 6 becomes closer to each other due to miniaturization, and the parasitic PNP transistor 1 is equivalently equivalent.
8. Since the base region interval of the parasitic NPN transistor 19 decreases and the current amplification factor of the parasitic transistors 18 and 19 exceeds 1, the resistance to radiation exposure or the resistance to electromagnetic field entering the signal input terminal from the outside decreases. However, there is a drawback that the latch-up phenomenon easily occurs.

An object of the present invention is to solve the above-mentioned drawbacks, and to prevent a decrease in withstand capability against a latch-up phenomenon caused by an exposure radiation or an electromagnetic field intruding into a signal input terminal from the outside, a latch-up resistant semiconductor device having a CMOS structure. To provide.

[0014]

A latch-up resistant semiconductor device of the present invention is a latch-up resistant semiconductor device having a CMOS structure provided with a function of eliminating an influence of a latch-up phenomenon caused in a radiation environment or a high electromagnetic field environment. A semiconductor device having an optical waveguide made of an oxide film formed on a surface of a semiconductor device having a CMOS structure for optically detecting the latch-up phenomenon, The light emission is converted into an electric signal, and the overcurrent of circuit conduction caused by the latch-up phenomenon is cut off, so that permanent destruction and loss of function are repeatedly restored.

Further, the anti-latch-up semiconductor device of the present invention has a function of detecting a functional loss of normal operation due to the latch-up phenomenon by a hardware configuration and notifying other electronic circuits connected thereto.

Further, in the latch-up resistant semiconductor device of the present invention, when a permanent structural abnormality occurs due to the latch-up phenomenon and the overcurrent flowing in the circuit cannot be eliminated,
The power supply to the semiconductor device is permanently cut off to suppress the occurrence of the overcurrent.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a CMOS according to the first embodiment of the present invention.
2 is a plan view of a latch-up resistant semiconductor device having a structure, FIG. 2 is a longitudinal sectional view of the embodiment of FIG. 1, FIG. 3 is a side view of the embodiment of FIG. 1, and FIG. 4 is an equivalent circuit diagram of the embodiment of FIG. ..

This embodiment shows an example of application to an inverter circuit. As shown in FIGS. 1 and 2, at the position sandwiched by the drain electrode 7, the gate electrode 8 and the source electrode 9 of the P-channel MOS transistor 6, the gate electrode is formed. The oxide film forms the optical waveguide 2 in the shape of enclosing 8, and in the N-channel MOS transistor 10, the oxide film forms the optical waveguide 1 as in the P-channel MOS transistor 6 described above, and the positional relationship is the drain electrode. And the source electrode, and surrounds the gate electrode 13.

The optical waveguides 1 and 2 and the optical waveguide 4 are coupled to each other in a gentle curve, and the optical waveguides 1 and
The structure is such that the light guided to 2 is propagated to the optical waveguide 4.

The end face of the optical waveguide 4 is processed at an angle of 45 degrees as shown in FIG. 3, and the processed surface is provided with a coating for totally reflecting light in the visible to infrared region.

Therefore, the light emitted by the latch-up phenomenon is totally reflected and the propagation direction is changed by 90 degrees, and the photoelectric conversion element 3
Is incident on and converts the propagating light into electromotive force.

This electromotive force is applied to the gate electrode of the depletion type MOS transistor 5 shown in the equivalent circuit of FIG. 4, thereby operating the depletion type MOS transistor 5. As a result, the current supplied from the power supply terminal 31 is cut off, the current flowing in the portion where the latch-up phenomenon occurs is interrupted, and the latch-up phenomenon can be eliminated.

Further, when the latch-up phenomenon stops, the light emission at the latch-up phenomenon generating portion disappears, the light propagating through the optical waveguides 1, 2 and 4 disappears, and the electromotive force generated by the photoelectric conversion element 3 is reduced. When the depletion-type MOS transistor 5 disappears, the depletion-type MOS transistor 5 is deactivated, and the circuit can be supplied with current again to restore the normal functioning state.

Further, as shown in the operational connection example of FIG. 5, the latch-up occurrence signal terminal 27 shown in FIG. , It is used to send out a latch-up generation signal that warns that an erroneous electrical signal that is under the latch-up phenomenon and is invalid should be output.

FIG. 6 shows a CMOS according to the second embodiment of the present invention.
FIG. 7 is a plan view of a latch-up resistant semiconductor device having a structure, and FIG. 7 is an equivalent circuit diagram thereof.

In the second embodiment, as shown in the equivalent circuit of FIG. 7, a nonvolatile depletion type MOS transistor 22 having a floating gate structure is arranged between the power supply terminal 31 and the depletion type MOS transistor 5. However, even if the power is cut off for the generated latchup,
In the state where the structure is destroyed in which an overcurrent flows again when the power source is connected again, the light is guided to the photoelectric conversion element 3 through the optical waveguides 1, 2 and 4, and the electromotive force generated by the photoelectric conversion element 3 is A non-volatile depletion type MOS transistor 22 having a floating gate structure having a memory function is applied in parallel to the gate of a normal depletion type MOS transistor 5 and a latch-up phenomenon holding time of a finite time is reached.
Electric charges are accumulated in the floating gate of the transistor 22, whereby the non-volatile depletion type MOS transistor 22 is completely turned off, and the semiconductor device circuit having the structural breakdown is permanently cut off from the power supply.

The time until the non-volatile depletion type MOS transistor 22 is completely turned on is adjusted as follows.
This is possible by changing the thickness of the insulating oxide film which causes the FN tunnel effect in advance.

In the above-described first and second embodiments, the optical waveguide can be made of silicon dioxide of the same quality as the insulating film of the semiconductor device, which can be dealt with in the present process steps, and the optical waveguide is provided. This allows the semiconductor device to function even if the entire semiconductor device is covered with the metal electrode.

Also, a method of providing a photoelectric conversion device on the entire surface of the semiconductor device may be considered, or the case where the optical waveguide is configured as in the present invention is more effective for the light generated by the latch-up phenomenon. It is possible to use strength.

In this way, when used in a radiation environment or a high electromagnetic field environment, it is possible to prevent the permanent destruction of the semiconductor device caused by the latch-up phenomenon and the recovery from the abnormal operation repeatedly, and the operating life. The period can be greatly extended, and the hardware costs such as simplification of the redundant system and radiation resistant shield and electromagnetic field resistant shield can be significantly reduced.

Although the silicon composition semiconductor device and the small-scale integrated circuit have been described in the above-mentioned embodiments, an optical waveguide is formed in the oxide film to prevent exposure to radiation or high electromagnetic fields regardless of the degree of integration. Since the latch-up phenomenon due to exposure is accompanied by a light emission phenomenon, light is guided and propagated in an optical waveguide, converted into an electric signal by a photoelectric conversion device, input to a switching device, and the current supplied to a semiconductor device is changed. It is clear that it is possible to cut off and recover the latch-up phenomenon, and that the cross-sectional area, shape and size of the optical waveguide can be set arbitrarily.

[0033]

As described above, according to the present invention, the CMOS
In a semiconductor device having a structure, an optical waveguide structure is formed on an oxide film between a drain electrode and a source electrode of a P-channel MOS transistor and an oxide film between a drain electrode and a source electrode of an N-channel MOS transistor. Then, the light generated by the latch-up phenomenon is guided to the optical waveguide, propagated and applied to the photoelectric conversion device, and the depletion type M is generated by the electromotive force generated thereby.
It is possible to suppress the latch-up phenomenon by operating the OS transistor and cut off the current supplied from the power supply to the semiconductor device, and prevent the permanent damage or abnormal electrical operation of the semiconductor device caused by the latch-up phenomenon. There is an effect that can be done.

Further, after the latch-up phenomenon is stopped, a current can be supplied to the semiconductor device again, and the circuit operation can be repeatedly restarted.

Further, during the period in which the latch-up phenomenon is occurring, the state in which normal operation is lost is detected by hardware by itself, and it is notified to other connected electronic circuits,
This has the effect of preventing erroneous signals from being continuously processed.

Further, in the case where a permanent structural abnormality occurs in the semiconductor device having the CMOS structure, and the overcurrent flows when the power is reconnected after the power is shut off due to the overcurrent flowing in the semiconductor device, By turning off the non-volatile depletion type MOS transistor after the latch-up phenomenon lasts for a finite time, the semiconductor device circuit in which the structural abnormality has occurred is permanently cut off from the power supply and the overcurrent is prevented from continuing to flow. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a plan view of a latch-up resistant semiconductor device having a CMOS structure according to a first embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view of the anti-latch-up semiconductor device of FIG.

3 is a side view of the latch-up resistant semiconductor device of FIG.

4 is an equivalent circuit diagram of the latch-up resistant semiconductor device of FIG.

5 is a diagram showing an example of an operational connection of the latch-up resistant semiconductor device of FIG.

FIG. 6 is a plan view of a latch-up resistant semiconductor device having a CMOS structure according to a second embodiment of the present invention.

7 is an equivalent circuit diagram of the latch-up resistant semiconductor device of FIG.

FIG. 8 is a vertical sectional view showing an example of a conventional semiconductor device having a CMOS structure.

9 is an equivalent circuit diagram of the semiconductor device of FIG.

10 is an equivalent circuit diagram of a parasitic thyristor existing in the semiconductor device of FIG.

[Explanation of symbols]

 1, 2 Optical Waveguide 3 Photoelectric Conversion Element 4 Optical Waveguide 5 Depletion Type MOS Transistor 6 P Channel MOS Transistor 7 Drain Electrode 8 Gate Electrode 9 Source Electrode 10 N Channel MOS Transistor 11 Drain Electrode 12 Source Electrode 13 Gate Electrode 14 Drain Side PN Junction Part 15 Source-side PN junction part 16 N-type bulk material 17 P-well 18 Parasitic PNP transistor 19 Parasitic NPN transistor 20 Distance A 21 Distance B 22 Non-volatile depletion type MOS transistor 23 Integrated circuit (1) 24 Integrated circuit (2) 25 Integrated Circuit (3) 26 Logical data bus 27 Latch-up occurrence signal terminal 28 Latch-up occurrence communication bus 29 Input terminal 30 Output terminal 31 Power supply terminal

Claims (3)

[Claims] 1. A latch-up resistant semiconductor device having a CMOS structure provided with a function of eliminating an influence of a latch-up phenomenon caused in a radiation environment or a high electromagnetic field environment. An optical waveguide formed of an oxide film is formed on the surface of a semiconductor device having a CMOS structure for detection, and light emitted by the latch-up phenomenon guided by the optical waveguide is converted into an electric signal.
A latch-up resistant semiconductor device having a function and structure for repeatedly recovering permanent damage and loss of function by cutting off an overcurrent of circuit conduction caused by the latch-up phenomenon. 2. The resistance according to claim 1, which has a function and a structure for detecting a functional loss of a normal operation due to the latch-up phenomenon by a hardware configuration and notifying other electronic circuits connected thereto. Latch-up semiconductor device. 3. When a permanent structural abnormality occurs due to the latch-up phenomenon and the overcurrent flowing through the circuit cannot be eliminated, the power supply to the semiconductor device is permanently cut off to prevent the overcurrent from occurring. The anti-latch-up semiconductor device according to claim 1, which has the function and structure of: