JPH05159599A - Flash memory - Google Patents

Abstract

PURPOSE:To make it possible to conduct a reliable test of the number of rewritable times and to guarantee the number of rewritable times with high precision, without affecting a memory cell transistor for which the number of rewritable times is to be guaranteed, in regard to EEPROM, a so-called flash memory, which executes erasure of data written in the memory cell transistor with respect to each chip or a block as a unit. CONSTITUTION:In the case when data written in memory cell transistors 130 and 131 for a test are erased when the number of rewritable times is tested, a voltage required for erasure is supplied only to the sources of the memory cell transistors 130 and 131 for the test from a source power circuit 17 through a source line 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is an electrically erasable and writable nonvolatile semiconductor memory device EEPRO.
M (Electrically Erasable and Programmable Read On
memory), an EEPROM that erases data written in memory cell transistors in units of chips or blocks, so-called flash memory.
Regarding memory.

[0002]

2. Description of the Related Art Conventionally, a flash memory shown in FIG.
It is known that the main part is shown in. 1 in the figure
₀₀ , 1 ₁₀ , 1 _0n , 1 _1n are memory cell transistors composed of EEPROM cell transistors, 2 ₀ , 2 ₁ are word lines, and X ₀ , X ₁ are word line selection signals.

Further, 3 ₀ , 3 _n are bit lines, 4 ₀ , 4 _n are nMOS transistors forming column gates, Y ₀ , Y _n are column selection signals for selecting columns, and 5 are memory cells.
It is a sense amplifier that amplifies the data read from the transistor.

Further, 6 is a memory cell transistor 1
_{00, 1 10, 1 0n,} 1 1n source connected to source line of,
7 is a memory cell transistor 1 via a source line 6
_{00, 1 10, 1 0n,} 1 is a source power supply circuit for supplying a source voltage to the source of _1n.

[0005] In addition, the memory cell transistor 1 _00,
1 ₁₀ , 1 _0n and 1 _1n are configured, for example, as shown in the schematic sectional view of FIG. In the figure, the P 8 ^- -type silicon substrate, a drain made of N ⁺ diffusion layer 9, the source consisting of N ⁺ diffusion layers 10, 11 are floating gates, 1
2 is a control gate, V _G is a control gate voltage, V _D is a drain voltage, and V _S is a source voltage.

[0006] Such a memory cell transistor 1 _00,
At the time of writing, 1 ₁₀ , _10n and _1n are, for example, control gate voltage V _G = 12 [V] and drain voltage V _D = 6.
[V], source voltage V _S = 0 [V], drain 9
Electrons are injected into the floating gate 11 from.

On the other hand, at the time of erasing, for example, the control gate voltage V _G = 0 [V] and the drain voltage V _D =
Open, the source voltage V _{S is set to} 12 [V], and electrons are extracted from the floating gate 11 to the source 10.

At the time of reading, for example, the control gate voltage V _G = 5 [V] and the drain voltage V _D = 1.
[V] and source voltage V _S = 0 [V].

[0009]

[Problems to be Solved by the Invention]
Since the memory is a rewritable memory, it is necessary to guarantee the number of rewritable times, and for this purpose, it is necessary to mount a test memory cell transistor for testing the number of rewritable times. However, the conventional flash memory does not have a memory cell transistor for testing.

In a flash memory, data is erased in units of chips or blocks. Therefore, for example, in a conventional flash memory whose essential portion is shown in FIG. 2, the memory cell transistor 1 is used.
_00, 1 _10, provided with a source line 6 in common for 1 _0n, 1 _1n, erasing of data, the memory cell transistors 1 _00, 1 _10, 1 _0n, 1 _1n source to, at the same time, erases voltage required for, for example, 12 [V] to supply, and these memory cell transistors 1 _00, 1 _10, the 1 _0n, 1 erasure of being written data to _1n in performed in batch.

Therefore, according to this method, when a memory cell transistor for testing is mounted, for example, as shown in FIG.
As shown the main part, the memory cell transistors _{1 00, 1 10, 1 0n} , 1 1n the memory cell transistors 13 ₀ for testing consisting of EEPROM cell transistor the source line 6 formed by a common , 13 ₁ may be provided.

Reference numeral 14 is a test bit line, 15 is an nMOS transistor for selecting the test bit line 14, and TEST is a test signal for controlling ON / OFF of the nMOS transistor 15.

However, with such a configuration, when the rewritable count test is performed, that is, when the writing and erasing are repeatedly performed on the test memory cell transistors 13 ₀ and 13 ₁ , the rewriting is originally performed. possible number of times the memory cell transistor should ensure _{1 00, 1 10, 1 0n} , 1
Because becomes possible to perform the erase operation repeatedly against _1n, these memory cell transistors 1 _00, 1
_10, 1 _0n, 1 _1n become over-erased state, there is a disadvantage that a always on during normal use as a memory.

[0014] That is, as shown in a main portion thereof in FIG. 4, the number of rewritable times the memory cell transistor 1 should ensure _00, 1 _10, 1 _0n, 1 _1n and for then formed by testing a source line 6 into the common When the memory cell transistors 13 ₀ and 13 ₁ are provided, the memory
Cell transistors _{1 00, 1 10, 1 0n} , will affect the 1 _1n, there is a problem that it is not possible to perform reliable rewritable count test.

In view of such a point, the present invention performs a reliable rewritable count test without affecting the memory cell transistor for which the rewritable count should be guaranteed.
An object of the present invention is to provide a flash memory capable of guaranteeing the number of rewritable times with high accuracy.

[0016]

A flash memory according to the present invention tests a memory cell transistor for which the rewritable count is to be guaranteed and the rewritable count for the memory cell transistor for which the rewritable count is to be guaranteed. In a flash memory configured with a test memory cell transistor for testing, the source of the memory cell transistor for which the rewritable count should be guaranteed and the source of the test memory cell transistor Are connected to separate and independent source lines, and when erasing the data written in the memory cell transistor for testing during the rewritable count test,
The cell transistor is configured so that the voltage required for erasing is applied only to the source of the cell transistor.

[0017]

According to the present invention, the source of the memory cell transistor for which the number of rewritable times should be guaranteed and the source of the memory cell transistor for testing are connected to separate and independent source lines to test the number of rewritable times. At this time, when erasing the data written in the test memory cell transistor, the voltage required for erasing can be applied only to the source of this test memory cell transistor. Therefore, it is not necessary to apply a voltage required for erasing to the source of the memory cell transistor, which must guarantee the number of rewritable times.

Therefore, the rewritable number can be tested with certainty and the rewritable number can be guaranteed with high accuracy without affecting the memory cell transistor for which the rewritable number should be guaranteed.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. Note that, in FIG. 1, portions corresponding to those in FIGS. 2 and 4 are denoted by the same reference numerals, and duplicate description thereof will be omitted.

FIG. 1 is a circuit diagram showing an essential part of one embodiment of the present invention. In the flash memory of this embodiment,
In addition to the source line 6, a source line 16 independent of the source line 6 is provided.

[0021] Therefore, in this embodiment, the memory cell transistors 1 ₀₀ should guarantee the number of rewritable times,
The sources of 1 ₁₀ , 1 _0n , 1 _1n are commonly connected to the source line 6, and the memory cell transistors 13 ₀ for testing,
13 ₁ are commonly connected to the source in the source line 16.

Further, in this embodiment, in addition to the source power supply circuit 7, the source power supply circuit 17 independently of the source power supply circuit 7 is provided, the memory cell transistors 1 _00, 1 _10, 1 _0n A source voltage is supplied from the source power supply circuit 7 to the source of 1 _1n via the source line 6, and the memory cell transistors 13 ₀ and 13 ₁ for testing are supplied.
The source of the power is from the source power supply circuit 17 to the source line 16
Is configured to supply a source voltage via the.

In the present embodiment having the above-described structure, the memory cell
When erasing the data written in the transistors 13 ₀ and 13 ₁ , the memory cell transistor 13 ₀ for testing is connected from the source power supply circuit 17 through the source line 16.
Only the source of 13 _{1 has} the voltage required for erasing, for example, 1
2 can be applied to [V], the memory cell transistors 1 _00, 1 _10, the 1 _0n, 1 _1n source need not apply a voltage necessary for erasure.

[0024] Thus, according to this embodiment, the memory cell transistors 1 ₀₀ should ensure the number of rewritable times, 1 _10, 1 _0n, 1 without affecting the _1n, perform a reliable number of rewritable times test The rewritable count can be guaranteed with high accuracy.

[0025]

As described above, according to the present invention, the source of the memory cell transistor for which the rewritable count is to be guaranteed and the memory cell transistor for which the rewritable count is to be guaranteed.
The source of the memory cell transistor for testing to test the rewritable count of the cell transistor is connected to a separate and independent source line, and the rewritable count test is performed.
When erasing the data written in the test memory cell transistor, the test memory cell
Since the voltage required for erasing can be applied only to the source of the transistor, rewriting is possible when erasing the data written in the memory cell transistor for testing during the rewritable count test. Since it is not necessary to apply the voltage necessary for erasing to the source of the memory cell transistor that should guarantee the number of possible times,
It is possible to perform a reliable rewritable count test and guarantee the rewritable count with high accuracy without affecting the memory cell transistor for which the rewritable count should be guaranteed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main part of a conventional flash memory.

FIG. 3 is a schematic cross-sectional view showing a memory cell transistor.

FIG. 4 is a circuit diagram showing an example of a flash memory provided with a memory cell transistor for testing.

[EXPLANATION OF SYMBOLS] 1 _00, 1 _10, 1 _0n, 1 _1n memory cell transistors 2 _0, 2 ₁ word line 3 _0, 3 _n bit lines 6 the source lines 13 _0, 13 memory cells for ₁ test, Transistor 14 Bit line for testing 16 Source line for testing

Claims (1)

[Claims] 1. A memory cell transistor for which the rewritable count is to be guaranteed, and a test memory cell transistor for testing the rewritable count of the memory cell transistor for which the rewritable count is to be guaranteed. In a flash memory configured by providing a source of the memory cell transistor for which the number of rewritable times should be guaranteed and a source of the memory cell transistor for testing are connected to separate and independent source lines. ,
During the rewritable count test, the memory cell
A flash memory, characterized in that when erasing data written in a transistor, a voltage required for erasing is applied only to the source of the memory cell transistor for testing.