JP3106624B2 - Flash memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable and writable nonvolatile semiconductor memory device EEPRO.
M (Electrically Erasable and Programmable Read On
ly memory), an EEPROM that erases data written in a memory cell transistor in units of chips or blocks, a so-called flash memory.
Regarding memory.

[0002]

2. Description of the Related Art Conventionally, as a flash memory, FIG.
There are known those which show the main part. In the figure, 1
_00, 1 _10, 1 _0n, 1 _1n the memory cell transistors composed of EEPROM cell transistor, 2 _0, 2 ₁ word line, X _0, X ₁ is a word line selection signal.

[0003], 3 _0, 3 _n bit lines, 4 _0, 4 _n is an nMOS transistor constituting the column gate, Y _0, Y _n is the column select signal for selecting a column, 5 memory cell
This is a sense amplifier that amplifies data read from the transistor.

Further, reference numeral 6 denotes a memory cell transistor 1
_{00, 1 10, 1 0n,} 1 1n source connected to source line of,
7 is a memory cell transistor 1 via a source line 6
_{00, 1 10, 1 0n,} 1 is a source power supply circuit for supplying a source voltage to the source of _1n.

[0005] In addition, the memory cell transistor 1 _00,
1 _10, 1 _0n, 1 _1n, for example, is configured to show the schematic sectional view in FIG. In the figure, the P 8 ^- -type silicon substrate, a drain made of N ⁺ diffusion layer 9, the source consisting of N ⁺ diffusion layers 10, 11 are floating gates, 1
2 control gate, V _G is the control gate voltage, V _D is the drain voltage, the V _S is the source voltage.

[0006] Such a memory cell transistor 1 _00,
1 _10, 1 _0n, 1 _1n are the time of writing, for example, the control gate voltage V _G = 12 [V], the drain voltage V _D = 6
[V], the source voltage V _S = 0 [V], and the drain 9
, Electrons are injected into the floating gate 11.

On the other hand, at the time of erasing, for example, the control gate voltage V _G = 0 [V] and the drain voltage V _D =
Open, the source voltage V _{S is set to} 12 [V], and electrons are extracted from the floating gate 11 to the source 10.

At the time of reading, for example, control gate voltage V _G = 5 [V] and drain voltage V _D = 1
[V], and the source voltage V _S = 0 [V].

[0009]

SUMMARY OF THE INVENTION Here, flash
Since the memory is a rewritable memory, it is necessary to guarantee the number of rewritable times. To this end, it is necessary to mount a test memory cell transistor for testing the number of rewritable times. However, the conventional flash memory does not include a memory cell transistor for testing.

Since a flash memory erases data in units of chips or blocks, for example, in a conventional flash memory whose main part is shown in FIG.
_00, 1 _10, provided with a source line 6 in common for 1 _0n, 1 _1n, erasing of data, the memory cell transistors 1 _00, 1 _10, 1 _0n, 1 _1n source to, at the same time, erases voltage required for, for example, 12 [V] to supply, and these memory cell transistors 1 _00, 1 _10, the 1 _0n, 1 erasure of being written data to _1n in performed in batch.

Therefore, according to this method, when a memory cell transistor for testing is mounted, for example, as shown in FIG.
As shown the main part, the memory cell transistors _{1 00, 1 10, 1 0n} , 1 1n the memory cell transistors 13 ₀ for testing consisting of EEPROM cell transistor the source line 6 formed by a common , it is conceivable to provide a 13 _1.

Reference numeral 14 denotes a test bit line, 15 denotes an nMOS transistor for selecting the test bit line 14, and TEST denotes a test signal for controlling on / off of the nMOS transistor 15.

However, with such a configuration, when a rewritable number test is performed, that is, when writing and erasing are repeatedly performed on the test memory cell transistors 13 ₀ and 13 ₁ , the rewriting is originally required. possible number of times the memory cell transistor should ensure _{1 00, 1 10, 1 0n} , 1
Because becomes possible to perform the erase operation repeatedly against _1n, these memory cell transistors 1 _00, 1
₁₀ , _10n , and _11n are in an excessively erased state, and are always in an on state during normal use as a memory.

[0014] That is, as shown in a main portion thereof in FIG. 4, the number of rewritable times the memory cell transistor 1 should ensure _00, 1 _10, 1 _0n, 1 _1n and for then formed by testing a source line 6 into the common When the memory cell transistors 13 ₀ and 13 ₁ are provided, the memory cells for which the number of rewritable times must be guaranteed
Cell transistors _{1 00, 1 10, 1 0n} , will affect the 1 _1n, there is a problem that it is not possible to perform reliable rewritable count test.

In view of the foregoing, the present invention performs a reliable rewritable number test without affecting a memory cell transistor for which the rewritable number is to be guaranteed.
It is an object of the present invention to provide a flash memory capable of guaranteeing the number of rewritable times with high accuracy.

[0016]

A flash memory according to the present invention tests a memory cell transistor for which the number of rewritable times is to be guaranteed and a number of rewritable times of the memory cell transistor for which the number of rewritable times is to be guaranteed. In a flash memory provided with a memory cell transistor for testing, a source of the memory cell transistor for which the number of rewritable times is to be guaranteed, a source of the memory cell transistor for testing, Is connected to a separate source line, and when erasing the data written in the test memory cell transistor during the rewritable number test, the test memory
The configuration is such that a voltage required for erasing is applied only to the source of the cell transistor.

[0017]

According to the present invention, the source of a memory cell transistor whose number of rewritable times is to be guaranteed and the source of a memory cell transistor for testing are connected to independent source lines to perform a rewritable number of times test. When erasing data written in a memory cell transistor for testing, the voltage required for erasing can be applied only to the source of the memory cell transistor for testing. Therefore, it is not necessary to apply a voltage necessary for erasing to the source of the memory cell transistor for which the rewritable number is to be guaranteed.

Therefore, a reliable test can be performed on the number of rewritable times without affecting the memory cell transistor that should guarantee the number of rewritable times, and the number of rewritable times can be guaranteed with high accuracy.

[0019]

An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIGS. 2 and 4 are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention. In the flash memory of this embodiment,
In addition to the source line 6, a source line 16 independent of the source line 6 is provided.

[0021] Therefore, in this embodiment, the memory cell transistors 1 ₀₀ should guarantee the number of rewritable times,
1 _10, 1 _0n, 1 _1n are connected in common to the source in the source line 6, the memory cell transistors 13 ₀ for the test,
13 ₁ has its source commonly connected to the source line 16.

Further, in this embodiment, in addition to the source power supply circuit 7, the source power supply circuit 17 independently of the source power supply circuit 7 is provided, the memory cell transistors 1 _00, 1 _10, 1 _0n , _1n is supplied with a source voltage from a source power supply circuit 7 via a source line 6, and the memory cell transistors 13 ₀ , 13 ₁ for testing are supplied.
Are connected to the source line 16 from the source power supply circuit 17.
Is supplied to supply the source voltage via the.

In the present embodiment configured as described above, the memory cell for the test is tested during the rewritable number test.
When erasing data written in the transistors 13 ₀ and 13 ₁ , the test memory cell transistors 13 ₀ and 13 ₀ are connected from the source power supply circuit 17 through the source line 16.
13 ₁ Only the source requires a voltage required for erasing, for example, 1
2 can be applied to [V], the memory cell transistors 1 _00, 1 _10, the 1 _0n, 1 _1n source need not apply a voltage necessary for erasure.

[0024] Thus, according to this embodiment, the memory cell transistors 1 ₀₀ should ensure the number of rewritable times, 1 _10, 1 _0n, 1 without affecting the _1n, perform a reliable number of rewritable times test In addition, the number of rewritable times can be guaranteed with high accuracy.

[0025]

As described above, according to the present invention, the source of the memory cell transistor for which the number of rewritable times is to be guaranteed and the memory cell for which this rewritable number of times is to be guaranteed.
The source of the test memory cell transistor for testing the number of rewritable times of the cell transistor is connected to an independent source line, and at the time of the rewritable number test,
When erasing the data written in the test memory cell transistor,
Since the voltage required for erasing can be applied only to the source of the transistor, the data written in the test memory cell transistor can be erased during the rewrite count test. Since it is not necessary to apply the voltage required for erasing to the source of the memory cell transistor for which the number of possible operations is to be guaranteed,
A reliable rewritable number test can be performed without affecting the memory cell transistor for which the rewritable number should be guaranteed, and the rewritable number can be guaranteed with high accuracy.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main part of a conventional flash memory.

FIG. 3 is a schematic cross-sectional view showing a memory cell transistor.

FIG. 4 is a circuit diagram showing an example of a flash memory provided with a test memory cell transistor.

[Explanation of symbols]

1 _00, 1 _10, 1 _0n, 1 _1n memory cell transistors 2 _0, 2 ₁ word line 3 _0, 3 _n bit lines 6 the source lines 13 _0, 13 for ₁ test memory cell transistors 14 of the test Bit line 16 Source line for test

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-55-146700 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 29/00 G11C 16/06

Claims (1)

(57) [Claims] 1. A memory cell transistor for which the number of rewritable times is to be guaranteed, a test memory cell transistor for testing the rewritable number of the memory cell transistor for which the number of rewritable times is to be guaranteed, and In the flash memory configured by providing the above, the source of the memory cell transistor for which the rewritable number is to be guaranteed and the source of the test memory cell transistor are connected to independent source lines. ,
During the rewritable number test, the memory cell for the test
A flash memory characterized in that when erasing data written in a transistor, a voltage required for erasing is applied only to the source of the test memory cell transistor.