JPH05158245A - Production of semiconductor device - Google Patents
Production of semiconductor deviceInfo
- Publication number
- JPH05158245A JPH05158245A JP31826791A JP31826791A JPH05158245A JP H05158245 A JPH05158245 A JP H05158245A JP 31826791 A JP31826791 A JP 31826791A JP 31826791 A JP31826791 A JP 31826791A JP H05158245 A JPH05158245 A JP H05158245A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- groove
- substrate
- sensitivity
- coated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体基板上に形成した
アスペクト比の大きい複数の溝を選択的にレジストで封
口する処理方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing method for selectively sealing a plurality of grooves having a large aspect ratio formed on a semiconductor substrate with a resist.
【０００２】半導体集積回路の形成工程において、ドラ
イエッチング法を用いてアスペクト比の大きい複数の溝
を形成し、この溝を用途により使い分けする場合があ
る。例えば、Si基板上に幅が約１μm で深さが約５μm
の溝（Trench) を多数形成し、一部のものは素子間分離
用に使用し、一部のものはトレンチ・キャパシタ（Tren
ch-capacitor) や電源供給線として使用している。In the process of forming a semiconductor integrated circuit, a plurality of trenches having a large aspect ratio may be formed by using a dry etching method, and the trenches may be selectively used depending on the application. For example, on a Si substrate, the width is about 1 μm and the depth is about 5 μm.
Many trenches are formed, some of which are used for element isolation, and some of which are trench capacitors (Tren).
ch-capacitor) and power supply line.
【０００３】本発明は一方の溝をレジストで封口して絶
縁し、他方の溝を開口状態に保ち、後工程で導電材料を
充填するような用途に使用する写真蝕刻技術( フォトリ
ソグラフィ) に関するものである。The present invention relates to a photolithography technique (photolithography) used for applications such as sealing one groove with a resist to insulate it, keeping the other groove open, and filling a conductive material in a later step. Is.
【０００４】[0004]
【従来の技術】図２は従来の処理工程を示す断面図であ
る。すなわち、LSIやVLSIのような集積度の極めて高い
集積回路の形成においては導体線路の最小線幅がサブミ
クロン(Sub-micron)であるために素子間分離用の溝や電
源供給用の穴の幅は約１μm と狭く、一方、深さは数μ
m と深いのが通例である。2. Description of the Related Art FIG. 2 is a sectional view showing a conventional processing step. That is, in the formation of an extremely integrated circuit such as LSI or VLSI, the minimum line width of the conductor line is sub-micron, so that the trench for element isolation and the hole for power supply are formed. The width is narrow, about 1 μm, while the depth is a few μ.
It is usually deep with m.
【０００５】かゝる溝の一方をレジストで封止し、他方
を開口したまゝとする処理方法として、先ず、低粘度の
レジスト（例えばポジ型）１を基板２の上にスピンコー
トして 封止溝３と開口溝４の総てに充填した後、加熱
乾燥する。（以上図２Ａ） 次に、マスク５を用いて紫外線を照射するなどの方法に
より、封止溝３のある部分を除いて選択露光を行う。
（以上同図Ｂ） 次いで現像することにより、封止溝３の部分を除いて露
光部のレジスト１が溶解除去される。（以上同図Ｃ） 然し、実際には溝の深さが深いことゝ、紫外線がレジス
トに吸収されるために開口溝４の底のレジストは感光し
ない。As a processing method in which one of the grooves is sealed with a resist and the other is left open, first, a low-viscosity resist (for example, positive type) 1 is spin-coated on a substrate 2. After filling all of the sealing groove 3 and the opening groove 4, it is heated and dried. (FIG. 2A above) Next, selective exposure is performed by a method such as irradiating ultraviolet rays using the mask 5 except the portion where the sealing groove 3 is present.
(The above B in the same figure) Next, by developing, the resist 1 in the exposed portion is dissolved and removed except for the sealing groove 3. However, since the groove is actually deep and ultraviolet rays are absorbed by the resist, the resist at the bottom of the opening groove 4 is not exposed to light.
【０００６】そのために、開口溝４の底部にはレジスト
１が残存すると云う問題がある。また、ネガ型のレジス
トを用いる場合も同様であって、紫外線が封止溝３の底
部まで届かぬために重合が進行せず、信頼性の面で問題
がある。Therefore, there is a problem that the resist 1 remains on the bottom of the opening groove 4. The same applies to the case where a negative resist is used, and since ultraviolet rays do not reach the bottom of the sealing groove 3, polymerization does not proceed and there is a problem in terms of reliability.
【０００７】以上のことから、一回の写真蝕刻技術でレ
ジストによる封止溝と開口溝を作ることはできなかっ
た。From the above, it has been impossible to form the sealing groove and the opening groove by the resist by a single photo-etching technique.
【０００８】[0008]
【発明が解決しようとする課題】Si基板上に集積度の極
めて高い素子形成を行うには写真蝕刻技術が多用されて
おり、その内でアスペクト比の大きな溝を反応性イオン
エッチング( 略してRIE)などを用いて形成し、この溝を
選択的にレジストで封口する工程があるが、一回の処理
で封止溝と開口溝を作ることが課題である。Photolithography is often used to form highly integrated devices on a Si substrate. Among them, a groove having a large aspect ratio is formed by reactive ion etching (abbreviated as RIE). ) Or the like and selectively seal the groove with a resist, but the problem is to form the sealing groove and the opening groove by one treatment.
【０００９】[0009]
【課題を解決するための手段】上記の課題は高感度のポ
ジ型レジストを基板上に被覆し、選択露光と現像とを行
って複数の溝の総てにレジストを充填した後、この基板
上に低感度のポジ型レジストを被覆し、開口する溝部の
みを選択露光し、先に封口してある高感度レジストをも
同時に溶解除去することを特徴として半導体装置の製造
方法を構成することにより解決することができる。SUMMARY OF THE INVENTION The above-mentioned problems are obtained by coating a high-sensitivity positive resist on a substrate, performing selective exposure and development to fill the resist in all of the plurality of grooves, and Solution by configuring a method for manufacturing a semiconductor device, characterized in that a low-sensitivity positive-type resist is coated on the substrate, only the opening groove is selectively exposed, and the high-sensitivity resist previously sealed is also dissolved and removed. can do.
【００１０】[0010]
【作用】本発明は高感度のポジ型レジストと低感度のポ
ジ型レジストの使い分けをすることにより問題を解決す
るものである。The present invention solves the problem by selectively using a high-sensitivity positive resist and a low-sensitivity positive resist.
【００１１】従来、アスペクト比の大きな開口溝に充填
したレジストが容易にとれず残留する理由は紫外線がレ
ジストに吸収され、溝の底部にまで届かぬからである。
そこで、感度の特に高いポジ型レジストを溝の中に充填
し、上部には低感度のレジストを薄く被覆するておくこ
とにより、通常の選択露光により溝の底までレジストの
分解が進むようにしたものである。Conventionally, the reason why the resist filled in the opening groove having a large aspect ratio cannot be easily removed and remains is that ultraviolet rays are absorbed by the resist and do not reach the bottom of the groove.
Therefore, by filling the groove with a highly sensitive positive resist and thinly coating a low-sensitivity resist on the top, it was possible to decompose the resist to the bottom of the groove by normal selective exposure. It is a thing.
【００１２】図１は本発明に係る処理工程を示す断面図
であって、アスペクト比の大きな溝が形成されている基
板２に高感度のポジ型レジスト７をスピンコートし、封
止溝（封止すべき溝）３と開口溝（開口すべき溝）４の
総てにレジストを充填する。FIG. 1 is a cross-sectional view showing a processing step according to the present invention. A substrate 2 having a groove with a large aspect ratio is spin-coated with a high-sensitivity positive resist 7 to form a sealing groove (sealing). The resist is filled in all of the groove 3 to be stopped and the opening groove 4 (the groove to be opened).
【００１３】次に、加熱乾燥させた後、マスク６を通し
てて紫外線の照射を行い、封止溝３と開口溝４を除いて
基板２の全域を感光させる。（以上同図Ａ） 次に、現像を行うと封止溝３と開口溝４のみに高感度レ
ジスト７が残留したものができる。（以上同図Ｂ） 次に、この基板２の上に低感度ポジ型レジスト９をスピ
ンコートし、加熱乾燥させた後、マスク８を用いて選択
露光を行い、開口溝４のみを露光させると開口溝４の底
部まで感光する。（以上同図Ｃ） 次に、現像を行うことにより開口溝４のレジストは完全
に溶解し除去される。Next, after heating and drying, ultraviolet rays are irradiated through the mask 6 to expose the entire area of the substrate 2 except the sealing groove 3 and the opening groove 4. (A in the above figure A) Next, when development is performed, the high-sensitivity resist 7 remains only in the sealing groove 3 and the opening groove 4. Next, spin-coating the low-sensitivity positive resist 9 on the substrate 2, heating and drying, and then performing selective exposure using the mask 8 to expose only the opening groove 4. The bottom of the opening groove 4 is exposed. Next, by performing development, the resist in the opening groove 4 is completely dissolved and removed.
【００１４】このような工程をとることによりレジスト
の残留のない開口溝４を形成することができる。（以上
同図Ｄ）By taking such a step, the opening groove 4 in which the resist is not left can be formed. (The above figure D)
【００１５】[0015]
【実施例】RIE により幅が１μm で深さが５μm の素子
分離溝と電源供給ライン用溝とトレンチ・キャパシタ用
溝を多数形成してあるSi基板を試料とした。EXAMPLES A sample was a Si substrate on which a large number of element isolation trenches having a width of 1 μm and a depth of 5 μm, trenches for power supply lines and trenches for trench capacitors were formed by RIE.
【００１６】そして、高感度ポジ型レジストとしては粘
度が５cpのNPRΣ1025( 長瀬化成)を用い、低感度ポジ型
レジストとして粘度が20cpのTSMR-V50( 東京応化) を使
用した。NPRΣ1025 (Nagase Kasei) having a viscosity of 5 cp was used as the high-sensitivity positive resist, and TSMR-V50 (Tokyo Ohka) having a viscosity of 20 cp was used as the low-sensitivity positive resist.
【００１７】まず、Si基板上に NPRΣ1025を１μm の厚
さにスピンコートし、80℃で乾燥した後、マスクを通し
て紫外線照射を行い、溝の部分を除いて露光した後、現
像して溝の部分にのみレジストを残した。First, NPRΣ1025 was spin-coated to a thickness of 1 μm on a Si substrate, dried at 80 ° C., irradiated with ultraviolet rays through a mask, exposed except for the groove portion, and developed to develop the groove portion. Only left the resist.
【００１８】次に、この基板上にTSMR-V50を0.5 μm の
厚さにスピンコートし、80℃で乾燥した後、マスクを通
して紫外線照射を行い、開口溝とすべき溝のみを露光し
た後、現像した結果、開口溝の部分はTSMR-V50のみなら
ず NPRΣ1025も溶解しており、その中にはレジストは全
く存在しなかった。Next, TSMR-V50 was spin-coated on this substrate to a thickness of 0.5 μm, dried at 80 ° C., and then irradiated with ultraviolet rays through a mask to expose only the groove to be an opening groove. As a result of development, not only TSMR-V50 but also NPRΣ1025 was dissolved in the opening groove portion, and no resist was present in it.
【００１９】[0019]
【発明の効果】本発明の実施によりアスペクト比の大き
な溝について選択的にレジストの充填を精度よく行うこ
とができ、これにより工程の短縮が可能となる。According to the present invention, the resist can be selectively filled in the groove having a large aspect ratio with high accuracy, and the process can be shortened.
【図１】本発明に係る処理工程を示す断面図である。FIG. 1 is a sectional view showing a processing step according to the present invention.
【図２】従来の処理工程を示す断面図である。FIG. 2 is a cross-sectional view showing a conventional processing step.
２ 基板 ３ 封止溝 ４ 開口溝 ５，６，８ マスク ７ 高感度ポジ型レジスト ９ 低感度ポジ型レジスト 2 substrate 3 sealing groove 4 opening groove 5, 6, 8 mask 7 high-sensitivity positive resist 9 low-sensitivity positive resist
Claims (1)
数の溝を形成した後、一方の溝をレジストで封孔し、他
方の溝を開口する処理工程において、 高感度のポジ型レジストを前記基板上に被覆し、選択露
光と現像とを行って複数の溝の総てにレジストを充填し
た後、該基板上に低感度のポジ型レジストを被覆し、開
口する溝部のみを選択露光し、先に封口してある高感度
レジストをも同時に溶解除去することを特徴とする半導
体装置の製造方法。1. A high-sensitivity positive-type resist is applied to the substrate in a processing step of forming a plurality of grooves having a large aspect ratio on a semiconductor substrate, sealing one groove with a resist, and opening the other groove. After coating on the top, selective exposure and development are performed to fill the resist in all of the plurality of grooves, a low-sensitivity positive resist is coated on the substrate, and only the opening groove is selectively exposed. A method for manufacturing a semiconductor device, characterized in that the high-sensitivity resist sealed in the above is also dissolved and removed at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31826791A JPH05158245A (en) | 1991-12-03 | 1991-12-03 | Production of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31826791A JPH05158245A (en) | 1991-12-03 | 1991-12-03 | Production of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05158245A true JPH05158245A (en) | 1993-06-25 |
Family
ID=18097297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31826791A Withdrawn JPH05158245A (en) | 1991-12-03 | 1991-12-03 | Production of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05158245A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010114328A (en) * | 2008-11-07 | 2010-05-20 | Mitsumi Electric Co Ltd | Resist application method |
| US9437477B1 (en) | 2015-03-31 | 2016-09-06 | Kabushiki Kaisha Toshiba | Pattern forming method |
-
1991
- 1991-12-03 JP JP31826791A patent/JPH05158245A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010114328A (en) * | 2008-11-07 | 2010-05-20 | Mitsumi Electric Co Ltd | Resist application method |
| US9437477B1 (en) | 2015-03-31 | 2016-09-06 | Kabushiki Kaisha Toshiba | Pattern forming method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990311 |