JPH05153630A - Synchronizing device for asynchronous video signal - Google Patents

Abstract

PURPOSE:To synchronize a horizontal phase with a color subcarrier phase of two video signals having a relative time axis fluctuation or with different phases by using a memory. CONSTITUTION:Counters 3, 4 count a period being an integral number of multiple of a horizontal period and an integral number of multiple of a color subcarrier period respectively. A count WADR of the counter 3 with respect to the horizontal phase and the color subcarrier phase of an input video signal Vin1 and a count RADR of the counter 4 with respect to the horizontal phase and the color subcarrier phase of an output reference video signal Vin2 are made equal to each other. Thus, the signal Vin1 is written in a line memory 5 by using an address WADR and read by using an address RADR to make the phase of an output video signal Vcrr with the horizontal phase and the color subcarrier phase of the output reference video signal Vin2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction device (TBC) and a synchronizing device for synchronizing an output video signal of a magnetic recording / reproducing apparatus or a video signal having a different frequency and phase with a reference video signal. In detail, in a video editing device such as a switcher that switches and outputs different video signals, synchronization of video signals with different time axes used for pre-processing of switching in order to prevent disturbance of video synchronization during switching. The present invention relates to a chemical conversion device.

[0002]

2. Description of the Related Art In a magnetic recording / reproducing apparatus that handles video signals, in the field of broadcasting VTRs and the like, which generally have strict standards,
A time axis correction device (TBC) is incorporated in the reproduction processing circuit of the VTR, and the reproduction video signal is controlled so that the vertical, horizontal, and color subcarrier phases of the reproduction video signal coincide with the external reference video signal. One of the reasons for using TBC is that the video signal reproduced from the recording medium generally does not have sufficient mechanical precision of the medium or the accuracy of speed control of the pickup, so that the reproduced video signal is subject to many time-axis fluctuations. This is because it does not satisfy the vertical, horizontal, and color subcarrier frequencies defined by the broadcast standard and cannot be sent as a broadcast program as it is. Another reason is that in the field of production such as creating program software, video is edited, so you can switch the video from multiple video devices,
In order to prevent the video from being distorted due to the discontinuity of the sync signal at the video editing point when the work of mixing or dubbing from the VTR to the VTR is performed.
This is because it is necessary to synchronize the plurality of video signals with an absolute video reference.

FIG. 11 shows an example of a block diagram of the above-mentioned synchronizing apparatus for a plurality of video signals. FIG. 12 is a timing waveform chart of each part in FIG. In FIG. 11, 1
Is a TBC, and 2 is a switcher.
Outputs Vo by switching between two video signals Vin1 and Vin2
to get ut. The TBC1 synchronizes the video signals Vin1 and Vin2. As a method of synchronizing the two video signals, there is a method of performing time axis correction on each of the two video signals based on an absolute video reference. As one simple method, there is a method in which one video signal is used as a reference and the other video signal is subjected to time-axis processing for synchronization, and FIG. 11 corresponds to the latter. That is, the video signal Vin2 is used as an output reference signal, and the TBC1 corrects the video signal Vin1 on the time axis to synchronize the two video signals.

Here, the video signal is a composite video signal as shown in FIG. 12 in which a luminance signal and a carrier color signal are multiplexed, and Vin1 and Vin2 are digital data (video) sampled at an integer multiple of the color subcarrier frequency. Signal data). The waveform of FIG. 12 is shown in FIG.
The data value of each part of 1 is represented by an analog size. CK1 and CK2 shown in FIG. 11 are Vin1 and Vin2 sampling clocks, respectively.
There have been many proposals for a composite video signal time axis correction device, and a line memory that stores video signal data for several H sections (H is one horizontal period of the video signal) is used (Japanese Patent Laid-Open No. 2006-242242). 58-34688).
Or a combination of a line memory and a frame memory (capable of storing video signal data for one frame) (Japanese Patent Laid-Open No. 168485/1987 and Japanese Patent Laid-Open No. 23-23 / 1987).
No. 0192).

[0005]

Although the one using only the line memory has a simple structure, it is necessary to suppress the horizontal / vertical phase of the input video signal data with respect to the output reference video signal within a certain range. .. For example, nH
In the case of using the line memory (n is an integer), the input video signal data must be input about (nH) / 2 earlier than the reference video signal. This is because processing is always delayed due to the correction of the time axis. Therefore, it is necessary to perform some kind of timing control on the source of the input video data. The width of the phase change of the input that can be corrected is also within the capacity of the line memory. For example, for the reference video signal,
For video signal data that is input later than the minimum early phase of video data required for time axis correction processing or that is delayed from the reference video signal, and data that is out of phase by more than the correctable phase change width. On the other hand, correct correction is not performed, and the horizontal position of the output image is displaced, or the color subcarrier becomes discontinuous and the hue of the image is changed.

The above problem has been solved in the case of using the line memory and the frame memory in combination. Because the memory capacity is large, it is possible to correct even a phase change of one field or more. In addition, a large margin of timing control can be provided for the source of the input video signal data. The operation to shift the vertical position of the horizontal line of the video data to be output with respect to the video reference (called line shift) without any control, or the horizontal of the video signal data so that the subcarrier phase matches the reference video signal Even if the field of the input video signal data is different from the field of the reference video signal by the operation of slightly shifting the phase (called sample shift), the time axis can be corrected with almost no deterioration of the video. However, a large-capacity memory is required, the writing / reading control of the memory is complicated, and the like, so that the circuit scale becomes large, which is not practical in terms of downsizing and cost reduction.

[0007]

In order to achieve this object, a synchronizing device for an asynchronous video signal according to the present invention is approximately n times (n is an integer) the horizontal cycle of input video signal data, and
A first counter that counts a period that is m times (m is an integer) the color subcarrier period, and that is approximately n times the horizontal period of the output reference video signal and that is m the color subcarrier period.
A second counter that counts a double cycle, and the input video signal data is written with the count output of the first counter as an address, and the data is read with the count output of the second counter as an address.
It has an AM (random access memory).

[0008]

According to the present invention, the input video data is RA when the output of the first counter is used as a write address.
When the video data is written in M and the output of the second counter is used as a read address to read the video data from the RAM, the read data is such that the horizontal phase and the color subcarrier phase match the output reference video signal. Become.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In the following description, parts that perform the same operations as those in the other drawings will be assigned the same reference numerals and overlapping description will be omitted.

FIG. 1 is a block diagram of an asynchronous video signal synchronizing apparatus according to a first embodiment of the present invention. In FIG. 1, 3 is a first counter, 4 is a second counter, 5 is a 2H line memory, 6 is a first color frame detection circuit, and 7 is a second color frame detection circuit. FIG. 1 corresponds to the TBC in FIG. Figure 2
FIG. 2 is a timing waveform chart of each part in FIG. Similar to the description of the conventional example, the video signals Vin1, Vin2, Vcr
r is digital data sampled at a clock that is an integral multiple of the color subcarrier frequency, and the form of all video signals is a composite video signal.

The composite video signal is generally composite data in which a horizontal sync signal, a vertical sync signal, color subcarrier phase information (burst) and video information are multiplexed.
In the TSC system video signal, the color subcarrier frequency fsc and the horizontal frequency fh have a relationship expressed by the following equation.

4fsc = 910fh (1) Therefore, 1H is 455/2 times the color subcarrier period, and the phase of the color subcarrier of the video signal is inverted by 180 ° at the same horizontal position every 1H and every 2H. Then, the color subcarrier phases at the same horizontal position match. For example, the sampling frequency of the data Vin1 and Vin2 is 4fsc, which is four times the frequency fsc. In FIG. 1, clocks CK1 and CK2 are clocks each having a frequency of 4 fsc. The counters 3 and 4 respectively divide the clocks CK1 and CK2 and count 1820 clocks which is 2H. The output of the counter 3 is supplied to the 2H line memory 5 as the write address WADR, and the output of the counter 4 is supplied as the read address RADR. The line memory 5 writes data Vin1 according to the address WADR and reads it according to the address RADR.

As described above, according to this embodiment, the write address WADR and the read address RADR of the line memory 5 circulate in a cycle of an integral multiple of H, and the phase of the color subcarrier at the same address is constant. , Even when the data Vin1 and Vin2 have a large time-axis fluctuation and the fluctuation cannot be absorbed within the capacity of the line memory, data in which the horizontal position and the color subcarrier phase match are repeatedly output or read for several H. Since the output is skipped, it is possible to prevent the horizontal position of the output image from being shifted and the color subcarrier from becoming discontinuous and changing the hue of the image, which has been a problem in the past.

CFR1 and CFR2 in FIG. 1 are reset pulses of the counters 3 and 4, respectively, and determine the initial phase of writing and reading of the line memory 5.

FIG. 3 is a block diagram of an asynchronous video signal synchronizing apparatus according to the second embodiment of the present invention. In FIG. 3, the embodiment of FIG. 1 is adapted to the video signal of the PAL system, the constituent elements and operations are the same as those of the embodiment of FIG. 1, 8 is a first counter, and 9 is a first counter. 2 counter, 10 4H line memory, 11 first
2 is a color frame detection circuit, and 12 is a second color frame detection circuit. FIG. 4 is a timing waveform chart of each part in FIG.

Unlike the NTSC system video signal, the PAL system video signal has a relationship expressed by the following equation between the color subcarrier frequency fsc and the horizontal frequency fh.

4fsc = (1135 + 4/625) fh (2) In other words, 1H is almost 1 of the color subcarrier period.
It is 135/4 times, and the phase of the color subcarrier of the video signal is inverted every 2H by 180 ° at the same horizontal position,
The color subcarrier phases at the same horizontal position coincide with each other in every four horizontal periods. For example, as in the embodiment of FIG. 1, the sampling frequency of the data Vin1 and Vin2 is 4fs.
Let be c. In FIG. 3, clocks CK1 and CK2 are clocks each having a frequency of 4 fsc. The counters 8 and 9 divide the clocks CK1 and CK2, respectively, and count 4540 clocks, which are approximately 4H. The output of the counter 3 is supplied to the 2H line memory 5 as the write address WADR, and the output of the counter 4 is supplied as the read address RADR. The line memory 10 has an address WAD
Write data Vin1 according to R, and write address RA
Read according to DR.

According to the present embodiment as described above, even in the PAL system video signal, the NTSC in the embodiment of FIG.
The same effect as that for the video signal of the system is obtained.

CFR1 and CFR2 in FIG. 3 are used for the reset pulses of the counters 8 and 9, respectively, and the detection circuits 11 and 12 respectively detect the color frame (PAL) of the image.
In the case of the method, the 8 field period of the image is detected), and a reset pulse C is detected at the beginning of each color frame.
FR1 and CFR2 are generated. As is clear from the equation (2), the color subcarrier period is S for four horizontal periods (4H).
If it is C, it is expressed by the following equation.

4H = (1135 + 4/625) SC (3) That is, when the read timing deviates from the write timing of the line memory 10, per 4H (4 /
625) The horizontal phase on the read side is shifted by SC. Moreover, when the counters 8 and 9 are not reset, the horizontal phase of the data for the addresses WADR and RADR changes from moment to moment, and the phase of the output video signal Vcrr with respect to the reference video signal Vin2 may become unstable. As is clearer from equation (3), the address WADR
On the other hand, the horizontal phase of the data written in the line memory 10 is 625 times that of 4H, that is, it shifts by 4SC in one color frame (8 fields) of the video signal of the PAL system. In other words, the relationship between the color subcarrier phase and the horizontal phase coincides with one color frame in one cycle.

Therefore, in this embodiment, the detection circuit 1
1 and 12 detect the color frames of the video signals Vin1 and Vin2, respectively, and the reset values CFR1 and CFR2 generated at the heads of the color frames reset the count values of the counters 8 and 9, respectively.
The values corresponding to the horizontal positions of R and RADR are almost constant. That is, it is possible to prevent the horizontal phase of the output video signal Vcrr with respect to the output reference video signal Vin2 from becoming unstable because the horizontal positions of the addresses WADR and RADR are not determined.

FIG. 5 is a block diagram of an asynchronous video signal synchronizing apparatus according to the third embodiment of the present invention. In the figure, reference numerals 8 and 9 denote first and second counters, which have the same configuration as the counters 8 and 9 in FIG. Similarly,
The line memory 10 also has the same configuration as the line memory 10 in FIG. In this embodiment, the counter 8,
The reset pulses FR1 and FR2 supplied to 9 are pulses generated at the beginning of the video field, which is different from the embodiment of FIG. 13 and 14 are reset pulses FR1, F
It is a reset pulse generation circuit for creating R2.
The reset pulse generation circuit 13 generates a reset pulse FR1 on the write side, and the reset pulse generation circuit 14 generates a reset pulse FR2 on the read side. The reset pulse generation circuits 13 and 14 generate pulses FR1 and FR2.
The input that is the reference for generating the input signal is the input video signal Vin1 and the sampling clock CK1 thereof, and the output reference video signal Vin2 and the sampling clock CK2 thereof are different, and the constituent elements are exactly the same. .. 51 in the reset pulse generation circuits 13 and 14,
Reference numerals 52 and 54 are frequency dividing circuits, and 53 is an inverting circuit (gate). Similarly, 60, 61, 62, 64, 65, 66 are latches, and 63, 67 are gates, which constitute a reset pulse output synchronizing circuit. FIG. 6 is a timing waveform chart of the reset pulse generating circuit 13 and the counter 8. Since the reset pulse generation circuit 14 has the same configuration, duplicate description will be omitted.

As described above, in the embodiment of FIG. 3, the pulses CFR1 and CFR2 are one pulse per color frame, so that when a PAL video signal is used,
The address WADR and RADR inevitably have a remainder of 4 SC for each color frame. Clocks CK1 and CK
If the frequency of 2 is set to 4 times the frequency of the subcarrier, addresses 0 to 15 are generated at the end of the color frame as shown in the timing waveform chart of FIG. In other words, since one color frame has 8 fields, the addresses WADR and RADR are displaced from the horizontal phase by 2 clock cycles per field. For example, when the video signal is edited in field units, the output reference video signal Vi
It often happens that the fields of the input video signal Vin1 do not match with n2. The above-mentioned field disagreement is not preferable because it causes a shift in the horizontal phase of the output video signal Vcrr and blurring of the video for each color frame.
In this embodiment, the counters 8 and 9 are supplied with reset pulses FR1 and FR2 generated at the timing when the color subcarrier phase and the horizontal phase match for each field.

As described above, since the horizontal phase of the address WADR representing the 4H period is delayed by 2 clocks in one field, the operation of advancing the phase of the address WADR by 2 clocks is performed for each field. 2 clocks correspond to half of the color subcarrier period SC, and the address WADR
The subcarrier phase with respect to the address WADR is inverted due to the change of the phase, and the color phase of the output video signal Vcrr becomes discontinuous every field as it is. However, for two horizontal periods, from equation (3), almost (1
135/2) SC, and by further changing the address WADR by 2H (2270 clocks), the color subcarrier phase is further inverted with respect to the address WADR, and the relationship between WADR and carrier phase is the phase of WADR. It can be matched before and after the change, and the phase of the address WADR with respect to the horizontal period can be made almost the same as the state one field before.

The reset pulse generating circuit 13 changes the phase of the above-mentioned address WADR, and its operation will be described below. The detection circuit 50 detects the horizontal sync signal HSYNC and the vertical sync signal VSY from the input video signal Vin1.
Detect NC. The timing is as shown in FIG.
The frequency dividing circuit 52 frequency-divides the vertical synchronizing signal VSYNC and outputs a signal DV which is inverted every field. Further, the frequency dividing circuit 51 divides the horizontal synchronizing signal HSYNC into 1/4 and
The signal DH having the H period is output. Similarly, the detection circuit 50 detects a color frame and outputs a reset pulse CFR generated at the head of the color frame. The operation of the reset pulse generating circuit 13 makes one cycle in one color frame, and the pulse CFR determines the initial phase thereof. A signal obtained by inverting the signal DH having a period of 4H with the signal DV by the inverting circuit 53 is a signal G0 having a phase inverted by 2H for each field.
Becomes The signal DV is the latch 60, 61, 62, 64, 6
5, 66 and the gates 63 and 67 synchronize with the output G0 of the inverting circuit 53, and the reset pulse FR
1 is output. Since the signal DH is a horizontal synchronizing signal separated from Vin1 of the video signal, the phase after one field is ahead of the address WADR by two clocks of the clock CK2. That is, the reset pulse FR1 is 1
The reset pulse FR1 is generated for each field and has a constant phase with respect to the horizontal phase of the video signal and the color subcarrier phase. The same applies to the reset pulse FR2. The frequency dividing circuit 54 generates a subcarrier, and the generated subcarrier is a horizontal synchronization signal HSYN.
Since C is not an integer multiple of the clock CK1 or CK2, it is unstable, and is supplied as the clock of the latch 64 in order to stabilize the timing of the output G1 of the gate 63 created from the timing of the horizontal synchronizing signal HSYNC. Always use the signal G in the stable part of the horizontal sync signal HSYNC.
It can be omitted if 1 is generated.

By resetting the count values of the counters 8 and 9 with the pulses FR1 and FR2, the addresses WADR and RADR whose horizontal phase and color subcarrier phase are constant with respect to the video signals Vin1 and Vin2 in each field of the color frame are generated. can get. The operation of the line memory 10 by the addresses WADR and RADR is the same as the operation of the embodiment shown in FIG.

As described above, according to the present embodiment, the reset pulse generating circuits 13 and 14 generate the pulses FR1 and FR2 having a constant phase with respect to the horizontal phase and the subcarrier phase for each field, and the counters 8 and 9 are operated. Since the count value is reset, even when the field of the input video signal Vin1 is different from the output reference video signal Vin2, the color subcarrier phase and the horizontal phase are output at a substantially constant level, and the horizontal phase shift and the image swing of each color frame are eliminated. Can be prevented.

The reset pulse generating circuits 13 and 14
, The detection of the signals HSYNC and VSYNC is omitted, reset by the pulse CFR, and the clocks CK1 and C
A counter that operates in K2 and counts the horizontal cycle and the field cycle is provided. For example, as in the WADR of FIGS. 5 and 6, the counter of the 4H cycle is reset to the field by 2271 counts once. It is also possible to create the pulses FR1 and FR2, and the output of the counter in the 4H cycle is directly applied to the address WA.
It is also possible to supply as DR and RADR and omit the counters 8 and 9.

FIG. 7 is a block diagram of an asynchronous video signal synchronizing apparatus according to the fourth embodiment of the present invention. In the figure, reference numerals 8 and 9 denote first and second counters, which have the same configuration as the counters 8 and 9 in FIG. Similarly,
The line memory 10 also has the same configuration as the line memory 10 in FIG. 15 and 20 are color frame detection circuits, 16 and 18 are latches, 17 is an adder, 21 and 21,
2 is a frequency divider, 23, 24, 25, 26, 27 are gates, 28 is a counter, 29 is a decoder, 30 is a shift register, and 31 is a selector.

The operation of the video signal blanking processing apparatus configured as described above will be described below.

In the case of handling a PAL system video signal, according to the third embodiment shown in FIG. 5, the output reference video signal Vin2 is used.
On the other hand, a stable output video signal Vcrr was obtained even when the phase of the input video signal Vin1 was shifted in field units. However, when the output reference video signal Vin2 and the input video signal Vin1 are completely asynchronous, for example, the signal Vin at the center of the field of the output reference video signal Vin2.
When the 1 field is switched, the output video signal Vc
rr is not stable. In the third embodiment, the write address WADR is shifted backward by (SC / 2) with respect to the horizontal phase at the field head of the input video signal Vin1, and the address RADR is similarly set at the field head of the output reference video signal Vin2. Shift backwards by (SC / 2). As a result, the output video signal Vcrr is shifted to the write address WADR so that the video (SC /
2) The phase is shifted forward by the phase, and the video is shifted backward by the phase of (SC / 2) by the shift of the address RADR at the beginning of the field of the signal Vin2. That is, the obtained output video signal Vcrr has a horizontal phase shift near the center of the screen, and the lower part shifts to the right with respect to the upper part of the screen, resulting in a difficult screen. Therefore, in the present embodiment, the image shift is prevented from occurring even when the signals Vin1 and Vin2 are asynchronous by the configuration described below.

The detection circuit 15 detects the color frame of the signal Vin1 and generates one reset pulse CFR1 at the head of the color frame, and at the same time, in the PAL color frame sequence (8 fields), which field is currently lined. A 3-bit field number INFNO. Output 0-2. The counter 8 has a count value reset by the reset pulse CFR1 and counts the address WADR in the 4H section. The operation is exactly the same as that of the counter 8 in FIG. The clocks CK1 and CK2 are four times the color subcarrier frequency, as in the second and third embodiments. Field number INFNO. The numbers 0 to 2 count the fields in the color frame sequence, which are 0 at the beginning of the color frame and count 0 to 7. The latches 16 and 18 and the adder 17 have a field number IN for the field of the signal Vin2.
FNO. 0 to 2 are synchronized, and a pulse VC near the center of the field of the signal Vin2 detected by the detection circuit 20.
ENT field number INFNO. After latching 0 to 2 and subtracting 1 by the adder 17, the signal Vin
By further latching with the pulse FST at the head of the second field, the field number of the signal Vin1 near the center of the field of the signal Vin2 is output in synchronization with the field of the signal Vin2. The synchronized field number is WFNO. 0 to 2 and subtraction of 1 by the adder 17 is to correct the delay of the average of one field generated in the latches 16 and 18. The detection circuit 20 detects the signal Vin2, and in addition to the pulses VCENT and FST, the pulse HST output at the beginning of one horizontal period, the pulse CFR2 output at the beginning of the color frame, and the field of the current field is an even field. Signal RFNO. Outputs 0. For convenience of explanation, the signal RFNO. 0 is the field number INFNO. Of the signal Vin2 generated by the detection circuit 15. Match the polarity with the least significant bit of 0 to 2 and set the odd field to "L".
The even field is set to "H". Here, the gate 23 outputs a logical sum of the pulse FST and the pulse HST, and supplies one reset pulse to the field to the counter 28. All the inputs and outputs of the gate 23 are "L" active. The output timing is signal Vin at the beginning of the field.
This pulse has a constant phase with respect to two horizontal periods.
The counter 28 counts the horizontal cycle as 1135 clocks of the clock CK2, and the decoder 29 counts the counter 2
The count value of 8 is counted, and the pulse ADVHST is output once in the horizontal cycle. The frequency dividing circuits 21 and 22 divide the pulse ADVHST, and invert the signal LAL every one horizontal cycle and the signal 1 / 2LA invert every two horizontal cycles.
Create L. The phases of the signals LAL and 1 / 2LAL are initialized by one reset pulse CFR2 in the color frame. The gate 24 controls the field number WFNO. Of the signal Vin1 synchronized with the field of the signal Vin2. 0 to
It is to compare whether the timings of the odd and even fields of the field represented by 2 match.
If they do not match, the output of the gate 24 becomes "H", and the signal 1 / 2LAL is inverted by the gate 25. As a result, the output of the gate 26 becomes the pulse WND which becomes "H" only during the 1H period of the 4H period in which the phase output by the phase relationship between the signals Vin1 and Vin2 is controlled. To simplify the description, first, the timing (field number WFN) of the beginning of the color frame of the signal Vin1
O. Consider 0) for 0-2. If the pulse ADVHST is supplied instead of the input pulse SELH of the gate 27 of FIG. 7 ignoring the shift register 30 and the selector 31, the output RR of the gate 27 is a pulse every 4H. The phase is constant for the color subcarrier phase with respect to the signal Vin1, and the horizontal phase is also constant at the beginning of the field. At this time, the counter 9 whose count value has been reset by the reset pulse RR counts the clock CK2, and the 4H interval (4540
Clock) is repeated. In the present embodiment shown in FIG. 7, the field number WFNO. When the value of 0-2 is 0,
FIG. 8 shows a timing waveform chart of each part when the video field of the signal Vin2 is the first field and the second field. Regarding the timing in the case of the other fields of the color frame, since the period of one frame (2 fields) is 625H, the relationship of the pulse WND with respect to the beginning of the field (vertical synchronization signal) is compared with the signal one frame before. Since it only shifts by 1H, it is omitted. Output address RADR of counter 9 and signal Vi
The phase relationship with n2 is the same as the phase relationship between the output address WADR and the signal Vin2 after the reset pulse FR1 of the counter 8 in the third embodiment in FIG. 5 is supplied. Since the operation is the same principle as that of the third embodiment of FIG. 5, detailed description thereof will be omitted, but the frequency dividing circuit 51 in the reset pulse generating circuits 13 and 14 of FIG. 5 corresponds to the frequency dividing circuits 21 and 22 of FIG. The gate 53 corresponds to the gate 25. In the embodiment of FIG. 5, a reset pulse F is set so that the horizontal position and the color subcarrier phase are constant with respect to the video signals Vin1 and Vin2 at the beginning of each field.
R1 and FR2 were generated. Therefore, the inversion pulse supplied to the gate 53 is a signal generated by the frequency dividing circuit 51 for discriminating the odd / even field of the video signal. In this embodiment shown in FIG. 7, the field number WFNO. 0-2
Is 0, the relationship between the address RADR at the beginning of the field of the video signal Vin2, the horizontal phase of the signal Vin2, and the subcarrier is at the beginning of the first field of the signal Vin1 (the field where the value of INFNO.0-2 is 0). Output address WADR of counter 8 and signal Vin
1 are configured to have the same phase relationship, and the inversion pulse supplied to the gate 25 is the odd / even field discrimination signal of the signal Vin2 supplied from the detection circuit 20 created by the gate 24 and the field number WFNO. The least significant bit WF that is an odd / even field discrimination signal of 0 to 2
NO. This is a signal that is compared with 0.

In this embodiment, the output address WADR of the counter 8 is reset once at the beginning of the color frame, unlike the embodiment shown in FIG. 3, so that the address WADR is signal Vin1 as the field advances with respect to the first field. With respect to the horizontal phase of, a shift of 2 clocks is performed per field. The reason why the values for the horizontal phase of the address WADR are not aligned for each field is that the output video signal V is generated when the signals Vin1 and Vin2 are asynchronous.
This is to prevent the horizontal phase shift of crr from occurring in the upper and lower parts of the screen. However, as apparent from the above description, the output ADVHST of the decoder 29 is a pulse generated so as to have a constant phase with respect to the horizontal phase at the beginning of the field of the signal Vin2, and therefore the pulse SE is directly applied.
If supplied as LH, output address RAD of counter 9
Output video signal Vcr read from the line memory 9 at R
The horizontal phase of r is shifted backward by 2 clocks for each field. At the same time, the color subcarrier phase of the signal Vcrr is also inverted, and the color phase becomes discontinuous. Therefore, in the present embodiment, the pulse ADVHST is generated by the shift register 30.
10 pulses with a phase difference of 2 clocks each are generated, and the selector 31 selects the field number WFNO. 0-2 and INFNO. 0 to 2 most significant bit INFNO. The pulse SE can be
Create LH. A detailed block diagram of the shift register 30 and the selector 31 is shown in FIG. FIG. 10 is a timing waveform chart of each part in FIG. In FIG. 9, 70-
Reference numeral 87 denotes a pulse P0 to a pulse ADVHST which are sequentially delayed by a clock CK2 so that ten phases differ by two clocks from P0 to P0.
It is a latch that outputs P9 and constitutes the shift register 30. 90 is a decoder, which has a field number WFN
O. The signal of "H" is output to the signal lines F0 to F7 corresponding to the values of 0 to 2. For example, when the value of the field number is 0, the signal F0 becomes "H". 88, 89, 91-99
Is a gate, and outputs F0 to F7 of the decoder 90 and the field number INFNO. 0 to 2 most significant bit INF
NO. One of the pulses P0 to P9 is selected from the value of 2 and finally the pulse SELH selected by the gate 99 is selected.
Is output. Decoder 90, gates 88, 89, 91-
99 constitutes the selector 31. The asynchronous video signal synchronizing apparatus of this embodiment will be further described with reference to FIGS. 7 to 10. The pulse SELH is the field number WFNO. It is necessary to advance the timing by 2 clocks each time the value of 0 to 2 increases to 0 to 7, and eight pulses P8 to P1 having different phases are generated in eight fields. Actually, for the reason described later, pulses P9 and P0 having different phases for two clocks are also created before and after the pulse groups P8 to P1, and there are a total of 10 pulses having different phases P0 to P9. The pulse P9 having the earliest phase is the pulse ADVH as shown in FIG.
ST may be used as it is. Normally, the input video signal V
in1 field number INFO. 0 to 2 and a field number WFNO.0 which is synchronized with the field pulse FST of the output reference video signal Vin2. 0 to 2 have the same number, and the field number WFNO. When the value of 0 to 2 is 0, it is the head of 8 fields, so that 8 pulses P1
The pulse P1 having the latest phase among P8 to P8 is the selector 31.
Is selected for pulse SELH with and field number WFN
O. As the value of 0-2 increases, P2, P3, P
4, P5, P6, P7, P8 are selected in this order. Therefore, the pulse ADVHST is the field number INFN.
O. When the value of 0 to 2 is 0, the signal V of the address WADR created by the counter 8 when initialized by the pulse CFR1
In order to match the phase with respect to in1 and the phase with respect to the signal Vin2 of the address RADR created by the counter 9,
In this embodiment, the output is performed 20 clocks earlier. In FIG. 7, the horizontal phase of the reset pulse timing signal Vin2 generated in the gate 23 is the reset pulse C.
It is assumed that the horizontal phase of the signal Vin1 of FR1 is equal to that of the counter 28 at the next clock generated in the gate 23.
If the output HAD of the above is 0, the decoder 29 may be configured so that the position where the pulse ADVHST of the decoder 29 is generated is the position of the counter output HAD of 1124.

As described above, according to this embodiment, the field number WFNO. Address W when the value of 0-2 is 0
The horizontal phase and the subcarrier phase for the signal Vin2 of the address WADR2 are controlled so as to be equal to the horizontal phase and the subcarrier phase for the signal Vin1 of ADR, and the WFNO. Reference pulse ADVHST in which the horizontal phase is aligned for each field as the value of 0 to 2 increases
To advance the phase of the address RADRS by 2 clocks each, the horizontal and color subcarrier phases of the output video signal Vcrr are constant in the first field of the color frame of the signal Vin1 even when the color fields of the signals Vin1 and Vin2 are different. Controlled to be.
After that, in the color frame, the writing and reading of the line memory 10 are performed at the addresses WADR and RADR of continuous 4540 clock cycles without aligning the horizontal phase for each field. Therefore, the signals Vin1 and V
Even if in2 is asynchronous, the horizontal phase shift of the output video signal Vcrr does not occur unlike the third embodiment.

However, although the addresses WADR and RADR are continuous in the color frame in this embodiment, a fraction of 4 SC (16 clocks) is generated at the end of the color frame for the same reason as in the second embodiment.
The above-mentioned discontinuity is, for example, when the signals Vin1 and Vin2 are asynchronous and the synchronized field number WFNO. Although the value of 0-2 is 0, the line memory 10 is actually
The written signal Vin1 is delayed, and the final field (field number INFNO.
Field value WF when the writing of the value of 7 is not completed, or vice versa.
NO. Even if the value of 0 to 2 is 7 (the last field of the color frame), the line memory 10 actually receives the signal Vi.
When the phase of n1 is advanced and the writing of the data of the first field of the color frame has been started, a phase shift of 4 SC (for 16 clocks) occurs in the horizontal phase of the output video signal Vcrr. Therefore, in the present embodiment, the configuration described below prevents the phase shift of the output video signal even when the signals Vin1 and Vin2 are asynchronous. As is apparent from the above description, the phase shift may occur in the field number WFNO.1 of the input video signal Vin1 synchronized with the output reference video signal Vin2. The values 0 to 2 are 0 at the beginning and 7 at the end. In the case of the first field, the field number INFNO. 0-2
When the field before synchronization represented by is still the final field, the phase of the output video signal Vcrr is shifted backward by 16 clocks. In this case, the pulse ADVHS
The phase of T may be set to 16 clocks before. The gate 89 of FIG. 9 performs an operation before the pulse ADVHST. The field number INFNO. 0 to 2 most significant bit INFNO. 2 is determined by "H" and "L". Similarly, when the synchronized field is the final field, an operation of delaying the pulse ADVHST by 16 clocks is necessary, and the operation is performed by the gate 88.

As described above, according to this embodiment, the shift register 30 causes the address WA in one field to be changed.
A horizontal pulse shifted by 2 clocks, which corresponds to the shift of the DRS from the horizontal phase, is generated for P1 to P8 for 8 fields, and P0 and P9 which are the phases before and after the horizontal pulse, and the synchronized field number WFNO. The pulse corresponding to the field number WFNO. 0-2
, The field number INFNO.
By providing a selector 31 which detects a shift of 0 to 2 at the head of the color frame and switches the pulse P8 and P0 or the pulses P1 and P9, the phase shift of 4 SC of the output image due to the phase shift of the head of the color frame is also removed. be able to. That is, even if the input video signal Vin1 and the output reference video signal Vin2 are completely asynchronous, the signal Vin1
Is synchronized with the signal Vin2, and an output video signal Vcrr with a small horizontal phase shift of the video can be obtained.

[0037]

As described above, according to the present invention, the number of periods that is approximately n times (n is an integer) the horizontal period of the input video signal and m times (m is an integer) the color subcarrier period is counted. 1 counter, a second counter that counts a cycle that is approximately n times the horizontal cycle of the output reference video signal and m times the color subcarrier cycle, and the count output of the first counter as an address. Since the input video signal data is written and the data is read by using the count output of the second counter as an address, the RAM (random access memory) is used. Therefore, the horizontal phase and color of the video can be reduced with a small memory capacity. The subcarrier phases can be efficiently synchronized.

The first detection circuit for generating a reset pulse once in the color frame sequence of the input video signal supplied to the first counter, and the output reference video signal supplied to the second counter. By further including the second detection circuit for generating the reset pulse once in the color frame sequence, the horizontal phase of the output video can be easily determined, and an output video signal of a stable horizontal phase can be obtained.

Further, even when the period of n times the horizontal period and the period of m times the color subcarrier period are slightly different as in the case of the PAL system video signal, the input video signal is supplied to the first counter. A first reset pulse generation circuit that generates a reset pulse once at the beginning of the video field to be generated, and the second reference pulse signal based on the output reference video signal.
Further comprising a second reset pulse generation circuit for generating a reset pulse once at the beginning of the video field supplied to the counter of each of the first and second reset pulse generation circuits, wherein each reset pulse generation circuit divides the horizontal frequency of the video signal by 1/4. Frequency dividing circuit, a second frequency dividing circuit that divides the field frequency to generate a discrimination signal of an odd field and an even field of a video field, and a 1/4 frequency division signal of the horizontal frequency for discriminating the field. By correcting the horizontal phase for each field by an inversion circuit that inverts with a signal and a synchronization circuit that generates the reset pulse at a change point after synchronizing the discrimination signal of the field with the output of the inversion circuit, Even if the color fields of the input video signal and the output reference video signal are different, the output video signal can be output without changing the horizontal phase or color phase. It can be initialized.

Similarly, when handling a PAL video signal, a reset pulse indicating the beginning of the color frame sequence of the input video signal supplied to the first counter and a sequence number of the color frame are generated. 1 detection circuit, a second detection circuit for generating a pulse indicating the beginning of the color frame sequence of the output reference video signal, the beginning of the field, the beginning of the horizontal period, the beginning of the field of the output reference video signal and the horizontal A horizontal counter that counts one horizontal period reset at the beginning of the field from the pulse at the beginning of the cycle, a decoder that creates horizontal pulses generated at the same count value of the horizontal counter, and a color frame of the output reference video signal. It is reset by the pulse indicating the beginning of the sequence, and the horizontal pulse is divided by 4 to obtain 4 A line counter that generates a gate pulse that occurs only in one horizontal period of a flat period, a shift register that delays a horizontal pulse of the input video signal and generates a plurality of horizontal pulses having different phases, and a color of the input video signal. A latch circuit that latches a frame sequence number with a pulse indicating the beginning of the field of the output reference video signal, and a sequence number latched by the latch circuit and a sequence number before being latched,
A selector that selects one horizontal pulse from a plurality of horizontal pulses having different phases, and a horizontal pulse that is selected by the selector with a gate pulse from the line counter and is supplied to the second counter. By using a gate circuit that generates a reset pulse once per cycle, the input video signal is completely asynchronous with respect to the output reference video signal, and the output reference signal is output even when the vertical phase is different, for example. The optimum phase of the video signal is selected, the average horizontal phase shift is small, and there is an effect that an output video signal having no discontinuous horizontal phase shift generated at the field change point or the head of the color frame is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an asynchronous video signal synchronization device according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing the timing of each part in the first embodiment.

FIG. 3 is a block diagram showing a configuration of an asynchronous video signal synchronization device according to a second embodiment of the present invention.

FIG. 4 is a waveform chart showing the timing of each part in the second embodiment.

FIG. 5 is a block diagram showing a configuration of an asynchronous video signal synchronization device according to a third embodiment of the present invention.

FIG. 6 is a waveform diagram showing timings of a reset pulse generation circuit 13 and a counter 8 in the third embodiment.

FIG. 7 is a block diagram showing a configuration of an asynchronous video signal synchronization device according to a fourth embodiment of the present invention.

FIG. 8 is a waveform chart showing the timing of each part in the fourth embodiment.

FIG. 9 is a block diagram showing a detailed configuration of a shift register 30 and a selector 31 in the fourth embodiment.

10 is a waveform chart showing the timing of each part in FIG.

FIG. 11 is a block diagram showing an example of a conventional asynchronous video signal synchronization device.

FIG. 12 is a timing waveform chart of each part in FIG.

[Explanation of symbols]

3,8 First counter 4,9 Second counter 5,10 Line memory 6,11,15 First detection circuit 7,12,20 Second detection circuit 13,14 Reset pulse generation circuit 16,18, 60-62, 64-66, 70-87 Latch 17 Adder 21, 22, 51, 52, 54 Frequency divider 23-27, 63, 67, 88, 89, 91-99 Gate 28 Counter 29, 90 Decoder 30 Shift register 31 Selector 50 Detection circuit 53 Inversion circuit

Claims (4)

[Claims] 1. A substantially n-fold (n) horizontal cycle of an input video signal.
Is an integer) and m times the color subcarrier period (m
A second counter that counts a period that is substantially n times the horizontal period of the output reference video signal and that is m times the color subcarrier period. Of the input video signal data is written with the count output of the counter as an address, and the data is read with the count output of the second counter as the address, and an asynchronous video signal is provided. Synchronizer. 2. A first detection circuit for generating a reset pulse once in a color frame sequence of an input video signal supplied to a first counter, and a color frame sequence of an output reference video signal supplied to a second counter. The asynchronous video signal synchronization device according to claim 1, further comprising a second detection circuit for generating a reset pulse once. 3. A first reset pulse generation circuit for generating a reset pulse once at the beginning of a video field supplied from an input video signal to a first counter, and an output reference video signal supplied to a second counter. Second generation of one reset pulse at the beginning of the video field
Each of the reset pulse generation circuits includes a first frequency dividing circuit for dividing the horizontal frequency of the input video signal by 1/4, and a field frequency of the input video signal for frequency division. Then, a second frequency dividing circuit for generating an odd field / even field discrimination signal, an inverting circuit for inverting the output of the horizontal frequency divided signal by the field discrimination signal, and the field discrimination 2. The asynchronous video signal synchronizing device according to claim 1, further comprising a synchronizing circuit that generates the reset pulse at a change point after synchronizing the signal with the output of the inverting circuit. 4. A reset pulse indicating the beginning of a color frame sequence of an input video signal supplied to a first counter, a first detection circuit for generating a sequence number of the color frame, and a color frame of an output reference video signal. The beginning of the sequence,
A second detection circuit that generates a pulse indicating the beginning of the field and the beginning of the horizontal period, and one horizontal period reset at the beginning of the field from the beginning pulse of the field of the output reference video signal and the leading pulse of the horizontal period. A horizontal counter that counts, a decoder that creates a horizontal pulse generated at the same count value of the horizontal counter, a pulse that indicates the beginning of a color frame sequence of the output reference video signal, and the horizontal pulse is divided by four. A line counter that generates a gate pulse that occurs only in one horizontal period of four horizontal periods; a shift register that delays the horizontal pulse of the input video signal and generates a plurality of horizontal pulses having different phases; The sequence number of the color frame of the video signal indicates the beginning of the field of the output reference video signal. And a selector for selecting one horizontal pulse from a plurality of horizontal pulses having different phases corresponding to the sequence number latched by the latch circuit and the sequence number before being latched by the latch circuit, The gate circuit which gates the horizontal pulse selected by the selector with the gate pulse from the line counter, and further generates a reset pulse once every four horizontal cycles supplied to the second counter. Asynchronous video signal synchronization device.