JPH05153191A - Data reception circuit - Google Patents

Abstract

PURPOSE:To attain the high speed of data transmission by constituting a separator detection circuit, a data clock generation circuit, and the data output circuit of logic circuits respectively, and executing the comparison of data and the detection of an error by these circuits. CONSTITUTION:The Se detection circuit 1 compares successively constituent data in an inputted data string with the same data as a separator (Se), and detects SeS in the data string. The data clock generation circuit 2 generates data clock signals CKA, CKB for fetching main data from the Se detection signal S1 of the output of the circuit 1 and an Se arriving condition in the data string. Besides, the circuit 2 outputs an error signal ER when there is no Se detection signal. The data output circuit 3 accummulates the main data A, B in the data string fetched by the output clock signal of the circuit 2 plural times, and after that, when the main data coincide with each other, it outputs this data as received data. Thus, the high speed of the data transmission and large-scale integration can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving circuit used when transmitting and receiving data, and particularly to a data receiving circuit suitable for use in an environment where bit errors are likely to occur due to passing through a transmission line or the like. Regarding

[0002]

2. Description of the Related Art Conventionally, in this type of data receiving circuit, software repeatedly performs data comparison and error detection in order to cope with bit errors occurring in a transmission line or the like. FIG. 3 shows the configuration of a conventional data receiving circuit. As shown in this figure, the data string Do is
The data string Do received by the in-first memory 30 is read into the processor by the software program, and data comparison and error detection are performed.

[0003]

As described above, in the conventional data receiving circuit, since the processor performs data comparison and error detection processing, the load on the processor is large and the processing time is long. However, there is a problem that the transmission efficiency is not improved due to the limitation of the speed.

The present invention has been proposed in order to solve the problems of the conventional technique, and an object of the present invention is to provide a data receiving circuit capable of speeding up data transmission.

[0005]

In order to achieve this object, the present invention is intended to receive a data string formed by repeating the same data block composed of a separator which is identification data of a specific value and main data. In the data receiving circuit, the data string is input, and the separator detection circuit that detects the separator in the data string by sequentially comparing the constituent data in the data string with the same data as the separator, and the separator. A data clock creation circuit that creates a data clock signal for main data acquisition from the separator detection signal output from the detection circuit and the separator arrival condition in the data string, and outputs an error signal when there is no separator detection signal, and In the data string captured by the data clock signal output from the data clock generation circuit, Data accumulation several times, it is constituted and a data output circuit for outputting the first time the main data as received data when these main data matches accumulated several times.

Further, the data receiving circuit according to the present invention has flip-flops having the same number of stages as the number of constituent data of one data block, the above-mentioned data string is inputted to the flip-flops of the first stage, and each of these multi-stage flip-flops is inputted. A separator detection circuit that detects a separator in a data string by supplying a clock signal that is synchronized with the timing of the constituent data of the data string and comparing the output of the final stage flip-flop with the same data as the separator, and this separator. The counter circuit has a counter circuit that counts the clock signal in synchronization with the arrival of the separator in the data sequence based on the separator detection signal output from the detection circuit and the counter output of itself, and the arrival of the separator based on the output of this counter circuit. Create a data clock signal for main data acquisition synchronized with The data clock generation circuit that outputs an error signal when there is no separator detection signal, and the main data in the data sequence output from the flip-flop of the separator detection circuit is changed by the data clock signal output from the data clock generation circuit. It has a comparison circuit that compares these main data after it has been captured and accumulated multiple times, and outputs this main data as received data only when the comparison circuit confirms the match of these main data accumulated multiple times. And a data output circuit.

[0007]

According to the above-mentioned structure, even if the same data as the separator appears in the main data in the data string and the main data is erroneously detected as the separator in the separator detection circuit, the data clock generation circuit does not detect the data in the data string. Since the clock signal for taking in the data is created based on the arrival condition of the separator, there is no mistake in taking in the main data in the data output circuit. Further, in the data output circuit, the main data acquired by the data clock signal is accumulated multiple times, and the main data is output as the reception data only when these main data match, so that the main data can be accurately received. ..

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of a data receiving circuit according to the present invention will be described in detail below with reference to the drawings. An embodiment of this data receiving circuit is shown in the block diagram of FIG. 1, and the structure of an input data string is shown in FIG. In these figures, the data receiving circuit is composed of a separator detecting circuit 1, a data clock generating circuit 2 and a data output circuit 3. In the input data string Do input to this data receiving circuit, 1 data is made up of 8-bit byte units, and 2 bytes of main data A and B are data together with a 1-byte separator S that is identification data of a specific value. One block is formed, and a data block composed of these 3 bytes is repeatedly input. In this embodiment, the input data string Do in which one block is made up of 3 bytes is used as described above. However, one data does not have an 8-bit structure,
The bit configuration may be different, and the data in one block may be 3 bytes or more.

The separator detection circuit 1 which takes in the data string Do shown in FIG. 3 (a) from the data input terminal IN1 has three stages of flip-flops corresponding to the structure of one block of the data string Do is 3 bytes. 4, 5, 6 and a comparison circuit 7 for comparing the output of the final stage flip-flop 6 with the separator S. Each flip-flop 4, 5, 6 has a data string Do as shown in FIG.
A clock signal CK1 whose byte unit is 1 cycle is input. As a result, when the separator S of the data string Do is detected from the comparator circuit 7, the separator detection output S1 synchronized with the rising edge of the clock signal CK1 is taken out, and this separator detection signal S1 shown in FIG. It is supplied to the creating circuit 2. The A data output from the second-stage flip-flop 5 is supplied to the flip-flop 18 of the A data output circuit 3A. 1
The B data output from the flip-flop 4 at the stage is
It is supplied to the flip-flop 24 of the B data output circuit 3B.

The data clock generating circuit 2 detects the counter output CU and the synchronous counter circuit 8 in which "0" is loaded according to the status of the separator detection signal S1 and the counter output CU, respectively, and compares them. It is composed of circuits 9, 10, 11, and 12. The separator detection output S1 is input to the 3-input OR circuit 14 via the knot circuit 13, and the output signals of the comparator circuits 9 and 10 for detecting the counter outputs “0” and “1” are input to the OR circuit 14. There is. The load signal S2 shown in FIG. 3 (f) output from the 3-input OR circuit 14 is input to the load terminal L of the synchronous counter circuit 8. Further, the NOR circuit 15 is supplied with the clock signal CK1 and the error signal ER from the comparison circuit 12 which detects the counter output "3", and the inverted clock shown in FIG. The signal CK2 is supplied to the clock terminal C of the synchronous counter 8. In addition, the counter output “1”,
The output signals of the comparator circuits 10 and 11 for detecting "2" are input to the AND circuits 16 and 17, respectively, and the clock signal CK1 is input to the AND circuits 16 and 17, respectively. The output CU of the counter circuit is shown in FIG.
As shown in, when the counter output CU is "0" and "1", the A data and the B data are input, respectively.
With the configuration of the data clock generation circuit 2, when the same data as the separator S arrives in the data string Do and the contents of the A data and the B data become the same as the separator S, the data is sent from the separator detection circuit 1. The load signal S2 of the counter circuit 8 can be regulated by the output values "0" and "1" of the counter circuit 8 so as not to be synchronized with the incoming pseudo separator detection signal. Accordingly, the separator S is sequentially detected, and in synchronism with the detection of the separator S, a logical product of the "1" detection output of the counter output from the comparison circuit 10 and the clock signal CK1 is performed. The AND circuit 17 shown in FIG. 3D which obtains the A data clock signal CKA for fetching the A data and performs the logical product of the "2" detection output of the counter output from the comparison circuit 11 and the clock signal CK1. B shown in e)
A B data clock CKB signal for data acquisition is obtained.

When a separator S cannot be detected due to a bit error or the like, the counter circuit 8 is not loaded and the comparator circuit 12 counts "3" as the counter output and the error signal ER is output from the terminal OUT3. Is output.

The A-data output circuit 3A receives three-stage flip-flops 18, 19, 20 to which the A-data clock signal CKA is input as a clock, and three outputs of these flip-flops 18, 19, 20. It is composed of a comparison circuit 21 for detecting coincidence of three outputs and a flip-flop 22 for outputting data. The data output flip-flop 22 is supplied with the output from the third-stage flip-flop 20, and from the NAND circuit 23 to which the A data clock signal CKA and the comparison output signal of the comparison circuit 21 are input. The output is input as a clock signal. As a result, when three coincidences of the A data that sequentially arrive are detected, the A data is first output as received data from the output terminal OUT1 connected to the data output flip-flop 22.

Similarly, in the B data output circuit 3B, the three-stage flip-flops 24, 25, 26 to which the B data clock signal CKB is input as a clock respectively match the three outputs of these flip-flops 24, 25, 26. And a flip-flop 28 for outputting data. The output from the NAND circuit 29, to which the B data clock signal CKB and the comparison output signal of the comparison circuit 27 are input, is input to the data output flip-flop 28 as a clock signal, and the B data that sequentially arrives is input. When three times of coincidence are detected, B data is first output as received data from the output terminal OUT2 connected to the data output flip-flop 28.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the scope of the invention.

[0015]

As described above, according to the present invention, a separator detection circuit is used for receiving a data string in which the same data structure including identification data is repeatedly sent.
The data clock generation circuit and the data output circuit can each be configured by a logic circuit, and this logic circuit can compare data and detect an error. Therefore, when a processor performs data comparison and error detection processing as in the conventional case. In comparison, the speed of the data receiving circuit can be increased. In addition, the data receiving circuit can be made into an LSI.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data receiving circuit according to the present invention.

FIG. 2 is a diagram showing a structure of a data string.

3 is an operation waveform diagram for explaining an operation of the data receiving circuit of FIG.

FIG. 4 is a block diagram showing a configuration of a conventional data receiving circuit.

[Explanation of symbols]

 1 Separator Detection Circuit 2 Data Clock Creation Circuit 3 Data Output Circuit 3A A Data Output Circuit 3B B Data Output Circuit 4, 5, 6 Flip-Flop 7 Comparison Circuit 8 Synchronous Counter Circuit 9, 10, 11, 12 Comparison Circuit 13 Not Circuit Circuit 14 3-input OR circuit 15 NOR circuit 16,17 AND circuit 18,19,20 Flip-flop 21 Comparison circuit 22 Output flip-flop 23 NAND circuit 24,25,26 Flip-flop 27 Comparison circuit 28 Output flip-flop 29 NAND circuit

Claims (2)

[Claims] 1. A data receiving circuit for receiving a data string composed of repetitions of the same data block composed of a separator, which is identification data of a specific value, and main data. A separator detection circuit that detects the separator in the data string by sequentially comparing the constituent data in the string with the same data as the separator, the separator detection signal output from this separator detection circuit, and the separator in the data string. Data clock creation circuit that creates a data clock signal for main data acquisition based on the arrival conditions and outputs an error signal when there is no separator detection signal, and data acquired by the data clock signal output from this data clock creation circuit Main data in a column is accumulated multiple times, and these main data accumulated multiple times A data receiving circuit comprising: a data output circuit that outputs the main data as received data only when the data match. 2. A data receiving circuit for receiving a data string consisting of a repetition of the same data block composed of a separator, which is identification data of a specific value, and main data, and the number of constituent data of one data block. Having the same number of stages of flip-flops, the above-mentioned data string is input to the first-stage flip-flops, a clock signal synchronized with the timing of the configuration data of the data string is supplied to each of these multi-stage flip-flops, and the final-stage flip-flops. The output of is compared with the same data as the separator to detect the separator in the data string, and based on the separator detection signal output from this separator detection circuit and its own counter output, A counter that counts the clock signals in synchronization with the arrival of the separator. A data clock generation circuit having a circuit, which generates a data clock signal for fetching main data in synchronism with the arrival of the separator based on the output of the counter circuit, and outputs an error signal when there is no separator detection signal; It has a comparison circuit for comparing the main data in the data string output from the flip-flop of the detection circuit with the data clock signal output from the data clock generation circuit, after accumulating the data multiple times. And a data output circuit that outputs the main data as received data only when a match between the main data accumulated a plurality of times is confirmed by the comparison circuit.