JPH05152874A - Amplifier circuit - Google Patents

Abstract

PURPOSE:To quicken a data rate of a magnetic disk device by reducing an input capacitance of a read amplifier so as to improve the high frequency characteristic of a magnetic head drive integrated circuit. CONSTITUTION:A read amplifier RA or the like including plural pairs of input transistors(TRs) T1, T2 is provided with 1st cascode TRs T3, T4 between collectors of input TRs T1, T2 and internal nodes n1, n2 respectively and 2nd cascode TRs T5, T6 are provided respectively between the internal nodes n1, n2 and an inverting output terminal ROB and a noninverting output terminal ROT of the circuit. Thus, even when the substantial wire length of the internal nodes n1, n2 is extended and its wire resistance Rs is increased, the TRs T3, T4 are used to reduce a mirror capacitance of each unit read amplifier thereby reducing the input capacitance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit, and more particularly to a technique which is particularly effective when used for a read amplifier or the like included in a magnetic head drive integrated circuit of a magnetic disk device.

[0002]

2. Description of the Related Art There is a magnetic disk device using a magnetic disk as a storage medium. Further, there is a magnetic head drive integrated circuit which is provided in such a magnetic disk device and includes a write amplifier for applying a predetermined write current to the magnetic head and a read amplifier for amplifying the read signal.

A magnetic head driving integrated circuit including a read amplifier is described in, for example, Japanese Patent Application Laid-Open No. 60-201105.

[0004]

FIG. 4 shows a partial circuit diagram of the read amplifier RA of the magnetic head drive integrated circuit MHD developed by the inventors of the present invention prior to the present invention. In the figure, read amplifiers RA of the magnetic head drive integrated circuit MHD are magnetic heads MH1 to MH.
n unit read amplifiers URA provided corresponding to n
1 to URAn, and each unit read amplifier is of a differential form and corresponds to the base of the magnetic heads MH1 to MHn.
Input transistors T1 and T2 for receiving the read signal of
Including each. The commonly coupled emitters of the input transistors T1 and T2 are coupled to the low-potential side power supply voltage VEE of the circuit through a constant current source S1 which is selectively activated according to a selection signal (not shown), and its collector is
It is commonly coupled to the internal node n1 or n2, that is, the emitters of the cascode transistors T5 and T6. The collectors of the cascode transistors T5 and T6 are connected to the high-potential-side power supply voltage V of the circuit via the corresponding load resistors R1 and R2.
In addition to being coupled to CC, it is coupled as an inverting output terminal ROB or a non-inverting output terminal ROT of the read amplifier RA to an inverting or non-inverting input terminal of the main amplifier MA in the subsequent stage.

As a result, the unit read amplifiers URA1 to URA1.
The URAn is selectively operated according to the selection signal, amplifies the read signal of the corresponding magnetic head MH1 to MHn, and transmits it to the main amplifier MA. The cascode transistors T5 and T6 act to reduce the input capacitance of the unit read amplifiers URA1 to URAn and improve the high frequency characteristics of the magnetic head drive integrated circuit MHD.

However, the inventors of the present application have found that the following problems remain in the read amplifier RA. That is, in the magnetic head drive integrated circuit MHD, the unit read amplifiers URA1 to URAn
Are arranged close to the complementary input terminals HY1 and HY1 to HYn and HYn in order to shorten the distance from the corresponding magnetic heads MH1 to MHn, and the cascode transistor T
5 and T6 are arranged close to the main amplifier MA in order to reduce the wiring capacitance on the output side. Therefore, the collectors of the input transistors T1 and T2 and the internal nodes n1 and n
The substantial wiring length between the two becomes long, and the wiring resistance R
w becomes large. As a result, the unit read amplifier URA1
~ The mirror capacitance of URAn, that is, the input capacitance increases, and the high frequency characteristics of the magnetic head drive integrated circuit MHD deteriorate,
The data rate of the magnetic disk device including the magnetic head drive integrated circuit MHD is restricted.

An object of the present invention is to reduce the input capacitance of a read amplifier including a plurality of unit read amplifiers. Another object of the present invention is to improve the high frequency characteristics of a magnetic head drive integrated circuit including a read amplifier and to increase the data rate of a magnetic disk device including a magnetic head drive integrated circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a read amplifier or the like including a plurality of pairs of input transistors that receives a read signal of a magnetic head corresponding to the base and has its collector commonly coupled to a predetermined internal node and coupled to a non-inverting or inverting output terminal of a circuit. In, a first cascode transistor is provided between the collector of each pair of input transistors and the internal node, and a second cascode transistor is provided between the internal node and the non-inverting or inverting output terminal of the circuit.

[0010]

According to the above means, even when the substantial wiring length between the collector of the input transistor and the internal node becomes long and the wiring resistance becomes large, the first cascode transistor causes the Miller capacitance of the read amplifier, that is, the capacitance of the read amplifier. Can reduce the input capacity. As a result, the high frequency characteristics of the magnetic head drive integrated circuit including the read amplifier can be improved, and the data rate of the magnetic disk drive including the magnetic head drive integrated circuit can be increased.

[0011]

1 is a partial circuit diagram of an embodiment of a magnetic head drive integrated circuit MHD including a read amplifier RA to which the present invention is applied. Further, FIG. 2 shows a unit read amplifier UR included in the read amplifier RA of FIG.
An equivalent circuit diagram of one example of A1 is shown, and the noise spectrum of that example is shown in FIG. Based on these figures, the outline and characteristics of the configuration and operation of the read amplifier RA of this embodiment will be described. The magnetic head drive integrated circuit MHD further includes a write system circuit (not shown) that applies a predetermined write current to the magnetic head. The circuit element of FIG. 1 is formed on one semiconductor substrate such as single crystal silicon together with other circuit elements (not shown) of the magnetic head driving integrated circuit MHD. In the following circuit diagrams, the illustrated transistors (bipolar transistors are simply referred to as transistors in this specification) are not particularly limited, but all are NP.
It is an N-type bipolar transistor.

In FIG. 1, the read amplifier RA of the magnetic head drive integrated circuit MHD of this embodiment is a magnetic head M.
N unit read amplifiers URA1 to URAn provided corresponding to H1 to MHn are provided, and these unit read amplifiers have differential input transistors T1 and T1.
Includes 2 each. The bases of the input transistors T1 and T2 are coupled to the corresponding magnetic heads MH1 to MHn via complementary input terminals HX1 and HY1 to HXn and HYn, and their commonly coupled emitters are coupled to the corresponding constant current source S1. It is coupled to the low side power supply voltage VEE of the circuit. In this embodiment, the unit read amplifier UR
Input transistors T1 and T constituting A1 to URAn
The collector of the second cascode via the corresponding first cascode transistor T3 or T4 is either the internal node n1 or the internal node n2 and thus the second cascode transistor T5 and T5.
6 emitters are commonly coupled. Predetermined constant voltages Va and Vb are supplied to the bases of the cascode transistors T3 and T4 and T5 and T6. The collectors of the cascode transistors T5 and T6 are connected to the high-potential-side power supply voltage VC of the circuit via the corresponding load resistor R1 or R2.
In addition to being coupled to C, it is coupled as the inverting output terminal ROB or the non-inverting output terminal ROT of the read amplifier RA to the inverting or non-inverting input terminal of the main amplifier MA in the subsequent stage.

Here, the power supply voltage VCC on the high potential side of the circuit
Is a positive power supply voltage such as + 5V, and the low-potential-side power supply voltage VEE of the circuit is a negative power supply voltage such as -5.2V. Further, the unit read amplifiers URA1 to URAn
That is, the cascode transistors T3 and T4 have corresponding complementary input terminals HX1 and HY1 to HXn and H.
The cascode transistors T5 and T6 are arranged close to Yn, respectively, and the cascode transistors T5 and T6 are arranged close to the main amplifier MA. Further, the constant current source S1 provided corresponding to each differential transistor is selectively enabled according to a selection signal (not shown). As a result, the unit read amplifier U
RA1 to URAn are selectively activated according to the selection signal, and complementary input terminals HX1 and HY1 to HXn and HYn from corresponding magnetic heads MH1 to MHn.
The read signal input via the amplifier is amplified and selectively transmitted to the main amplifier MA.

By the way, the unit read amplifiers URA1 to URA
As illustrated in FIG. 2, input capacitors Ci are equivalently coupled to the input terminals of RAn, respectively. Each unit read amplifier has a predetermined resonance frequency fo determined by the input capacitance Ci and the inductance L _H of each magnetic head, as shown in the noise spectrum of FIG. However, in order to improve the high frequency characteristics of the magnetic head drive integrated circuit MHD and support high-speed reading, it is necessary to minimize the input capacitance Ci of each unit read amplifier and increase the resonance frequency fo.

As is well known, the unit read amplifier URA1
When the base-emitter capacitance and the base-collector capacitance of the input transistors T1 and T2 are C _TE and C _TC , respectively, the input capacitance Ci of URAn is Ci = [C _TE + C _TC {2 + gm ( _RA + rb / hfe)} + gm / 2πf _Ti ] / 2, and the C _TC · R _A term of this formula corresponds to the so-called mirror capacitance. The resistor R _A is connected to the transistor T1.
, And the collector saturation resistance of T2 is R _CS , the collector wiring resistance thereof is R _CW, and the emitter resistance of the corresponding cascode transistors T3 and T4 is R _EC , _RA = R _CS + R _CW + _REC ...・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (1) is required. gm is the transconductance, rb is the base resistance of the transistors T3 and T4, f _Ti is the intrinsic cutoff frequencies.

In the read amplifier RA of this embodiment,
As described above, the cascode transistors T3 and T4 are arranged close to the corresponding input transistors T1 and T2, and the wiring resistance R related to the internal nodes n1 and n2.
w is not included as the collector wiring resistance R _CW of the input transistors T1 and T2. However, the resistance R _{A in the} equation (1) becomes small, and the mirror capacitance of each unit read amplifier, that is, the input capacitance Ci is correspondingly reduced. As a result, the magnetic head drive integrated circuit M including the read amplifier RA
The high frequency characteristics of HD are improved, and the data rate of the magnetic disk device including the magnetic head drive integrated circuit MHD is increased.

By applying the present invention to an amplifier circuit such as a read amplifier included in a magnetic head drive integrated circuit as shown in the above embodiment, the following operational effects can be obtained. That is, (1) it includes a plurality of pairs of input transistors that receive a read signal of the magnetic head corresponding to the base and have their collectors commonly coupled to a predetermined internal node and coupled to a non-inverting or inverting output terminal of the circuit. In read amplifiers,
A first cascode transistor is provided between the collector of each pair of input transistors and the internal node,
By providing the second cascode transistor between the internal node and the non-inverting or inverting output terminal of the circuit, the substantial wiring length between the collector of the input transistor and the internal node is increased, and the wiring resistance is increased. Even when it becomes large, the mirror capacitance of the read amplifier, that is, the input capacitance can be reduced by the first cascode transistor. (2) According to the above item (1), the high frequency characteristics of the magnetic head drive integrated circuit including the read amplifier can be improved. (3) According to the above items (1) and (2), the data rate of the magnetic disk device including the magnetic head drive integrated circuit can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the read amplifier RA does not need to be a differential amplifier circuit, and the subsequent circuit need not be the main amplifier MA. The specific circuit configuration of the read amplifier RA is not restricted by this embodiment, and the polarity and absolute value of the power supply voltage, the conductivity type of the transistor, and the like can adopt various embodiments.

In the above description, the invention mainly made by the present inventor is applied to a magnetic head drive integrated circuit including a read amplifier which is the field of application which is the background of the invention, but the invention is not limited thereto. Without
For example, the present invention can be applied to various types of integrated circuit devices including a read amplifier that is formed as a single unit or a similar read amplifier. INDUSTRIAL APPLICABILITY The present invention can be widely applied to an amplifier circuit including a plurality of input transistors whose collectors are substantially commonly coupled, and a semiconductor device including such an amplifier circuit.

[0020]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a read amplifier or the like including a plurality of pairs of input transistors that receives a read signal of a magnetic head corresponding to the base and has its collector commonly coupled to a predetermined internal node and coupled to a non-inverting or inverting output terminal of a circuit. In, a first cascode transistor is provided between the collector of each pair of input transistors and the internal node, and a second cascode transistor is provided between the internal node and the non-inverting or inverting output terminal of the circuit. Thus, even when the substantial wiring length between the collector of the input transistor and the internal node becomes long and the wiring resistance becomes large, the mirror capacitance of the read amplifier, that is, the input capacitance can be reduced by the first cascode transistor. As a result, the high frequency characteristics of the magnetic head drive integrated circuit including the read amplifier can be improved, and the data rate of the magnetic disk drive including the magnetic head drive integrated circuit can be increased.

[Brief description of drawings]

FIG. 1 is a partial circuit diagram showing an embodiment of a magnetic head drive integrated circuit including a read amplifier to which the present invention is applied.

FIG. 2 is an equivalent circuit diagram showing an example of a unit read amplifier included in the read amplifier of FIG.

FIG. 3 is a noise spectrum showing an example of the unit read amplifier of FIG.

FIG. 4 is a partial circuit diagram of a magnetic head drive integrated circuit including a read amplifier developed by the inventors of the present application prior to the present invention.

[Explanation of symbols]

MHD ... Magnetic head drive integrated circuit, MH1 to MHn
... Magnetic head, RA ... Read amplifier, URA1
~ URAn ... Unit read amplifier. T1-T6 ...
NPN type bipolar transistor, R1 to R2 ... Resistor, S1 ... Constant current source. L _H ... inductance,
Ci ... Input capacity. Rw: wiring resistance.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masaki Yoshinaga 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (4)

[Claims] 1. A plurality of input transistors, whose collector receives an input signal corresponding to its base, and whose collector is commonly coupled to a predetermined internal node via a corresponding first cascode transistor; and the internal node and an output terminal of the circuit. And a second cascode transistor provided between the amplifier circuit and the second cascode transistor. 2. The amplifier according to claim 1, wherein the input signal is a differential signal, and the input transistor and the first and second cascode transistors are paired. circuit. 3. The first cascode transistor comprises:
The amplification according to claim 1 or 2, wherein the second cascode transistor is arranged in a position close to the corresponding input transistor, and the second cascode transistor is arranged in a position close to an output terminal of the circuit. circuit. 4. The amplifier circuit according to claim 1, wherein the amplifier circuit is a read amplifier included in a magnetic head drive integrated circuit of a magnetic disk device.