JP2779432B2 - Read / write integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read / write integrated circuit, and is effective when used in, for example, a read / write integrated circuit corresponding to a thin film head used in a small magnetic disk drive. It is about technology.

[Conventional technology]

As a read / write circuit for a thin film head, for example, there is a circuit as shown in FIG. On the other hand, the complementary write data Din is amplified by a differential amplifier circuit using differential transistors Q5 and Q6, level-shifted by emitter-follower transistors Q7 and Q8 and level shift diodes D1 and D2, and transferred to the magnetic head HD. The write current IW is transmitted to the bases of the differential transistors Q3 and Q4, and is switched. On the other hand, the write data Din is voltage-amplified by a differential amplifier circuit using differential transistors Q9, Q10, and forms a voltage applied to the magnetic head HD via the emitter follower transistors Q1, Q2. The emitter follower transistors Q1 and Q2 have a function of clamping the voltage across the magnetic head HD by the output voltage of the differential amplifier circuit. The voltage at both ends of the magnetic head is also coupled to the bases of the differential transistors Q11 and Q12 constituting the first-stage amplifier for reading.

Such a read / write circuit is disclosed, for example, in Japanese Patent Application Laid-Open No. 60-201505.

[Problems to be solved by the invention]

As the size of the magnetic storage device is reduced and the recording density is increased, the inductance of the magnetic head is increasing as a measure for reducing the read signal. Due to such an increase in the inductance of the magnetic head, a back electromotive force (flyback voltage) generated at the time of current switching as shown in the operation waveform diagram of FIG.
Inevitably increases. In a conventional circuit as shown in FIG. 6, a transistor Q for switching a write current is used.
3, the size of the collector of Q4 is made relatively large, and the collector parasitic capacitance is used to make the change of the switching current gradual so as to suppress the generation of the pulse-like flyback voltage. However, in this case, as viewed from the differential transistors Q11 and Q12 constituting the first-stage amplifier, the input parasitic capacitance is increased, so that the level margin is deteriorated. In other words, the conventional circuit has a problem in that when attempting to reduce the size, increase the recording density, and increase the speed, the level marsin and the withstand voltage marsin have an opposite relationship, and an effective solution that satisfies both cannot be found.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a read / write integrated circuit capable of obtaining necessary level margins and withstand voltage margins corresponding to miniaturization, high recording density, and the like.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
Using the time constant including a capacitor for the input write data, the switching is controlled based on the output signal of the first differential amplifier circuit whose change is moderated, and the write is supplied to the magnetic head. A pair of emitter follower transistors that receive an output signal of a second differential amplifier circuit that performs a current switching operation and receives the write data to increase the signal amplitude upon receiving the write data form a voltage applied to both ends of the magnetic head. An input terminal of a first-stage amplifier for reading is coupled to both ends of the magnetic head.

(Operation)

According to the above-described means, the change in the write current flowing through the magnetic head can be moderated, so that the generation of a pulse-like flyback voltage can be suppressed, and the size of the write current switching differential transistor can be minimized. As a result, the level margin of the first-stage amplifier for reading can be increased.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a read / write integrated circuit according to the present invention. Each circuit element except the magnetic head in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

This embodiment is directed to, but not limited to, a read / write integrated circuit corresponding to a thin film head used in a small magnetic disk drive.

The input data Din for writing is a complementary pair of signals, and one of them is supplied to the bases of the differential transistors Q5 and Q6 constituting the first differential amplifier circuit. The collectors of these differential transistors Q5 and Q6 are provided with load resistors R1 and R2, respectively. These load resistors R1, R2
Is supplied with a power supply voltage VCC via a resistor R0. The common emitter of the differential transistors Q5 and Q6 is provided with a constant current source I0.

In this embodiment, the current switching operation of the differential transistor that performs the switching operation of the write current IW based on the output signal of the first differential amplifier circuit is moderated.
In order to suppress the generation of the flyback voltage in the above, capacitors C1 and C2 are respectively provided between the collectors of the differential transistors Q5 and Q6 and the ground potential point of the circuit. These capacitors C1 and C2 moderate the change of the output signal due to the time constant of the load resistors R1 and R2 provided on the collector.

The voltage signals at the output nodes d and c of the first differential amplifier circuit are transmitted to the bases of the emitter follower type transistors Q7 and Q8. The constant current sources I1 and I2 are provided at the emitters of these transistors Q7 and Q8 via diodes D1 and D2 for level shift, respectively. This constant current source I1
And the constant current value of I2 are set to the same constant current value.

A pair of complementary output signals level-shifted through the emitter follower transistors Q7 and Q8 and the diodes D1 and D2 are differential transistors Q3 and Q4 that perform a switching operation of the write current IW via the base resistors R3 and R4.
Supplied to the base. A constant current source IW for writing is provided on a common emitter of the differential transistors Q3 and Q4. The write current IW switched by the differential transistors Q3, Q4 is caused to flow to the thin-film magnetic head HD connected to the terminals a, b. The terminals a and b are external terminals of the read / write integrated circuit according to this embodiment.

To apply a clamping voltage to both ends (a and b) of the magnetic head HD, a second differential amplifier circuit and an emitter follower circuit are provided as follows. That is, the input data Din is supplied to the bases of the differential transistors Q9 and Q10 constituting the second differential amplifier circuit on the other hand. The collectors of these differential transistors Q9 and Q10 and the power supply voltage VCC
Are provided with load resistors R5 and R6, respectively. The common emitter of the differential transistors Q9 and Q10 is provided with a constant current source I3. Thus, the second differential amplifier circuit generates an amplified output signal for the input data Din such that the power supply voltage VCC is at a high level and R5 × I3 or R6 × I3 is at a low level. This amplified output signal is transmitted to the terminals a and b to which the magnetic head HD is connected via the emitter follower output transistors Q1 and Q2.

The write current switching differential transistors Q3, Q
The relationship between the switch operation of No. 4 and the output level for voltage clamping is as follows. When the write current switching differential transistor Q3 is on and Q4 is off, the differential transistor Q10 constituting the second differential amplifier circuit is on and Q9 is off. Therefore, the output level corresponding to the transistor Q9 in the off state becomes high level,
The output level corresponding to the transistor Q10 in the on state becomes low level. Therefore, a high level is output through the emitter follower output transistor Q2 and a low level is output through the emitter follower output transistor Q1. Thereby, the terminal a to which the magnetic head HD is connected
And b are supplied with a voltage corresponding to the output amplitude of the second differential amplifier circuit, and the write current IW flows through the path of the differential transistor Q3-magnetic head-output transistor Q2. Conversely, when the write current switching differential transistor Q3 is off and Q4 is on, the differential transistor Q10 constituting the second differential amplifier circuit is off and Q9 is on. Therefore, the output level corresponding to the transistor Q10 in the off state becomes high level, and the output level corresponding to the transistor Q9 in the on state becomes low level. Therefore, a high level is output through the emitter follower output transistor Q1, and a low level is output through the emitter follower output transistor Q2. Thereby, the terminals a and b to which the magnetic head HD is connected
Is supplied with a voltage having a polarity opposite to that of the above case and corresponding to the output amplitude of the second differential amplifier circuit.
The write current IW flows through the path between the magnetic head and the output transistor Q1.

It should be noted that resistors RD1 and RD2 are provided between the terminals a and b and the power supply voltage VCC, the resistors RD1 and RD2 acting as a damping resistor during a write operation and as a bias resistor during a read operation.

The terminals a and b are coupled to the bases of the differential transistors Q11 and Q12 forming the first-stage amplifier for reading. The emitters of the differential transistors Q11 and Q12 have a transistor Q13 that is switch-controlled by the read mode signal RC.
A constant current source I4 for generating an operating current via the power supply is provided.
Load resistors R7, R8 are provided at the collectors of the differential transistors Q11, Q12.

In this embodiment, the size of the current switching differential transistors Q3 and Q4 is formed small only by allowing the current IW to flow, so that the input parasitic capacitance of the first-stage amplifier is reduced. That is, the size of the differential transistors Q3 and Q4 is not increased as in the related art, and the collector parasitic capacitance is not increased.

FIG. 2 is a waveform chart for explaining an example of the operation of the embodiment circuit shown in FIG.

The first differential amplifier circuit that receives the input data Din forms output voltages Vd and Vc whose changes are moderated by a time constant circuit including the load resistors R1 and R2 and the capacitors C1 and C2. The output voltages Vd and Vc are level-shifted by the level shift circuit as described above, and the differential transistors Q3 and Q4
Supplied to the base. The current switching control voltages Vd 'and Vc' transmitted to the base also have their level changes moderated as described above. With this, the magnetic head HD
Current i _H than switched slowly as -IW from example + IW, can be negligibly small even pulsed flyback voltage of the magnetic head HD.

On the other hand, the input data Din is made to have a large amplitude like the voltage VB by the second differential amplifier circuit. This voltage VB is
Emitter-follower output transistors that change at high speed in response to changes in input data Din and generate clamp voltages Va and Vb
It is supplied to both ends a and b of the magnetic head HD via Q1 and Q2.

To speed up the write current switching time t1,
This is achieved by increasing the voltage VB, but must be increased on average. That is, as shown in FIG. 7, when the flyback voltage in the form of a pulse is temporarily large, the current switching time t1 is short and the contribution to the speeding up of the total current switching time is small, but the first stage amplifier for reading is constituted. This causes a problem that the transistor breakdown voltage (between base and emitter) of the differential transistors Q11 and Q12 is exceeded.

Therefore, in a read / write circuit that requires a high speed, it is necessary to minimize the pulse flyback voltage, increase the clamp voltage VB on average, and shorten the current switching time t1.

As means for reducing the pulse-like flyback voltage, the current switching differential transistors Q3 and Q4 have a base resistor R
3, It is also conceivable to insert R4 to increase the resistance value. However, when the resistance value is increased, the write current
IW requires several tens of mA. For this reason, the base currents of the transistors Q3 and Q4 cannot be ignored, and the input amplitude margin of the transistors Q3 and Q4 is reduced due to the base current drop.

Also, in consideration of a future increase in the capacity (higher recording density) and a higher speed of the magnetic disk memory device, the inductance of the magnetic head increases, and the input parasitic capacitance of the read system amplifier needs to be further reduced. For this reason, the transistors Q3 and Q4 that pass the write current of the write circuit become parasitic capacitances for the differential transistors Q11 and Q12, which are the first-stage amplifiers of the read system, and in order to reduce the input capacitance and secure the read margin, It is necessary to reduce the size of the transistors Q3 and Q4 as much as possible. At that time, it is necessary to increase the resistance values of the base resistors R3 and R4 in order to maintain the same current change rate. On the other hand, the increase in the inductance L _H of the magnetic head HD can be calculated from the following equation (1): V = L _H (di _H / dt) (1) At the same current change rate (di _H / dt) If inductance
In proportion to the increase of L _H, pulsed flyback voltage V increases. For this reason, it is necessary to suppress the pulse-like flyback voltage V by reducing the current change rate. However, in the method using the base resistors R3 and R4 as described above, the current switching differential transistor Q3 , Q4 loses its input amplitude margin.

In this embodiment, instead of the differential circuit for switching the write current as described above, a control for reducing the current change rate is performed in the first differential amplifier circuit as a drive circuit for forming the control voltage. It forms a voltage. This makes it possible to suppress the generation of a pulse-like flyback voltage without deteriorating the input amplitude margin of the current switching differential transistor. Since the generation of the pulse-like flyback voltage is suppressed in this manner, a withstand voltage margin of the first-stage amplifier of the reading system can be secured. In addition, current switching transistors Q3 and Q4
Can be formed to the required minimum, so that the input capacitance of the first-stage amplifier can be reduced and a read margin can be secured.

FIG. 3 is a circuit diagram showing another embodiment of the read / write integrated circuit according to the present invention. In this embodiment, a capacitor C is provided between the collectors of the differential transistors Q5 and Q6 constituting the first differential amplifier circuit. The capacitor C having this configuration has no polarity like a PN junction capacitive element, for example, the first layer, the wiring layer, and the second layer.
A capacitive element is used in which a first wiring layer is used as an electrode and an insulating film therebetween is used as a dielectric. In this embodiment, when obtaining the same time constant as the embodiment of FIG.
If the resistance values of R1 and R2 are the same, the capacitance value can be halved. The configuration and operation of the other circuits in FIG. 7 are the same as those in FIG. 1, and a description thereof will be omitted.

FIG. 4 is a circuit diagram of another embodiment of the first differential amplifier circuit used in the read / write integrated circuit according to the present invention.

In this embodiment, the capacitors C1 and C2 that moderate the output voltage change are provided between the collectors and the emitters of the differential transistors Q5 and Q5. In this configuration, it is possible to use a capacitor element that can reduce the voltage applied between the electrodes of the capacitors C1 and C2 and has a low withstand voltage but a large capacitance value, such as a junction capacitance between the base and the emitter of the transistor. This enables high integration of the semiconductor integrated circuit. The emitter-side electrodes of the capacitors C1 and C2 may be connected to an appropriate bias voltage terminal. By setting the bias voltage to a voltage that reduces the voltage applied to the capacitors C1 and C2, the same capacitive element as described above can be used.

The bias voltage may be switched according to the specifications of the magnetic head by utilizing the voltage dependence of the capacitors C1 and C2. That is, when used as a read / write correction circuit for a magnetic head having a large inductance, the bias voltage is changed to
The capacitance values of C1 and C2 are set relatively large, and the write current change rate is made smaller. Conversely, when used as a read / write correction circuit for a magnetic head with a small inductance, the bias voltage is changed, the capacitance values of the capacitors C1 and C2 are set to a relatively small value, and the write current change rate is increased. You may make it.

FIG. 5 is a circuit diagram showing still another embodiment of the first differential amplifier circuit used in the read / write integrated circuit according to the present invention.

In this embodiment, two differential amplifier circuits connected in cascade are used as the first differential amplifier circuits. That is, the first-stage differential amplifier circuit has the same configuration as the conventional one, and the differential transistor Q1 'forming the output-side differential amplifier circuit
Capacitors C1 and C2 are provided between the base and collector of Q2 '.

In this configuration, the capacitors C1 and C2 act as Miller capacitances, and can equivalently increase the capacitance value corresponding to the amplification factor of the amplifier. Thus, a large time constant can be obtained while using a small capacitance value. The output side differential amplifier circuit is equivalent to the capacitor C1 depending on the amplification factor.
Therefore, the signal transmitted to the bases of the emitter follower output transistors Q7 and Q8 may be the collector output of the first-stage differential transistors Q5 and Q6. In this case, the resistor R0 'for adjusting the DC level provided in the differential amplifier circuit on the output side may be omitted.

The operational effects obtained from the above embodiment are as follows. That is, (1) the switching of the differential transistor is controlled based on the output signal of the first differential amplifier circuit whose change is moderated by using a time constant circuit including a capacitor for the input data, and the magnetic head is controlled by the switching. A switching operation of a write current to flow is performed, and a pair of emitter follower transistors receiving an output signal of a second differential amplifier circuit receiving the input data and increasing a signal amplitude forms a voltage applied to both ends of the magnetic head. At the same time, input terminals of a first-stage amplifier for reading are coupled to both ends of the magnetic head. With this configuration, it is possible to moderate the change in the write current flowing through the magnetic head without increasing the size of the write differential transistor or the resistance value of the input base resistor. As a result, the generation of a pulsed flyback voltage in the magnetic head can be suppressed, so that the size of the write current switching differential transistor can be set to the minimum necessary, and the breakdown voltage margin and level margin of the first-stage amplifier can be secured. The effect is obtained.

(2) Since the generation of the pulse-like flyback voltage can be suppressed by the above (1), the amplitude of the output signal formed by the second differential amplifier circuit is limited as long as the withstand voltage of the differential transistor or the like permits. Since a large value can be obtained (a large flyback voltage is obtained on average), the effect that the write current switching time can be shortened can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the gist of the invention. Nor. For example, input data Di
The first differential amplifier circuit which receives n and forms a control signal to be supplied to the base of the current switching differential transistor is provided by a time constant circuit using a capacitor and a resistance means in the same manner as in the previous embodiment. Anything can be used as long as the change is moderated. Further, the differential transistor circuit constituting the first-stage amplifier may be of any type as long as it performs the amplification operation by receiving the voltage signal at both ends of the magnetic head as described above.

The storage medium in which the read / write circuit according to the present invention is used may be any storage medium that performs read / write using a magnetic head such as a floppy disk and a magnetic tape in addition to a hard disk.

INDUSTRIAL APPLICABILITY The present invention can be widely applied to various magnetic storage devices as a read / write integrated circuit.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, based on the output signal of the first differential amplifying circuit whose change is moderated by using a time constant circuit including a capacitor for input data, switching control of the differential transistor is performed and a write current flowing to the magnetic head. And a pair of emitter follower transistors receiving an output signal of a second differential amplifier circuit for receiving the input data and increasing the signal amplitude to form a voltage applied to both ends of the magnetic head. The input terminals of the first-stage amplifier for reading are coupled to both ends of the magnetic head. With this configuration, it is possible to moderate the change in the write current flowing through the magnetic head without increasing the size of the write differential transistor or the resistance value of the input base resistor. As a result, the generation of a pulsed flyback voltage in the magnetic head can be suppressed, so that the size of the write current switching differential transistor can be set to the minimum necessary, and the breakdown voltage margin and level margin of the first-stage amplifier can be secured. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a read / write integrated circuit according to the present invention, FIG. 2 is an operation waveform diagram for explaining an example of its operation, and FIG. FIG. 4 is a circuit diagram showing an embodiment of a first differential amplifier circuit used in the read / write integrated circuit. FIG. 4 is a first differential amplifier used in the read / write integrated circuit according to the present invention. FIG. 5 is a circuit diagram showing another embodiment of the circuit. FIG. 5 is a circuit diagram showing still another embodiment of the first differential amplifier circuit used in the read / write integrated circuit according to the present invention. FIG. 6 is a circuit diagram for explaining an example of the prior art, and FIG. 7 is an operation waveform diagram for explaining the problem. I0 to I4: Constant current source, IW: Write constant current source, Q1 to Q1
3 ... Transistor, R1-R8, RD1, RD2 ... Resistance, C, C1, C2
…… Capacitor, HD …… Magnetic head.

Claims (1)

(57) [Claims] A first differential amplifier circuit including a differential pair transistor for receiving a write data as a base and forming a complementary output signal from a collector; and receiving the complementary output signal of the first differential amplifier circuit. hand,
A level shift circuit that forms a level-shifted complementary signal, and a switching operation of a write current that is supplied to the magnetic head of the magnetic disk drive connected to the collector, based on the level-shifted complementary signal of the level shift circuit. A second differential amplifier circuit that receives the write data as a base and forms a clamp voltage applied from a collector to both ends of the magnetic head; and a second differential amplifier circuit A pair of emitter follower output transistors whose emitters are connected to the both ends of the magnetic head, and a read differential transistor whose bases are connected to the both ends of the magnetic head. Read / write integrated circuit for magnetic disk drive including first stage amplifier A capacitor connected to a collector of each transistor of the differential pair transistor of the first differential amplifier circuit,
A read characterized in that the change in the complementary output signal is moderated by a time constant with a collector load resistance, so that the rate of change in the write current of the magnetic head is reduced and the pulse voltage of the magnetic head is reduced. / Integrated circuit for writing.