JPH0515139B2 - - Google Patents

Description

[Detailed description of the invention]

(a) Field of industrial application The present invention relates to a power supply device that operates a pulse width modulation inverter system using a solar cell as a power source and a commercial power system in parallel to supply power to a load. This relates to phase locked circuits. (b) Prior art In general, in-house power generation equipment using solar cells applied to private residences, etc., in order to effectively utilize solar energy, a storage battery is installed to store power, and the power generated by the solar cells is used. The power generation equipment is linked to the commercial power system, and the power generated by the solar cells is regenerated to the commercial power system to effectively utilize the power generated. However, when using the former type of storage battery, it becomes expensive due to the need for the storage battery, and it takes time and effort to maintain the storage battery.Moreover, there is an inconvenience that power loss occurs when charging the former type of storage battery, and the latter type of storage battery is expensive. Even when linking to a commercial power system, there are many technical problems and legal problems when obtaining approval for implementation, all of which lack practicality. Therefore, an inverter system consisting of the power generation equipment and an inverter that converts the DC power generated by the power generation equipment into AC power, and the commercial power system are connected in parallel to the load to configure a power supply device with so-called parallel operation, Both systems are operated to supply power to the load so that the power supplied by the inverter system does not exceed the total power demand of the load, and so-called cross flow in which the power of the inverter system is regenerated to the commercial power system does not occur. things are being done. The block circuit diagram shown in FIG. 1 is an improvement on the invention previously proposed by the present inventors in Japanese Patent Application No. 70,640/1982. 1 is a solar cell; 2 is a pulse width modulation inverter whose input terminal is connected to the solar cell 1 and constitutes a pulse width modulation inverter system 3 together with the solar cell 1; and 4 is connected in parallel to a load 5 together with the inverter system 3. 6 is a switch, 7 is a step-up transformer provided between the solar cell 1 and the inverter 2, 8 is a static switch provided between the transformer 7 and the load 5, 9 , 10 have input terminals connected to the output line and load line of the inverter 2, and detect the output voltage e _I of the inverter system 3 and the system voltage e _C of the commercial power system 4, respectively, and output detection signals. 2 voltage detection parts, 11, 12
are two current transformers provided in the output line and the load line, respectively, to take out the output current i _I and the load current i _L of the inverter system 3, and 13 and 14 have input terminals connected to both current transformers 11 and 12, respectively. Both current transformers 1
a _{first ;}
The second current detection units 9', 13', 10', and 14' are zero-crossing inspections that detect the zero-crossing points of the analog outputs of the detectors 9, 13, 10, and 14, and output digital signals indicating the zero-crossing points. Output circuit 15 is a third voltage detection section 16 whose input terminal is connected to the solar cell 1 and detects the output voltage of the solar cell 1 and outputs a detection signal.
17 is an AD converter that converts each detection signal consisting of an analog signal from each detection unit 9, 10, 13, 14, 15 into a detection signal consisting of a digital signal and outputs the same; A bidirectional switch unit 18 is a phase comparator which switches and outputs the input detection signals, and both voltage detection units 9 and 1 which are input via the switch unit 17
0, the phase of the output voltage of the inverter system 3 and the phase of the system voltage are compared, and a voltage phase comparison signal is output to the inverter 2 to control the pulse width of the control pulse to the inverter 2. . 19 is a synchronization detection unit that outputs a synchronization signal when the phases of the output voltage and the grid voltage are synchronized and when the phases of the output current and the load current are synchronized; A central processing unit (hereinafter referred to as a controller) that receives each digital signal and the synchronization signal and outputs each control signal.
21 is a switch drive unit that outputs control pulses to the inverter 2 and turns on and off the switch 6 according to a pulse width control signal from the CPU 20; 23 is a static switch drive unit;
The static switch 8 is turned on and off by an on/off control signal from the CPU 20. Note that 24 is an AC filter, and 25 is a link reactor. The third voltage detection unit 15 detects the output voltage of the solar cell 1 and outputs a detection signal, the detection signal is input to the CPU 20 via the AD converter 16, and the CPU 20 converts the output voltage to the inverter
It is determined whether or not a predetermined value sufficient to activate the
20 outputs an on control signal to the switch drive unit 22 to turn on the switch 6, the output voltage of the solar cell 1 is applied to the inverter 2, the inverter system 3 starts operating, and the first and second The output voltage of the inverter system 3 and the system voltage of the commercial power system 4 on both sides of the static switch 8 in the OFF state are detected by the voltage detection units 9 and 1, and both detection signals are outputted, respectively. but
is input to the CPU 20 via the AD converter 16,
The CPU 20 outputs a pulse width control signal to the pulse output unit 21 until the absolute values of the output voltage and the grid voltage match, and the pulse width of the control pulse output from the pulse output unit 21 to the inverter 2 is controlled. , the output voltage of the inverter 2 is controlled so that the absolute values of the output voltage and the grid voltage become equal, and at the same time, the detection signals from the first and second voltage detection sections 9 and 10 are sent to the phase comparator 18 via the switch section 17. A voltage phase comparison signal is output from the phase comparator 18 to the inverter 2 so that the phase of the output voltage of the inverter system 3 is synchronized with the phase of the system voltage of the commercial power system 4, and the pulse output section 21 outputs the voltage phase comparison signal to the inverter 2. The pulse width of the control pulse is controlled, the phase of the output voltage of the inverter 2 is controlled, and the phase of the output voltage is synchronized with the phase of the system voltage. Next, when the synchronization detection section 19 detects that the output voltage of the inverter system 3 and the grid voltage of the commercial power system 4 are synchronized in phase, the synchronization detection section 19
A synchronization signal is output from the inverter system 20 to the CPU 20, and in response to the synchronization signal, the CPU 20 outputs an on control signal to the static switch drive section 23, turning on the static switch 8 and receiving power from the inverter system 3 in addition to the power from the commercial power system 4. is supplied to the load 5, and the power supplied by the inverter system 3 is controlled so as not to exceed the total power demand of the load 5. Both current transformers 11 and 12 and both current detection sections 1
3 and 14 detect the output current of the inverter system 3 and the load current flowing through the load 5, and output detection signals, respectively.
The pulse width of the control pulse from the pulse output section 21 to the inverter 2 is limited, and the output voltage phase of the inverter 2 is limited so that the phase of the output current is equal to that of the load current. Inverter system 3 for load 5 in phase synchronization
And appropriate power sharing of the commercial power system 4 is performed. By the way, the phase comparator 18 is conventionally composed of an analog phase comparator 26, as shown in FIG.
It consisted of a low pass filter 27, a voltage controlled oscillator 28, an inverter control circuit 29, and a 90° phase circuit 30 connected between the bidirectional switch section 17 and the phase comparator 26. The inverter output voltage e _I , the inverter output current i _I , the commercial power system voltage e _C , and the load current i _L can be input to the bidirectional switch 17 at any time. The inverter output voltage e _I passes through the 90° phase circuit 30,
Furthermore, the system voltage e _C directly becomes an input signal to the phase comparator 26 . The phase comparator 26 outputs an error voltage proportional to the phase difference and frequency difference between these two input signals. Now, if the phase difference between the two input signals is 90°, the average difference signal of the output will be 0, and with this as a reference, the error voltage according to the phase difference will be calculated as the phase lead or lag. Generated from the comparator 26. This voltage becomes the control voltage of the voltage controlled oscillator 28 after removing high frequency components through the low-pass filter 27 . The oscillator 28 outputs a frequency proportional to the control voltage. This output signal operates by controlling the inverter 2 via the inverter control circuit 29 so that the system voltage e _C and the inverter output voltage are in phase synchronization. Hereinafter, the oscillation frequency of the oscillator 28 in the phase synchronization state will be referred to as a free-running frequency. The so-called phase lock loop circuit (hereinafter referred to as PLL circuit) as described above is used to control the inverter of a grid parallel system, but it is important to note that the PLL circuit plays an important role in controlling such a system. Needless to say, in the PLL circuit, in the synchronous state, the frequency of the oscillator 28 matches the input signal, but their phase is changed by an error voltage (phase control error). Furthermore, due to the influence of power supply voltage fluctuations of the control circuit that constitutes the PLL circuit, temperature drift of the oscillator 28, changes over time, etc., the oscillator 28 is no longer able to maintain its free-running frequency in the synchronized state, and as a result, the phase difference increases. arise. Therefore, in controlling the inverters for system parallel operation, although the circuit configuration is simple, there is a problem in accuracy and it is not possible to perform sufficient phase control. (C) Purpose of the Invention The present invention has been made in view of the problems of the prior art as described above, and is intended to improve the relationship between the commercial power system voltage and the inverter output voltage, or the load When performing phase control of the current and inverter output current, even if the PLL circuit generates a phase control error, it is monitored and the phase difference between the commercial power system voltage and the inverter output voltage, or the load current and the inverter output current is corrected. It is an object of the present invention to provide a phase control circuit using a microcomputer that can perform phase control so as to eliminate the problem. (d) Structure of the invention A pulse width modulation inverter system using a solar cell as a power source and a commercial power system are connected in parallel, and both systems are operated so that the power supplied by the inverter system does not exceed the total power demand of the load. A phase synchronized circuit of a power supply device that supplies power to the load by detecting a phase difference between a detection signal due to the commercial power system voltage and an inverter system output voltage, or a phase difference of a detection signal due to the current flowing through the load and the inverter system output current. a phase detection circuit that detects a phase difference, a control section, a phase control circuit that converts the phase of a detection signal based on the inverter system output voltage or inverter system output current based on a command from the control section, and the commercial power system voltage. Alternatively, a phase comparator outputs an error voltage proportional to a detection signal based on a current flowing through the load and a phase difference and a frequency difference between the output signal of the phase control circuit, and a phase comparator outputting an error voltage proportional to a control voltage based on the error voltage. a voltage controlled oscillator that outputs, the control unit:
The phase is controlled so that the phase of the output signal with respect to the input signal of the phase control circuit is 90° in the initial state, and the commercial power system voltage and the inverter system output voltage, or the current flowing through the load and the inverter system output current. is to control the phase of the output signal of the phase control circuit based on the detection output of the phase detection circuit in a phase synchronized state, and the detection signal based on the commercial power system voltage and the inverter system output voltage, or the load The phase state of the detection signal based on the flowing current and the inverter system output current is monitored, and the phase of the detection signal based on the inverter system output voltage or the inverter system output current is advanced or delayed by the control section. (E) Embodiment FIG. 3 shows a connection circuit diagram of the phase comparator of the present invention and its peripheral parts. In this figure, 31 is a phase control circuit, and 32 is a phase detection circuit. The phase detection circuit 32 is composed of, for example, a D flip-flop, and based on the input signal φ ₁ based on the output voltage e _I or output current i _I from the inverter 2, the system voltage e _C from the commercial power system 4 or flowing through the load 5 It is determined whether the phase of the input signal φ ₂ due to the current i _L is advanced or delayed, and a digital signal corresponding to the phase is sent to the CPU 20 . As shown in FIG. 4, the phase control circuit 31 is composed of one-shot circuits 33, 34, an OR circuit 35, a presettable counter 36, and a D flip-flop 37. The one shot circuit 33, 34
The input signal _eI or _iI is the aforementioned _φ1 , the output signal from the OR circuit 35 is _φ3 , the output signal from the presettable counter 36 is _φ4 , and the output signal from the D flip-flop 37 is _φ5. shall be. The presettable counter 36 is used in the down mode here, and the control signal of the CPU 20 becomes the data input (preset value) of the counter 36. Further, the output signal φ ₃ becomes a load signal for the counter 36, and the counter 36 sets the count to a preset state every time it receives the output signal φ ₃ . The counter 36 receives a count pulse (CK).
is applied, and after the count ends, the output signal φ ₄
is output to the D flip-flop 37. D flip-flop 37 functions according to Table 1 and provides an output signal _φ5 .

[Table] FIG. 5 is a timing diagram of the output signals φ ₁ , φ ₃ , φ ₄ , and φ ₅ . Here, the phase difference θ ₁ between the output signal φ ₁ and the output signal φ ₅ is controlled by the control signal of the CPU 20 (preset value of the presettable counter 36). FIG. 6 is a diagram showing the correlation between the synchronous frequency of the PLL circuit and the phase difference θ ₂ between the two input signals φ ₂ and φ ₅ of the analog phase comparator (hereinafter abbreviated as APC) 26. In Figure 6
Assume that the PLL circuit is in a synchronous state, and the APC26
Gradually increase the input signal frequency of the voltage controlled oscillator (
The frequency at which the synchronization of the PLL circuit is released when moving away from the free-running frequency ₀ of 28 (abbreviated as VCO) is ₁ , _4.
and define B _L = ₄ − ₁ . Furthermore, it is assumed that the PLL circuit is in an asynchronous state, and when the input signal frequency of the APC26 is gradually moved away from the free-running frequency ₀ ,
When the frequency at which the synchronization of the PLL circuit is released approaches ₀ , the frequency at which the PLL circuit synchronizes is set to ₂ and ₃ , and B _P =
Define _{as 3-2} . Such B _L and B _P are called lock range and capture arrangement, respectively. Now, if the PLL circuit operates in the ideal state (point A in Fig. 6), the output signals φ ₁ and φ ₂ are safely synchronized, and the frequency difference and level between the output signal φ ₁ and the output signal φ ₂ are No phase difference occurs at all. However, in reality, the PLL circuit does not operate at the above point A due to the influence of phase control errors of the PLL circuit itself, fluctuations in the power supply (solar cell 1) voltage, drift of the free-running frequency of the VCO 28, and changes over time. , the phase difference θ ₂ (see FIG. 7) between the output signal φ ₁ and the output signal φ ₂ continues to remain in the locked state. Therefore, if the phases of the output signals φ _{1 and} φ ₂ are constantly monitored and the phase difference θ ₂ is controlled to be small using a microcomputer, the output signal φ ₁ and the output signal φ 2 can be The phase with φ ₂ will always match. Next, the above control method will be explained in detail. In the initial state, the CPU 20 provides data such that the phase difference θ ₁ between the output signal φ ₁ and the output signal φ ₅ is 90° as data in the presettable counter 36 of the phase control circuit 31 . As soon as the PLL circuit enters the synchronized state, the phase detection circuit 32
determines whether the phase of the output signal φ ₂ is advanced or delayed based on the output signal φ ₁ and sends a corresponding digital signal to the CPU 20 . For example, if the phase of the output signal φ ₁ lags the phase of the output signal φ ₂ by θ ₂ as described above, the CPU 20 continuously presets data that advances the output signal φ ₁ by 90° − θ ₂ . By giving it as data to the double counter 36, the APC26
The phase difference between the two input signals φ ₂ and φ ₅ is always controlled to be close to 90°. In this way, the phase of the output signal φ ₁ and the output signal φ ₂ is constantly monitored, and the microcomputer controls the phase control circuit 31 so that the phase difference between the output signal φ ₂ and the output signal φ ₅ is 90°. The phase difference between the output signal φ ₁ and the output signal φ ₂ can be eliminated. FIG. 8 is a characteristic diagram of the PLL circuit. The vertical axis is the phase difference between the output signal φ ₂ and the output signal φ ₅ ,
The horizontal axis shows the oscillation frequency of the VCO 28.
When the PLL circuit is operating in a steady state (voltage 5V), point D is the operating point of the PLL circuit, and at this time there is no phase difference. Here, the free running frequency of VCO28 is set to 60Hz. For example, if the oscillation frequency of VCO28 changes to 56Hz or 62Hz, the PLL
The operating point of the circuit moves to point E or point F. That is, since the phase difference between the output signal φ ₂ and the output signal φ ₅ is not 90°, a phase difference occurs between the output signal φ ₁ and the output signal φ ₂ . In the present invention, the phase difference between the output signal φ ₂ and the output signal φ ₅ is set to 90° to eliminate the phase difference between the output signal φ ₁ and the output signal φ ₂ . (F) Effects of the Invention As described above, the present invention provides a detection signal based on the voltage or the current when the commercial power system voltage and the inverter system output voltage, or the current flowing through the load and the inverter system output current are in a phase synchronized state. monitor the phase state of the detection signal by
By advancing or delaying the phase of the detection signal based on the inverter system output voltage or inverter system output current using the control unit, the phase of the commercial power system voltage and the inverter system output voltage, or the current flowing through the load and the inverter system output current can be adjusted. can always be matched. Therefore, it becomes possible to effectively utilize the power generated by sunlight.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a power supply device employing the phase-locked circuit of the present invention, FIG. 2 is a block circuit diagram of a conventional phase-locked circuit, FIG. 3 is a block circuit diagram of a phase-locked circuit of the present invention, and FIG. The figure is also a block circuit diagram of the phase control circuit, FIG. 5 is a timing waveform diagram explaining the operation of the phase control circuit of FIG. 4, and FIG.
The figure shows the synchronous frequency of the PLL circuit of the present invention and the APC 2
Figure 7 is an explanatory diagram of the phase control method of the present invention, and Figure 8 is a diagram showing the phase difference between two input signals.
It is a phase characteristic diagram of a circuit. 1...Solar cell, 3...Inverter system, 4...
...Commercial power system, 5...Load, (e _C )...Commercial power system voltage, (e _I )...Inverter output voltage, (i _L )
...load current, (i _I ) ...inverter output current,
26... Phase comparator, 28... Voltage controlled oscillator, 31... Phase circuit, 32... Phase discriminator.

Claims (1)

[Claims] 1. A pulse width modulation inverter system using a solar cell as a power source and a commercial power system are connected in parallel, and both systems are connected in parallel so that the power supplied by the inverter system does not exceed the total power demand of the load. A phase synchronized circuit of a power supply device that operates and supplies power to the load, which detects a phase difference between a detection signal based on the commercial power system voltage and an inverter system output voltage, or a detection signal based on a current flowing through the load and an inverter system output current. a phase detection circuit that detects a phase difference; a control section; a phase control circuit that converts the phase of a detection signal based on the inverter system output voltage or inverter system output current based on a command from the control section; and the commercial power system. a phase comparator that outputs a detection signal based on a voltage or a current flowing through the load, and an error voltage proportional to the phase difference and frequency difference between the output signals of the phase control circuit; and a phase comparator that outputs an error voltage proportional to a control voltage based on the error voltage. a voltage controlled oscillator that outputs a voltage controlled oscillator, the control unit controls the phase so that the phase of the output signal with respect to the input signal of the phase control circuit is 90° in an initial state, and When the inverter system output voltage or the current flowing through the load and the inverter system output current are in a phase synchronized state, the phase of the output signal of the phase control circuit is controlled based on the detection output of the phase detection circuit. synchronous circuit.