JPH05151248A - Condition vectorizing/paralleling processor - Google Patents

Abstract

PURPOSE:To make it possible to efficiently execute tuning, to shorter a program execution time and to improve execution performance. CONSTITUTION:A compiler 10 stores a vectorizing/paralleling condition of an optimum execution format in a translated result storing file 20 by a vectorizing/ paralleling condition output means 11. A program forming means 30 forms a source program 3 into which a sentence for sampling the execution information of a vectorized/paralleled part is inserted based upon the vectorizing/ paralleling condition 2 stored in the file 20 and an execution information sampling and outputting means 40 samples execution information executed based upon the program 3, edits the sampled information and outputs the edited result as an execution result 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a condition vectorization parallelization processor of an electronic computer system.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a source program of a condition vectorization parallelization processing device. FIG. 7 is a diagram showing the determination result of the condition vectorization parallelization of the compiler of the condition vectorization parallelization processing device. FIG. 8 is a conceptual diagram of a target program of a compiler of a conventional condition vectorization parallelization processing device.

Generally, in a program such as scientific and engineering calculation, most of the execution time is concentrated in a part of the DO loop, so that processing the DO loop at high speed leads to improvement of the execution performance of the entire program. Therefore, in an electronic computer system having a vector processor or a multiprocessor, vectorization or parallelization of the DO loop is performed in the compiler so that the DO loop can be processed at high speed by effectively utilizing the functions of these processors. I'm trying to do it. Here, in recent advanced compilers, instead of fixedly executing the vectorized or parallelized instruction sequence, the instruction sequence to be executed is switched according to the number of loops at the time of execution. There are some that are designed to be optimized. Here, such an optimization process will be referred to as a condition vectorization parallelization process.

Conventionally, the condition vectorization parallelization processing device is
The input source program is translated, the DO loop in this source program is analyzed at the time of creating the target program, the optimal execution form by vectorization parallelization is determined according to the number of loops at execution, and the optimum execution form is dealt with. It is composed of a compiler that generates an instruction string on this object program and branches to the instruction string according to the value of the loop count, and a translation result storage file that stores the output object program of this compiler.

The processing of the conventional condition vectorization parallelization processing apparatus will be described. FIG. 6 shows an example of a source program including a DO loop. Here, since the loop count N of the DO loop “10” (* 61) is a dummy argument, the loop count N changes depending on the value given at the time of execution. When N is small, the execution time may be shorter when the scalar processing is performed as it is than when the vector processing is performed by the vectorized instruction sequence. Conventionally, in a compiler capable of performing conditional vectorization parallelization processing, when a program as shown in FIG. 6 is input, the DO loop “10” (* 61) is analyzed, and which one is executed depending on the value of the loop count N As shown in FIG. 7, it is determined whether the form is optimum, an instruction sequence corresponding to each execution form is generated on the target program, and a target program that branches to each instruction sequence according to the value of the loop count N is generated. Was there. FIG. 8 is a conceptual diagram when the instruction sequence created in the target program is expressed by the source program. '
* PDIR PARALLEL, VECTOR 'is called an instruction line and indicates that the DO loop immediately after that is parallelized and vectorized.

[0006]

However, in such a conventional compiler, the condition vectorization parallelization processing is automatically performed and its effect is great, but the optimization processing in the compiler is not complete. It can not be said that it is necessary to modify (tune) the program by the user in order to improve the execution performance by further speeding up,
There is a problem that useful information for tuning cannot be obtained because only the message that the predetermined DO loop is subjected to the condition vectorization parallel processing is output as a message.

The present invention solves the above problems.
An object of the present invention is to provide a condition vectorization parallelization processing device capable of improving the efficiency of tuning, shortening the execution time of a program, and improving the execution performance.

[0008]

According to the present invention, a source program to be input is translated, a DO loop in the source program is analyzed at the time of creating a target program, and optimal optimization is performed by vectorization parallelization according to the number of loops at the time of execution. A compiler that determines the execution form, generates an instruction sequence corresponding to this optimum execution form on the target program, and generates a target program that branches to the instruction sequence according to the value of the loop count,
In a conditional vectorization parallelization processing device including a translation result storage file storing an output target program of this compiler, the compiler stores a vectorization parallelization condition of the optimum execution mode in the translation result storage file. And parallelization condition output means.

According to the present invention, a statement for inputting the source program and collecting execution information of the vectorized parallelized portion of the source program based on the vectorized parallelization condition stored in the translation result storage file is provided. A program generation means for generating the inserted source program and an execution information collection / output means for executing based on the source program output by the program generation means to collect and edit execution information and output an execution result can be provided. ..

[0010]

The compiler causes the vectorization parallelization condition output means to store the vectorization parallelization condition of the optimum execution form in the translation result storage file. Further, the user generates a source program into which a sentence for collecting execution information of the vectorized and parallelized portion is inserted based on the vectorized and parallelized condition stored in the translation result storage file by the program generation means,
The execution information collecting means can execute the execution information based on this source program, collect and edit the execution information, and output the execution result.

As described above, the efficiency of tuning can be improved, the execution time of the program can be shortened, and the execution performance can be improved.

[0012]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a condition vectorization parallelization processing apparatus according to an embodiment of the present invention.

In FIG. 1, a conditional vectorization parallelization processor translates an input source program 1, analyzes a DO loop in the source program 1 when creating a target program, and vectorizes according to the number of loops during execution. A compiler 10 that determines an optimum execution form by parallelization, generates an instruction sequence corresponding to this optimum execution form on this object program, and generates an object program that branches to an instruction sequence according to the value of this loop count, and a compiler 10. And a translation result storage file 20 for storing the output target program of.

A feature of the present invention is that the compiler 10 includes vectorization parallelization condition output means 11 for storing the vectorization parallelization condition of the optimum execution mode in the translation result storage file 20. ..

Further, a source in which the source program 1 is input and a sentence for collecting execution information of the vectorized parallelized portion of the source program 1 is inserted based on the vectorized parallelization condition 2 stored in the translation result storage file 20. The program generation means 30 for generating a program and the execution information collection / output means 40 for collecting and editing the execution information based on the source program 3 output by the program generation means 30 and outputting the execution result 4 are provided.

The operation of the condition vectorization parallelization processing apparatus having such a configuration will be described. FIG. 2 is a diagram showing conditional expressions stored in the translation result storage file of the conditional vectorization parallelization processing device of the present invention. FIG. 3 is a flow chart showing the processing of the program generating means of the condition vectorization parallelization processing apparatus of the present invention. FIG. 4 is a diagram showing a source program in which a statement for collecting execution information of the program generating means of the condition vectorization parallelization processing device of the present invention is inserted. FIG. 5 is a diagram showing the execution result collected by the execution information collection output means of the condition vectorization parallelization processing device of the present invention.

In FIG. 1, the compiler 10 analyzes the DO loop in the source program 1 input by the vectorization parallelization condition output means 11 and optimizes the vectorization parallelization according to the number of loops during execution. The execution form is determined, and the condition is output to the translation result storage file 20 in which the translation result of the source program is stored. The program generation means 30 inputs the vectorization parallelization condition 2 from the source program 1 and the translation result storage file 20, and the source program 3 in which a statement for collecting execution information is inserted.
Is output. The execution information collection output means 40 inputs the source program 3 in which the statement for collecting the execution information generated by the program generation means 30 is input, collects the execution information, and outputs the collected execution result 4. ..

Next, the vectorized parallelization condition output means 11
Will be described in the case where the source program 1 as shown in FIG. 6 is input. The compiler 10 activates the vectorization parallelization condition output means 11 when the DO loop is detected in the source program 1 and the condition vectorization parallelization is performed. In this case, it is assumed that the DO vector (* 61) condition vector parallelization is performed. At this time, the determination is made as shown in FIG. 7 as in the conventional technique. When this means is started, the vectorization and parallelization conditions of the DO vectorization parallelized DO loop are output to the translation result storage file 20, and the processing is terminated.

FIG. 2 shows the DO in the translation result storage file 20.
This is loop information. * 21 is the line number in the source program with the DO statement of the DO loop, and * 22 is D
The sentence number of the terminal sentence of the O loop, * 23, is a word indicating that the DO loop is parallelized by the condition vectorization, and the above is the same as the conventional one. * 24 is a conditional expression for conditional vectorization and parallelization, and * 25 shows how to be vectorized and parallelized. In this case, '25
6. GT. N ', that is, when the loop count N is larger than 256,' PARALLEL, VECTOR '
Therefore, the DO loop is vector-processed by the multiprocessor. '4. GT. N ', that is, when the loop count N is larger than 4, it is'VECTOR', and therefore, '256. GT. Vector processing is performed except for the case of N '. Then, in the cases other than the above, that is, when the loop count N is 4 or less, the scalar processing is performed.

Next, the processing of the program generating means 30 will be described with reference to FIG. This means is activated when the user collects the execution information of the program. When the program generation means 30 is activated, it searches the translation result storage file 20 to display “ALTERNATIVE”,
That is, the information of the DO loop parallelized by the condition vectorization is obtained (step S1). Next, it is checked whether or not there is a condition that has not been processed yet under the registered conditions (step S2). If there is, check whether the first conditional expression is processed (step S
3). If it is the first conditional expression, 'IF (conditional expression) T
HEN 'is inserted immediately before the original DO loop (step S4), and if not,' ELSE IF (conditional expression) THEN 'is inserted immediately before the original DO loop (step S5). The conditional expression in the parentheses is the conditional expression registered in the information of the DO loop.

Next, a CALL statement of a runtime routine (hereinafter, referred to as RTP) for collecting the information of the DO loop is inserted immediately before the original DO loop (step S6).
Insert a directive line registered on the right side of the conditional expression immediately before the original DO loop (step S).
7). Next, the DO loop in which the terminal number of the DO loop is renumbered to a new one is inserted immediately before the original DO loop (step S8). Next, the RTP CALL sentence is inserted immediately before the original DO loop (step S9). It is checked whether there is a conditional expression that has not been processed (step S2), and the same processing is performed.

When all the conditional expressions have been processed, "ELSE" and the RTP CALL statement are inserted immediately before the original DO loop (steps S10 and S11). Next, in this case, since it is a case of processing with scalar, '* P
The instruction line "DIR NOPARALLEL, NOVECTOR '" is inserted immediately before the original DO loop (step S12). Immediately after the original DO loop, RTP CAL
Insert L sentence and'ENDIF '(steps S13, S
14) The processing of the program generation means 30 is ended. Figure 4
Is a source program in which a statement for collecting the execution information created by the program creating means 30 is inserted.

Next, the processing of the execution information collecting means 40 will be described. The execution information collecting means inputs the source program in which the sentence for collecting the execution information is input, translates, combines, and executes the source program, and collects the execution information. At that time, the information is edited as shown in FIG. 5 as the information of the DO loop parallelized to the condition vector, the execution result is output, and the processing is ended.

FIG. 5 shows an example of the execution information output by the execution information collecting means 40. * 51 is DO loop D
Line number in the source program with O statement, * 52
Is the sentence number of the terminal sentence of the DO loop, and * 53 is a word indicating that the DO loop has been parallelized by condition vectorization. *
54 is a word indicating which execution mode was processed, * 5
Reference numeral 5 is the collected execution information. In this case, 'PAR
ALLEL, VECTOR ', that is, the vector is processed 20 times by the multiprocessor, the vector is processed 200 times, and the scalar is processed 3 times.

[0025]

As described above, the present invention has an excellent effect that the efficiency of tuning can be improved, the execution time of a program can be shortened, and the execution performance can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a condition vectorization parallelization processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing conditional expressions stored in a translation result storage file of the conditional vectorization parallelization processing device of the present invention.

FIG. 3 is a flowchart showing the processing of the program generation means of the conditional vectorization parallelization processing device of the present invention.

FIG. 4 is a diagram showing a source program in which a statement for collecting execution information of program generation means of the conditional vectorization parallelization processing device of the present invention is inserted.

FIG. 5 is a diagram showing an execution result collected by an execution information collection output unit of the condition vectorization parallelization processing device of the present invention.

FIG. 6 is a diagram showing a source program of a condition vectorization parallelization processing device.

FIG. 7 is a diagram showing a determination result of conditional vectorization parallelization of a compiler of the conditional vectorization parallelization processing device.

FIG. 8 is a conceptual diagram of a target program of a compiler of a conventional condition vectorization parallelization processing device.

[Explanation of symbols]

 1, 3 Source program 2 Vectorization parallelization condition 4 Execution result 10 Compiler 11 Vectorization parallelization condition output means 20 Translation result storage file 30 Program generation means 40 Execution information collection output means

Claims (2)

[Claims] 1. A source program to be input is translated, a DO loop in the source program is analyzed at the time of creating a target program, an optimum execution form by vectorization parallelization is determined according to the number of loops at the time of execution, and this optimum A compiler for generating an instruction sequence corresponding to the execution form on this object program and generating an object program branching to the instruction sequence according to the value of this loop count, and a translation result storage file for storing the output target program of this compiler In the conditional vectorization parallelization processing device, the compiler includes vectorization parallelization condition output means for storing the vectorization parallelization condition of the optimum execution mode in the translation result storage file. Parallel processing device. 2. A source program into which a statement for inputting the source program and inserting execution information of a vectorized parallelized portion of the source program based on the vectorized parallelization condition stored in the translation result storage file is inserted. 2. The condition according to claim 1, further comprising: a program generating unit that generates a program, and an execution information collecting and outputting unit that executes the program based on the source program output by the program generating unit to collect and edit the execution information and output the execution result. Vectorization parallelization processor.