JPH05151172A - Data transfer system - Google Patents

Abstract

PURPOSE:To eliminate the connection of a CPU to an I/O and to perform data transfer from plural CPUs to an arbitrary I/O in a CPU system in which the plural CPUs are coupled with plural I/Os with a bus. CONSTITUTION:Registers 16, 17 readable and settable its own CPU No. are provided in the CPUs 11, 12, and semaphores 18, 22 which store the CPU No. being processed, common memory 19, 23 for communication with the I/Os, and CPU monitoring timers 20, 24 which detect the fault of the CPU being processed are provided, and when the operation of the I/O is completed, an interruption signal is outputted to the CPU with the CPU No. in accordance with the one stored in the semaphores 18, 22. Also, processing pointers are provided in the common memory 19, 23 for communication, in which data can be accumulated as processing awaiting data even when another CPU is performing processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU / I / O data transfer system in a multi-CPU system in which a plurality of CPUs and a plurality of I / Os are bus-coupled.

[0002]

2. Description of the Related Art Conventionally, in this type of data transfer system, as shown in FIG. 2, I / O3 and I / O4 are respectively CPUs.
1, fixedly connected to the CPU 2 by interrupt request signals 7 and 8.

In this state, the received data from I / O3 is I
When transmitting to / O4, the CPU 1 first develops the received data in the common memory 5 via the bus 6 in response to the interrupt request signal 7 from the I / O 3.

Next, the CPU 1 outputs an interrupt request signal 9 to the CPU 2, and the CPU 2 outputs an I / O signal from the common memory 5.
Receives data sent to O4.

Thereafter, the CPU 2 makes a transmission request to the I / O 4, and the completion of transmission is notified by an interrupt request signal 8.

On the contrary, the received data from the I / O4 is transferred to the I / O3.
Also in the case of sending to, the CPU 2 expands the received data in the common memory 5 and outputs the interrupt request signal 10 to the CPU 1.

The CPU 1 is activated by the interrupt request signal 10, receives data to be sent to the I / O 3 from the common memory 5, and makes a send request to the I / O 3.

As described above, since each CPU starts its processing by the interrupt from the I / O, the I / O not under its own control
For O, the CPU to which the I / O interrupt is connected
Need to request processing.

[0009]

[Problems to be Solved by the Invention] Conventional CPU and I / O
In the data transfer method of gang wrapping, there is a problem that a failure of one CPU renders all the I / Os under it inoperable and stops a specific function as a system.

In addition, increasing the number of CPUs in order to increase the processing capacity of the system also changes the allocation of subordinate I / Os, which requires a change in hardware configuration and programs. ..

An object of the present invention is to provide a data transfer system which eliminates the connection between the CPU and the I / O and transfers data from a plurality of CPUs to an arbitrary I / O.

[0012]

In order to achieve the above object, in the data transfer system according to the present invention, a plurality of C
In a multi-CPU system in which a PU and a plurality of I / Os are connected by a bus, the CPU with its own CPU NO. Has a register that can read this, and in the I / O,
CPU No. being processed. Semaphore and I / O
And a common memory for communication with the CPU, a CPU monitoring timer for detecting a CPU failure during processing, and a CPU No. stored in the semaphore when the I / O operation is completed. And an interrupt control unit that notifies an interrupt to the CPU corresponding to.

The processing pointer and the processing data are stored in the communication common memory.

[0014]

When the I / O operation is completed, the CPU NO. By outputting an interrupt signal to the CPU corresponding to, the coupling between the CPU and the I / O is eliminated.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, this embodiment shows a plurality of CPUs 1.
1 and 12 and a plurality of I / Os 13 and 14 are connected by a bus 15 to a multi-CPU system.

The CPUs 11 and 12 have their own CPU NO.
And registers 16 and 17 capable of reading the same.

On the other hand, each I / O 13, 14 has a CPU NO. Semaphores 18 and 22 that store
Common memory 19, 23 for communication with O, and CPU in process
CPU monitoring timers 20 and 24 for detecting failures, and I / O
CPU stored in the semaphore 18, 22 when the operation of the
NO. Interrupt control units 21 and 25 for notifying an interrupt to the CPU 11 or 12 corresponding to. 28, 29
Is a send pointer. Processing pointers and processing wait data are stored in the communication common memories 19 and 23.

When the CPU 11 sends data to the I / O 13, the CPU 11 checks the semaphore 18 in the I / O 13, and if it is in the reset state, the CPU 11 that is the NO. The CPU monitoring timer 20 is preset by setting the semaphore value in the semaphore 18, writing the transmission data in the communication common memory 19, setting the transmission pointer 28 and activating the transmission.

When the transmission operation is completed by the I / O 13, the CPU of the request source is based on the value set in the semaphore 18.
The interrupt request signal 26 for 11 is output from the interrupt control unit 21 and the CPU monitoring timer 20 is counted.

The CPU 11 responds to the I request by the interrupt request signal 26.
/ O13 transmission completion is detected, communication common memory 1
It is checked whether or not there is data waiting to be transmitted in 9, and if there is no data waiting to be transmitted, the semaphore 18 and the CPU monitoring timer 2
0 is reset, and the process ends.

If there is data waiting to be transmitted in the common memory for communication 19, the stored first data is taken out, and the CPU No. Is set in the semaphore 18 and the transmission pointer 28 is updated to start transmission, whereby the CPU monitoring timer 20 is preset again.

When the CPU 11 or the CPU 12 transmits data when the semaphore 18 of the I / O 13 is set, the CPU monitoring timer 20 is checked, and if the counter value is set, the I / O 13 is transmitting. It is judged that the own CPU NO. And the transmission data are set, and the process ends.

Even if the semaphore 18 of the I / O 13 is set, the CP set in the semaphore 18 if the CPU monitoring timer 20 is reset due to timeout.
UNO. The CPU of No. 1 is regarded as down, and its own CPU NO. After setting the transmission data and the transmission data, the top data in the communication common memory 19 is taken out, and the CPU NO. Is set in the semaphore 18, the transmission pointer 28 is updated, and transmission is started to preset the CPU monitoring timer 20 and restart the transmission operation of the I / O 13.

[0025]

As described above, according to the present invention, it is possible to transfer data from a plurality of CPUs to arbitrary I / Os by eliminating the connection between the CPUs and I / Os, and one CPU becomes a failure. Also, there is an effect that it is possible to construct a load balancing type multi-CPU system that can be operated without stopping the function of the system.

Further, since the number of CPUs does not affect the programs and the like, there is an effect that the number of CPUs can be easily increased according to the actual load.

In addition, when transferring data between I / O, the CPU
It has an effect that it can be implemented without data transfer between them.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 1,2,11,12 CPU 3,4,13,14 I / O 5 Common memory 6,15 Bus 7,8,9,10,26,27 Interrupt request signal 16,17 Register 18,22 Semaphore 19, 23 Common memory for communication 20,24 CPU monitoring timer 21,25 Interrupt control unit 28,29 Transmission pointer

Claims (2)

[Claims] 1. In a multi-CPU system in which a plurality of CPUs and a plurality of I / Os are connected by a bus, in the CPU, the own CPU NO. , And has a register capable of reading this. In the I / O, the CPU NO. , A common memory for communication with I / O, and a CPU being processed
A CPU monitoring timer for detecting a failure, and a CPU No. stored in the semaphore when the I / O operation is completed. C corresponding to
A data transfer method, comprising: an interrupt control unit that notifies the PU of an interrupt. 2. The data transfer method according to claim 1, wherein a processing pointer and processing data are accumulated in the communication common memory.