JPH05151066A - Fixed storage readout controller - Google Patents

Abstract

PURPOSE:To decrease the frequency of access and to save the consumption of electric power by providing a readout control circuit which reads plural unit words out of a fixed storage device by single-time access and outputs pieces of identification information enabling one of the unit words to be selected and outputted sequentially as many as the no. of unit words. CONSTITUTION:This controller is provided with the fixed storage device ROM 14 stored with the unit words each consisting of plural bits so that they can be read out by single-time access and the read out control circuit 16 which reads the unit words out of the fixed storage device 14 by the single-time access and outputs the pieces of identification information for selecting and outputting one of the unit words sequentially as many as the unit words. A selector 15 which has its input connected to the readout output of the fixed storage device 14 selects and extracts the unit words individually with the identification information sent from the readout control circuit 16. Consequently, the individual unit words can be selected as final outputs and the access frequency is decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a fixed memory read control device for reducing power consumption. A high-efficiency speech coder (LRE: Low) which is an application example of a digital signal processing LSI (hereinafter abbreviated as DSP) to speech processing.
Rate Encoder) is of course required to have high speed, but recently, it has been widely used for mobile communication, and since it has been installed in passenger cars, the demand for low power consumption has increased. ing.

[0002]

2. Description of the Related Art First, the general structure and function of a DSP will be described. FIG. 4 is a block diagram showing a general configuration of the DSP.

In the figure, reference numeral 1 indicates a DSP as a whole, and inside is an interface block 2, a data storage device 4, an address generation block 5, an arithmetic logic operation circuit (A).
LU) 6, an instruction storage device 7, and an execution control block 8, which are interconnected by an internal bus 3.

In the figure, in the DSP 1, the data read from the interface block 2 is transferred to the data storage device 4 via the internal bus 3. Data storage device 4
The data stored in is read at the address generated in address generation block 5, calculated in ALU 6, and processed. The procedure of data processing is written in the instruction storage device 7, and the contents of the instruction storage device 7 are accessed, read, decoded by the execution control block, and sent to the ALU 6 every machine cycle of the DSP. The processed data is transferred to the data storage device 4 again, and further transferred from the data storage device 4 to the interface block 2 and sent out.

Next, a conventional fixed storage read control device will be described. As described above, in the DSP, the contents of the instruction storage device 7 are frequently accessed every machine cycle. A fixed storage device (ROM) is mainly used as the instruction storage device 7. Hereinafter, this is referred to as a fixed storage device or ROM.

FIG. 5 is a principle diagram of this prior art. In the principle diagram, the storage device portion is mainly shown, and the read control portion is not shown. As shown in the figure, the conventional ROM 9
The number of bits forming one instruction word is m, and the total storage capacity is m.
In the case of bits × n words, a matrix is formed in which m-bit memory cells are rows (horizontal axis) and n-bit memory cells are columns (vertical axis). Only one instruction word is read out.

FIG. 6 shows a specific circuit example of the fixed memory read control device from reading the instruction word from the conventional ROM 9 to decoding the instruction word. In this circuit example, a CMOS ROM is used as a memory device, and m =
32, n = 1024. In the figure, blocks other than the ROM 9, that is, the program counter 10, the first instruction register 11, the second instruction register 12, and the decoder 13 are accommodated in the execution control block 8 in FIG.

The instruction word stored in the ROM 9 is accessed in a machine cycle with the output value of the program counter 10 as an address, and is read into the first instruction register 11 word by word in each machine cycle. Further, in the next machine cycle, it is read into the second instruction register 12, and the outputs of the first instruction register 11 and the second instruction register 12 are sequentially decoded by the decoder 13 and used for pipeline processing to be executed.

In the configuration shown in FIG. 6, the ROM 9 corresponds to the instruction storage device 7 shown in FIG. 4, and as described above, the other parts from the program counter 10 to the decoder 13 are the execution control block 8 in FIG. It is housed in. Therefore, the decoded instruction execution control signal is shown in FIG.
And is used for arithmetic control.

FIG. 7 is a time chart of signals at various points in the circuit of FIG. As shown in the figure, the output value of the program counter 10 is the address ..., 0, 1, 2 ,.
C, D, E, ... Used to access the ROM 9 in the machine cycle, and the first instruction register ... (0),
It is read as (1), (2), ..., (C), (D), (E) ,. Here, for example, (X) indicates the data written in the address X. Further, it is read into the second instruction register 12 in the next machine cycle, and as described above, the outputs of the first instruction register 11 and the second instruction register 12 are decoded by the decoder 13 and used for pipeline processing. Further, (4) is a branch instruction, and the next machine cycle is also used for the branch instruction.
The data output from is the ROM 9A.

[0011]

In the conventional technique as described above, the storage device is frequently accessed every machine cycle.

A feature of the recent DSP is that it incorporates a large-capacity instruction storage device because signal processing is performed by a one-chip LSI. Therefore, the power consumption is also large, and when mounted on a vehicle, the power consumption greatly affects the capacity of the battery serving as a power source.

In general, the power consumption of a ROM based on CMOS is expressed by the following empirical formula. {(Word number x bit number dependent part) + (word number dependent part) + (bit number dependent part)} x access frequency (frequency) It is shown by an empirical formula. As described above, the power consumption of the fixed storage device largely increases depending on the access frequency, and occupies 50% or more of the power consumption of the DSP in the conventional example.

An object of the present invention is to provide a fixed storage read control device with reduced power consumption by reducing the access frequency of the fixed storage device.

[0015]

FIG. 1 is a principle diagram showing a basic configuration of a fixed memory read control device according to the present invention.

In the figure, 14 is a fixed storage device (ROM),
The selector 15 and the read control circuit 16 are the main parts of the read control device of the present invention. As shown in the figure, a fixed storage device (14) for storing a plurality of unit words composed of a plurality of bits so as to be readable by one access, and the fixed storage device (14).
A read control circuit (16) for sequentially reading the plurality of unit words by one access and sequentially outputting the identification information for selecting and outputting any one of the plurality of unit words for the number of unit words; Persistent storage (1
4) The read output of 4) is connected to the input, and a selector (15) for receiving the identification information at the selection control input is provided.

[0017]

The fixed storage device ROM 14 of the present invention shown in FIG.
Has an originally required storage capacity of, for example, m bits ×
In the case of n words, it is assumed that the row (horizontal axis) storage cells have k · m bits and the column (vertical axis) storage cells have n / k bits in a matrix configuration. Where k is an integer,
A unit word is m bits. Then, the access frequency is not set to the machine cycle, and k unit words are read by one access. Therefore, the access frequency is every k machine cycles. The selector 15 is for individually selecting the k unit words that have been read, and performs selection based on the identification information sent from the read control device 16.
Unit words are fetched individually.

As described above, according to the fixed memory read control device of the present invention, the final output can be sorted into individual unit words and the access frequency can be reduced.

[0019]

FIG. 2 is a diagram showing the construction of an embodiment of the present invention. In the figure, 14 is a ROM, 15 is an alternative selector,
Reference numeral 18 denotes a program counter, 17 denotes a transfer circuit for transferring the LSB of the program counter 18 to the selector 15, and the program counter 18 and the transfer circuit 17 are shown in FIG.
Corresponds to the read control circuit 16 in FIG.

It is assumed that the ROM 16 is formed of CMOS and the total storage capacity required is 32 bits × 1024 words, and k is the simplest example, when k = 2, that is, row = 64 bits, column. = 512 bits, the stored unit word is a 32-bit instruction word, and one line is two instruction words.

The program counter 18 outputs an address in which two words of an instruction word are one access unit for two machine cycles, and the LSB of the address used for accessing the access unit is two machine cycles. The program counter 18 is controlled so that it is set to "0" in one machine cycle before and after it is set to "1" in one machine cycle. The frequency of access to the ROM 14 is once every two machine cycles, and therefore 1
Two instruction words are read by one access, and two instruction words are added to the data input of the selector 15 for two machine cycles.

On the other hand, in the transfer circuit 17, from the program counter 18 to the L cycle in the same cycle as the machine cycle.
Since SB is added, the LSB outputs a 1-bit binary code having "0" for the previous one machine cycle and "1" for the subsequent one machine cycle to the selector 15 as identification information. In this embodiment, It is applied to the control input of the alternative selector 15. Therefore, in the output of the selector 15, only the previous instruction word is present in one machine cycle before the identification information is "0", and the subsequent instruction is issued in the one machine cycle after the identification information is "1". Only words are output.

FIG. 3 is a time chart of signals at various points in the embodiment circuit of FIG. As shown in the figure, the program counter 18 has an address for every two words of the instruction word, ...
, 0, 2, ..., A, C, ... Are output, and the ROM 14 is accessed once every two machine cycles. At this time, one address, for example, 2 and two instruction words, for example, (2),
Since (3) is read, these two instruction words are added to the data input of the selector 15.

On the other hand, the transfer circuit 17 has an LSB updated from the program counter 18 every machine cycle.
Is added to the control input of the selector 15 as identification information. Therefore, the selector 15 selects and outputs only the previous instruction word, for example, (2) in the previous machine cycle, and the subsequent instruction word, for example, (3) in the subsequent machine cycle.

Thus, reading from the ROM 14
The previous word and the subsequent word are bit-parallel. Further, (4) is a branch instruction, and the next instruction word (5)
Does not appear in the output of the second instruction register not shown in FIG. This is similar to the case of FIG.

In the above embodiments, the CMO is used as the storage device.
I used S ROM, but bipolar ROM
With the same cell structure, almost the same effect can be obtained. Further, the required storage capacity is assumed to be 32 bits × 1024 words, but of course it is not necessary to specify such a value.

Next, the integer k will be described. In the above embodiment, k = 2, but this may be any integer. When the general integer k is applied as the selector 15, a k-choice selector is used. The program counter 18 outputs one address for each k word of the instruction word, and the ROM 1
4 are accessed once per k machine cycles. At this time, since k instruction words are read by one access, k instruction words are added to the data input of the selector 15 during k machine cycles.

On the other hand, the J bit is output from the program counter 18 to the transfer circuit 17 in the same cycle as the machine cycle. For example, the first machine cycle is ... 00, the second machine cycle is ... 01, the third machine cycle is ... 10, the fourth machine cycle is ... 11, that is, a binary code of J = 2 bits is output. To be done. However, 2 ^J ≧ k.

The binary code is added to the control input of the selector 15 as identification information. Therefore selector 1
In the output of 5, the first instruction word is in the cycle where the identification information is ... 00, the second instruction word is in the cycle of 01, and the third instruction word is in the cycle of ... 10. ,… 11
In the cycle, the fourth instruction word is read. To realize this, a k-selector having a J-bit binary code control input terminal may be used.

As described above, it goes without saying that the larger k is, the larger the contribution to the reduction in power consumption.

[0031]

As described above, the power consumption of the CMOS ROM is expressed by the following empirical formula. {(Word number x bit number dependent part) + (word number dependent part) + (bit number dependent part)} x access frequency (frequency) According to the present invention, in the above equation, the terms are Unchanged
The term is 1 / k times, the term is k times, and is 1 / k times, so if the parentheses are removed, it becomes × 1 / k + × 1 / k ² + × 1,
The part that depends on the number of words × the number of bits can be 1 / k, and the part that depends on the number of words can be 1 / k ² .

In the case of the ROM of the bipolar type, almost the same effect as described above can be achieved. Therefore, according to the present invention, the function of the fixed storage device having the same total storage capacity can be greatly reduced. Can be achieved with.

[Brief description of drawings]

FIG. 1 is a principle diagram showing a basic configuration of a fixed memory read control device of the present invention.

FIG. 2 is a circuit diagram of a specific embodiment including a fixed memory read control device of the present invention.

FIG. 3 is a time chart of signals at various points in the circuit of FIG.

FIG. 4 is a block diagram showing a general configuration of a DSP.

FIG. 5 is a block diagram showing a basic configuration of a conventional fixed storage read control device.

FIG. 6 is a circuit diagram showing a conventional fixed memory read control device.

FIG. 7 is a time chart of signals at various points in the circuit of FIG.

[Explanation of symbols]

 14 Fixed Storage Device 15 Selector 16 Read Control Circuit

Claims (1)

[Claims] 1. A plurality of unit words each consisting of a plurality of bits
Persistent storage device (14) that stores readably by access
And the identification information for reading out the plurality of unit words by one access to the fixed storage device (14) and selecting and outputting any one of the plurality of unit words is output in order by the number of unit words. Read control circuit (16)
And a selector (15) having an input connected to a read output of the fixed storage device (14) and receiving the identification information at a selection control input.