JPH08137666A - Arithmetic unit and its arithmetic method - Google Patents

Abstract

PURPOSE: To allow the arithmetic unit of a processor structure to conduct bit arithmetic processing such as interleave arithmetic processing, de-interleave arithmetic processing and coding processing of convoluted codes efficiently. CONSTITUTION: An instruction decoder 3 commands directly a shift number and a barrel shifter 4 makes shift operation and an arithmetic logic unit 6 makes OR arithmetic operation in the case of interleave arithmetic processing. In the case of de-interleave arithmetic processing, the unit 6 conducts AND arithmetic processing and conducts exclusive OR arithmetic processing in the case of coding convolution codes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit for performing a logical operation with a processor structure and an arithmetic method therefor.

[0002]

2. Description of the Related Art In recent years, a digital signal processor (hereinafter abbreviated as DSP) has been used as a processor for equipment incorporation in a digital system in the mobile communication field.

In the application of DSP to the field of mobile communication, interleave processing for rearranging data bit strings is performed as a measure against burst errors. Since interleaving is performed in bit units, it cannot be efficiently processed by a processor that mainly processes words.

An example of the operation of the conventional arithmetic unit will be described below with reference to the schematic block diagram shown in FIG.

In FIG. 3, 201 is a data memory, which holds data. An instruction memory 202 holds instructions. An instruction decoder 203 decodes an instruction output from the instruction memory 202. 20
Reference numeral 4 is a barrel shifter, which performs the designated number of shifts. Reference numeral 205 denotes a shift number instruction register, which indicates the shift number of the barrel shifter 204. Reference numeral 206 denotes an arithmetic logic operation unit, which outputs the output of the barrel shifter 204 and a bus 2 described later.
An arithmetic operation or a logical operation is performed between 08 data.
Reference numeral 207 is a register, which temporarily holds the operation result of the arithmetic logic operation unit 206. A bus 208 supplies the data of the register 207 to the arithmetic logic operation unit 206.
Reference numeral 209 denotes a bus, which transfers data from the register 207 and data output from the data memory 201 and the instruction decoder 203 to the barrel shifter 204 or the shift number instruction register 2
Supply to 05.

In the arithmetic unit configured as described above, the interleave arithmetic operation will be described below. (1) First Step The instruction decoder 203 decodes the instruction output from the instruction memory 202 (instruction to instruct the shift number instruction register 205 to store data). As the shift number, for example, an instruction for instructing a left 3-bit shift, 3 is output from the instruction decoder 203 to the bus 209, and 3 is held in the shift number instruction register 205 via the bus 209. (2) Second step Command output from command memory 202 (address of data memory 201 is directly given in command
Each of the circuits operates in accordance with an instruction to perform the shift of the shift number designated by the shift number designation register 205 using the barrel shifter 204 and to store the result in the register 207 after passing through the arithmetic and logic unit 206. To do.

At this time, there is a word in which an address designated to the data memory 201 has meaningful data only in the least significant bit, and 0 is included in other than the least significant bit. Since the word is left-shifted by 3 bits, after the second step, the word held in the register 207 has 0 from the least significant bit to the second bit and has the meaning at the third bit. Is present, and 0 is entered from the 4th bit onward up to the most significant bit. (3) Third Step An instruction output from the instruction memory 202 (an address different from the address designated in the second step in the instruction is directly given to the data memory 201, and the barrel shifter 204 outputs the data to the output of the data memory 201. Shift number 0
Each circuit operates in accordance with an instruction to take the logical sum of the output of the register 207 and the output of the register 207 via the bus 208 and the arithmetic logic operation unit 206 and save the result in the register 207.

At this time, the address instructed to the data memory 201 has meaningful data up to the second bit in the middle of interleaving, and the data including 0 from the third bit onward to the most significant bit. Shall be.

After the completion of the third step, the register 207 has meaningful data up to the third bit, and has data of 0 from the fourth bit to the most significant bit. (4) Fourth Step The data stored in the register 207 in the third step is stored in the data memory 201 via the bus 209. The third address to be stored in the data memory 201
Specify the same address as specified in step.

The interleave operation for 1 bit can be performed through the steps 1 to 4 described above. In the example shown above, the meaningful data is inserted in the third bit by shifting the left 3 bits, but the left shift number is sequentially changed to 1 bit, 2 bits, 4 bits, 5 bits. By doing so, meaningful data can be inserted into an arbitrary bit, so that the interleave operation is performed by sequentially changing the left shift number stored in the shift number instruction register 205.

[0011]

However, in the above-described conventional arithmetic unit, 1-bit interleave operation requires 4 steps, and when n-bit interleave operation is performed, 4 × n steps are required, resulting in efficient processing. Not relevant. Moreover, since a large number of steps are required, a large amount of power is consumed. Further, in the above-mentioned conventional example, since the address designated in the second step is different for each 1-bit interleaving operation, it is necessary to give a solid instruction when repeatedly executing an instruction sequence for 1-bit interleaving ( Cannot use repeated instructions). Therefore, a large number of static steps of instructions are required, and a large amount of instruction memory is required. The increase in chip area required for instruction memory is
Leading to higher prices.

The present invention solves the above-mentioned conventional problems, and it is possible to efficiently execute an operation with a small number of instructions. Therefore, it is possible to achieve high performance, low power consumption and low cost. It is an object of the present invention to provide a calculation device and a calculation method for the calculation device.

[0013]

The arithmetic unit of the present invention for achieving the above object has a structure in which the number of shifts can be directly instructed from an instruction decoder, and a storage means for holding arithmetic data and an arbitrary number of shifts are provided. It comprises a possible barrel shifter, a shift number instruction register for holding the shift number of this barrel shifter, and an operation means for performing a logical sum.

Another arithmetic unit of the present invention for achieving the above object is the arithmetic unit, wherein the arithmetic unit performs a logical product instead of a logical sum, and is provided with a constant generation circuit.

Still another arithmetic unit of the present invention for achieving the above object is the above arithmetic unit, wherein the arithmetic unit is configured to perform exclusive OR instead of logical product.

The arithmetic method of the present invention for achieving the above object uses the first arithmetic unit described above to specify a shift number,
The interleave operation is performed by a method of assembling data from a word having valid data of only 1 bit by using an instruction for performing shift and logical OR operation with a single instruction.

Another arithmetic unit of the present invention to achieve the above object is to use the second arithmetic unit to specify the number of shifts, perform the shift, and execute an instruction to perform a logical product operation with a single instruction. The deinterleaving operation is performed by a method of decomposing a word having valid data into a word having valid data of only 1 bit.

Still another operation method of the present invention for achieving the above object is to use the third operation device described above, specify a shift number, perform a shift, and perform an exclusive OR operation with a single instruction. The convolutional code is encoded by a method of taking an exclusive OR between arbitrary bits using an instruction to be executed.

[0019]

With the above arrangement, the present invention makes it possible to specify the number of shifts, perform the shifts, and perform the OR operation, the AND operation, and the exclusive OR operation with a single instruction.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment of the present invention will be described. FIG. 1 is a schematic block diagram showing an arithmetic unit according to the first embodiment of the present invention.

In FIG. 1, 1 is a data memory,
Holds the data. Reference numeral 2 is an instruction memory, which holds instructions. An instruction decoder 3 decodes an instruction output from the instruction memory 2. Reference numeral 4 is a barrel shifter, which shifts the indicated value. A shift number instruction register 5 indicates the shift number of the barrel shifter 4. Reference numeral 6 denotes an arithmetic logic operation unit, which performs arithmetic operations or logical operations. Reference numeral 7 is a register, which temporarily holds the operation result of the arithmetic logic operation unit 6. A bus 8 supplies the data of the register 7 to the arithmetic and logic unit 6. Reference numeral 9 is a bus, and the data of the register 7 and the data memory 1
Is supplied to the barrel shifter 4 or the shift number instruction register 5.

In the arithmetic unit configured as described above, the interleave arithmetic operation will be described below.

An instruction to be output from the instruction memory 2 (instructing the shift number to the shift number instruction register 5 and directly giving the address of the data memory 1 in the instruction, the shift number instruction register 5 to the output data of the data memory 1 The instructed shift is performed by using the barrel shifter 4, and each circuit operates according to the output of the register 7 via the bus 8 and a logical sum (OR) in the arithmetic logic unit 6 and the instruction to save in the register 7.

At this time, meaningful data exists only in the least significant bit at the address designated to the data memory 1,
There is a word that contains 0 other than the least significant bit. In the case where the word is left-shifted by 3 bits, for example, the output of the barrel shifter 4 has 0 from the least significant bit to the 2nd bit, there is meaningful data at the 3rd bit, and the 4th bit. The data is 0 from the bit bit onward to the most significant bit.

The data held in the register 7 is data in the middle of interleaving, has meaningful data up to the second bit, and contains 0 from the third bit to the most significant bit. It is assumed that there is data.

After completion of the logical sum operation in the arithmetic and logic unit 6, the register 7 has significant data up to the third bit, and data including 0 from the fourth bit to the most significant bit. Become.

The interleaving operation for 1 bit is performed only in the one step shown above. Therefore, the number of steps required for interleaving processing can be reduced.

In the example described above, the meaningful data is inserted in the third bit by shifting the left 3 bits, but the left shift number should be sequentially changed to 4 bits and 5 bits. Since it is possible to insert meaningful data in any bit, the interleave operation is performed by sequentially changing the left shift number.

In the above processing, an example in which an interleave operation is executed has been shown, but the above arithmetic unit also has an effect of reducing the number of steps in the bit string processing other than the interleave operation.

Next, a second embodiment in the case of the operation of taking the logical product (AND) in the arithmetic logic operation unit 6 will be described.

In the above embodiment, the process of assembling the bit strings is performed to perform the interleaving. In the deinterleave processing, the bit string is decomposed. In other words, when all bits in a word have meaningful data, the process of converting to data in which only the least significant bit of the word has valid bits and all other bits are 0 is the deinterleaving process. is necessary.

A second embodiment for performing the deinterleave processing will be described below. In this second embodiment, FIG.
As shown in FIG. 1, in the first embodiment shown in FIG.
The feature is that the constant generation circuit 10 is added. The constant generation circuit 10 is capable of generating a number in which the least significant bit is 1 and the other bits are 0, and is connected to the bus 8.

An instruction output from the instruction memory 2 (instructing the shift number to the shift number instruction register 5 and directly giving the address of the data memory 1 in the instruction, the shift number instruction register 5 outputs the output data of the data memory 1 to the shift number instruction register 5). The instructed shift is performed using the barrel shifter 4, and the output of the constant generation circuit 10 via the bus 8 and the logical sum (A
Each circuit operates in accordance with the instruction for taking ND) and saving it in the register 7.

At this time, it is assumed that all the bits of the address word instructing the data memory 1 are filled with meaningful data. In the case where the word is right-shifted by 3 bits, for example, the output of the barrel shifter 4 has the data of the third bit before shifting to the least significant bit.

After completion of the logical product operation in the arithmetic and logic unit 6, the register 7 has data only in the least significant bit, and is 0 otherwise.

The deinterleave operation for one bit is performed only in the one step shown above. As a result, the number of steps required for the deinterleave processing can be reduced.

In the example shown above, only the data at the third bit is moved to the least significant bit by shifting the right 3 bits, but the right shift number is sequentially changed to 4 bits and 5 bits. Since the data in any bit can be moved to the least significant bit by doing so, the deinterleave operation is performed by sequentially changing the right shift number.

The constant generating circuit 10 of the above-mentioned example
Can be a register. When performing deinterleave processing, the least significant bit is 1 and the other bits are 0
By setting a certain number, the same operation as that of the above-described embodiment can be performed. Further, the number generated by the constant generation circuit 10 is set to 1 only for the necessary bits and 0 is set for the unnecessary bits, thereby improving the processing capability in other bit processing operations other than deinterleaving. You can

Next, a third embodiment in the case of the operation of taking the exclusive OR (XOR) in the arithmetic logic operation unit 6 will be explained.

As an example of the case of taking the exclusive OR, there is a case of generating a convolutional code. To generate a convolutional code, it is necessary to take an exclusive OR between data.

A third embodiment for generating a convolutional code will be described below. In this third embodiment, FIG.
In the data generated from the constant generating circuit 10 shown in (1), the least significant bit is 1, and the other bits are 0.

In the following example, the case where the delay element is D and G = 1 + D ² (here, + represents an exclusive OR) is shown as the generation function of the encoder. (1) First Step Instruction output from the instruction memory 2 (instructing the shift number in the shift number instruction register 5 and giving the address of the data memory 1 directly in the instruction to output data of the data memory 1
The shift designated by the shift number designation register 5 is performed using the barrel shifter 4. Constant generation circuit 10 via bus 8
And the arithmetic logical operation unit 6 take the logical product (AND) and store it in the register 7. Each circuit operates according to the instruction.

At this time, it is assumed that the address designated to the data memory 1 has data to be encoded. In the first step of this embodiment, 0-bit shift is performed (that is, shift is not performed).

After the exclusive OR operation in the arithmetic and logic unit 6, the register 7 has meaningful data only in the least significant bit, and 0 otherwise. (2) Second step Instruction output from instruction memory 2 (instructing shift number in shift number instruction register 5 and giving address of data memory 1 directly in the instruction to output data of data memory 1
The shift designated by the shift number designation register 5 is performed by using the barrel shifter 4, and the exclusive logical sum (EXOR) is performed by the arithmetic logic unit 6 and the data of the register 7 via the bus 8.
And each circuit operates according to the instruction to store the data in the register 7).

At this time, there is encoded data in the address designated to the data memory 1, and it is the same address as the address designated in the first step.

In the second step of this embodiment, a 2-bit right shift is performed. After the exclusive OR operation in the arithmetic logic operation unit 6 is completed, the least significant bit of the register 7 stores the operation result of the above generation function.

The generation function G of the encoder is generated in the above two steps. As a result, it becomes possible to carry out the encoding process of the convolutional code with a small number of steps.

In the example described above, the number of terms is two as the generation function of the encoder, but if the number is more than that, the shift number is changed in the second step and the second step is used. It is possible to continue by the number of terms.

In the present embodiment as well, as in the second embodiment, by using the constant generating circuit 10 of the above-described example as a register, the least significant bit is 1 first and the other bits are not. The same operation is possible by setting a number that is 0.

[0051]

As described above, according to the present invention, it is possible to execute the interleave processing which conventionally required four steps in one step, and it is possible to reduce the number of static and dynamic steps. . If the logical product is used instead of the logical sum, the number of static and dynamic steps of the deinterleaving process can be reduced. Also, if exclusive OR is performed instead of logical product, it is possible to reduce the number of static and dynamic steps in the encoding process of the convolutional code. By reducing the number of dynamic steps in this way, power consumption can be reduced by lowering the operating speed. Further, at the same operation speed, other processing can be executed, and the processing capacity is improved. Further, by reducing the number of static steps, the area required for the instruction memory can be reduced, so that the instruction memory can be provided at a low price.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an arithmetic unit according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram showing an arithmetic unit according to a second embodiment of the present invention.

FIG. 3 is a schematic block diagram showing a conventional arithmetic unit.

[Explanation of symbols]

 1 Data Memory 2 Instruction Memory 3 Instruction Decoder 4 Barrel Shifter 5 Shift Number Instruction Register 6 Arithmetic Logic Operation Unit 7 Register 8 Bus 9 Bus 10 Constant Generation Circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G06F 15/31 D

Claims (6)

[Claims] 1. A storage device for storing operation data, a barrel shifter capable of shifting an arbitrary number, a shift number instruction register for holding the shift number of this barrel shifter, and an operation device for performing a logical sum operation. An arithmetic unit configured so that a single instruction can specify, shift, and perform an OR operation. 2. The arithmetic unit according to claim 1, wherein the arithmetic means performs a logical product instead of a logical sum and includes a constant generation circuit. 3. The arithmetic unit according to claim 2, wherein the arithmetic means performs an exclusive OR instead of the logical product. 4. An arithmetic unit according to claim 1 is used to specify a shift number, perform a shift, and perform an OR operation with a single instruction. A calculation method that performs interleave calculation by the method of assembling data. 5. The arithmetic unit according to claim 2, wherein an instruction for specifying the number of shifts, performing the shift, and performing a logical product operation with a single instruction is used, and only one bit is present from a word having valid data. A method of deinterleaving operations that decomposes data into words that have valid data. 6. An exclusive logic between arbitrary bits using the arithmetic unit according to claim 3 and using an instruction for designating a shift number, performing a shift, and performing an exclusive OR operation with a single instruction. An arithmetic method that encodes a convolutional code by a summation method.