JPH05150738A - Image data processing method for liquid crystal display plate - Google Patents

Abstract

PURPOSE:To simplify the constitution and facilitate the control and to reduce the size and power consumption of the device by reading out or writing image data of one pixel for every four bits of one-byte data in a specific address of a random access memory. CONSTITUTION:One-byte data of two pixels are generated by using four-bit data of one pixel as the high-order or low-order four-bit data in one byte in a CPU 10. Then an address signal is outputted from the CPU 10 to an address bus, data of two pixels for one byte are outputted to a data bus, and a write instruction is outputted to a control bus with a read/write signal and written in a video RAM 25. Addresses are outputted as an address signal in specific order from the address specifying circuit 32 of a video signal controller 30 and image data of two pixels are read in the controller 30 and stored in registers 37 and 38. The data are made into four-bit data having specific weight by a gradation data generating circuit 36 and sent to a liquid crystal display plate control circuit 17 in order.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of recording image data for displaying a multi-gradation image on a liquid crystal display panel.

[0002]

2. Description of the Related Art Today, an image signal for displaying an image on a liquid crystal display panel or the like is an image signal having a brightness of 8 gradations or 16 gradations.
The image data converted into digital signals is 1
In the case of 6 gradation signals, 4-bit data is assigned to the image signal of 1 pixel. In order to cope with high-speed processing such as CRT, conventionally, when a dedicated V-RAM is used as a random access memory for video, it is unobtrusive, and in the case of 16 gradations, as shown in FIG. 1 random access memory (hereinafter referred to as RAM) as a set,
RAM21, 2nd RAM22, 3rd RAM23 and 4th
Signals are weighted in each RAM of the RAM 24, and 1
4 of the first RAM 21 to the fourth RAM 24 based on one address signal and a control signal such as a read / write signal.
4 RAMs for one pixel output from the central processing unit 10 (hereinafter referred to as CPU)
The image data of bytes is distributed by the decoder 33 from the first byte to the fourth byte to the first RAM 21 to the fourth RAM 24, and the image of 8 pixels is output in the state that the single address signal and the control signal are output. 1st RA data sequentially
The process of writing to each bit of M21 to the fourth RAM24, carrying up the contents of the address signal to the end of the ground and writing the image data of 8 pixels is repeated, and the image from the video RAM in which four RAMs are combined is repeated. Also in the case of reading the data, the image data of 8 pixels is output from the first RAM 21 by outputting the address signal and the control signal once.
To read from the fourth RAM 24, and control 32 lines.
The data output to the bus are combined by the multiplexer 34 into 4 bytes for 1 pixel, and the image data for 8 pixels is sequentially sent to the gradation data creating circuit 36. The change and control signals are output to read out the image data of 8 pixels, and the 4-bit data is sequentially sent to the gradation data forming circuit 36, and the gradation data forming circuit is further repeated. An image signal based on 4-bit image data is sent from the liquid crystal display panel 36 to a liquid crystal display panel control circuit 17 which is a control circuit of a liquid crystal display panel 19 (hereinafter referred to as LCD), and the video signal control circuit 17 has a driver built-in. The control unit 31 of the controller 30 and the liquid crystal display panel control circuit 17 communicate a control signal while displaying an image on the LCD 19 based on the image signal.

A video signal controller 30 for writing an image signal in the video RAM and for reading an image signal in this manner is used to write 4-bit image data controlled by the CPU 10. The access request for reading and the LCD panel control circuit 17 display the image on the LCD.
The control unit 31 adjusts and controls the read request of the image data to be displayed on the display unit 19, and the address designation circuit 32 receives the control signal from the control unit 31 at the timing when the address signal of the CPU 10 is allowed. The address signal of a specific address is passed through or independently output to the video RAM.

[0004]

As described above, four R's are used.
The video signal processing method for simultaneously accessing the AM requires a small number of input / output times of the address signal and the control signal necessary for processing a certain amount of data, and thus enables high-speed image processing. In case of 16 gradations for video, 4 RAMs are used.
A wide range is required as the area for mounting M,
Moreover, since the number of RAMs is large, power consumption is increased, and 8 sets of 4 are provided as a data bus from the video RAM.
That is, 32 lines are required, which makes it difficult to downsize the device.

Further, a dedicated V-RAM conventionally used as a video RAM is a mixed type of a dynamic RAM and a static RAM, which has a drawback that power consumption becomes large.

[0006]

According to the present invention, the data for one pixel in an image signal is composed of 4 bits, and the 4-bit data for one pixel is the upper 4 bits in one byte or Lower 4 bits, thus RA for video
Data for 2 pixels in 1 byte specified by address 1 of M
Data is to be written or read.

[0007]

[Operation] According to the present invention, the image data for one pixel is composed of a 4-byte signal, so that an image with 16 gradations can be displayed. Further, since the image data for one pixel is accessed to the video RAM as the upper 4 bits or the lower 4 bits of 1 byte at a specific address, the number of lines of the data bus can be 8 and the bit mask operation of the CPU can be performed. By CPU
It is possible to directly send and receive data between and the video RAM.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention, as shown in FIG.
10 and a read-only memory 12 (hereinafter referred to as ROM) in which various control programs are stored, and a RAM 1 that stores programs and various information to assist the work of the CPU 10.
4. Further, a video signal control circuit 25 which stores a video RAM 25 for storing image signals and a liquid crystal display panel control circuit 17 has a built-in gradation data generating circuit 36 for outputting 4-bit image data and control signals. It has a la 30.

In such a circuit configuration, the image data processed by the CPU 10 has 16 gradations and handles a signal for one pixel as a 4-bit signal.
When the image signal is stored in the video RAM 25 by U10, the 4-bit data for one pixel is stored in the CPU.
Within 10 bytes, the higher 4 bits data in 1 byte are used, and the next 1
The 4-bit data for pixels is set as the lower 4-bit data in 1 byte in the CPU 10, and 1-byte data for 2 pixels is first created. Then, an address signal is output from the CPU 10 to the address bus and 1 byte 2 Pixel data
The data is output to the data bus, and the write command is output to the control bus in response to the read / write signal to output the video R.
It is to be written in AM25.

The chip select control signal of the video RAM 25 is always sent to the video RAM during the operation of the device. The control signals such as address signals, data signals and read / write signals output from the CPU 10 are exchanged between the control unit 31 and the CPU 10 in the video signal controller 30 while the LCD 19 is being operated. Is adjusted by the control unit 31 at a timing that does not hinder the display control of the video R.
It is sent to the AM 25, and this embodiment uses the CPU 10.
RA for video specified by the address signal output by
The CPU 10 directly writes the image data of 2 pixels output to the data bus by the CPU 10 for each predetermined address of M25.

When the image data is read from the video RAM 25, the video signal controller 30 is used.
The address designation circuit 32 outputs the addresses in a predetermined order as address signals, reads the image data of 2 pixels into the video signal controller 30, and stores them in the two 8-bit registers 37 and 38. The data is temporarily stored and sequentially sent to the liquid crystal display panel control circuit 17 as 4-bit data having a predetermined weight in the gradation data creating circuit 36, and the liquid crystal display panel control circuit 17 is designated by the built-in driver. LCD
An image is displayed on the LCD 19 with each point of the LCD 19 having a predetermined brightness by making a predetermined position on the LCD 19 transparent for a predetermined time based on each gradation signal.

As described above, according to the present embodiment, the image data of 4 bits for one pixel is processed as the upper 4 bits or the lower 4 bits of 1 byte. Therefore, one address signal outputs 1 from the video RAM 25. Image processing of 2 pixels is possible with byte data, CPU 10 and video RAM
25, data can be directly communicated with the device 25, the device can be easily downsized, and the LCD 19 and other image signal storage media, and the CPU 10 to the video RAM 25.
There is an advantage that the control based on the priority order for accessing to is easy.

Further, in this embodiment, as compared with the conventional method of using four RAMs for outputting image data of 8 pixels for one address as video RAMs, the processing speed of the image signal is somewhat. Although it becomes slower, the processing speed can sufficiently correspond to the reaction speed of the LCD 19, and the normal static RAM can be used without using the dedicated video RAM, thereby reducing the power consumption.

Further, since 4-bit data is used as an image signal of 1 pixel, it is possible to display an image with 16 shades of gray in a single color and 4096 colors in the case of a color image. ..

[0015]

The image data processing method according to the present invention has four steps.
Since a bit signal is used as 1-pixel image data, a 16-gradation video signal can be used to display a natural image on the liquid crystal display panel. Since it is processed as 4 bits or lower 4 bits, it is possible to communicate with the central processing unit, the liquid crystal display panel control circuit, the video random access memory, etc. by the data bus of 8 lines, and the circuit configuration and timing control are easy. This is an image data processing method capable of assembling a control circuit suitable for a liquid crystal display panel which enables downsizing of the device and low power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an image data processing apparatus for carrying out a method according to the present invention.

FIG. 2 is a block diagram showing a main part of an example of a conventional image data processing device.

[Explanation of symbols]

10 Central processing unit 12 Read only memory for program 14 Random access memory for work 17 Liquid crystal display panel control circuit 19 Liquid crystal display panel 21, 22, 23, 24, 25 Video random access memory 30 Video signal controller 33 Dewar Da 34 Multiplexer 36 Grayscale data creation circuit

Claims (1)

[Claims] 1. Image data of 1 pixel is constituted by 4 bit data, and image data for 1 pixel is provided for each of upper 4 bits or lower 4 bits in 1 byte data at a predetermined address of a random access memory for video. A method of processing image data for a liquid crystal display panel, which comprises reading and writing data.