JPH05149990A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH05149990A
JPH05149990A JP3341723A JP34172391A JPH05149990A JP H05149990 A JPH05149990 A JP H05149990A JP 3341723 A JP3341723 A JP 3341723A JP 34172391 A JP34172391 A JP 34172391A JP H05149990 A JPH05149990 A JP H05149990A
Authority
JP
Japan
Prior art keywords
pattern
lands
cut
land
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3341723A
Other languages
Japanese (ja)
Inventor
Takeo Takahashi
威夫 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Canon Components Inc
Original Assignee
Canon Inc
Canon Components Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc, Canon Components Inc filed Critical Canon Inc
Priority to JP3341723A priority Critical patent/JPH05149990A/en
Publication of JPH05149990A publication Critical patent/JPH05149990A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits

Landscapes

  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To accurately and reliably inspect in a short time by cutting a part of a loop circuit of a circuit pattern in a manner to be easily connected. CONSTITUTION:A pattern 8 is provided to suppress influences of the signal delay at the farthest land 4 among lands 2, 3, 4 for input pins of signals sequentially connected by a land 1 at an output pin of signals and a pattern 7. The pattern is cut at an optional point of the pattern 8, and lands 5, 6 for through holes are provided at the confronting end points of the cut pattern. In the case, for example, where the pin is brought in touch with the lands 1 and 4 to conduct checking, it is possible to check even if either of the patterns 7 and 8 is opened. In other words, it is possible to detect an opening if the route of lands 5-1-2-3-4-6 is opened somewhere by bringing the pin in touch with the lands 5 and 6. After the inspection, the lands 5 and 6 are connected through a jumper wire.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電子機器等に用いるプリ
ント配線基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board used for electronic equipment and the like.

【0002】[0002]

【従来の技術】電子技術の発達に伴い、プリント配線基
板上に実装される電気回路の作動周波数が高くなり、信
号電送時間の遅れ、クロストークの発生、発生ノイズ等
の問題が顕在化してきており、これらを解決するため配
線パターンをループ状にする方法が考案されている。
2. Description of the Related Art With the development of electronic technology, the operating frequency of an electric circuit mounted on a printed wiring board becomes higher, and problems such as delay of signal transmission time, occurrence of crosstalk, and generated noise become apparent. In order to solve these problems, a method of forming a wiring pattern in a loop has been devised.

【0003】図4は信号遅延の防止のためのループ回路
の従来例を示す図、図5はクロストーク・ノイズの防止
のためのループ回路の従来例を示す図である。
FIG. 4 is a diagram showing a conventional example of a loop circuit for preventing signal delay, and FIG. 5 is a diagram showing a conventional example of a loop circuit for preventing crosstalk noise.

【0004】図4においては、4個のランド11,1
2,13,14がパターン17によって順次接続され、
また両端のランド11,14のみが他のパターン18に
よっても接続されており、これらパターン17,18に
よってループ回路が形成されている。これによってラン
ド11,14間の信号遅延が防止される。
In FIG. 4, four lands 11, 1 are provided.
2, 13, 14 are sequentially connected by the pattern 17,
Further, only the lands 11 and 14 at both ends are connected by another pattern 18, and the patterns 17 and 18 form a loop circuit. This prevents a signal delay between the lands 11 and 14.

【0005】図5においては、信号パターン20の周囲
にアースパターン21がループ回路として形成されてい
る。これによって信号パターン20への、または信号パ
ターン20からのクロストーク・ノイズが防止される。
In FIG. 5, a ground pattern 21 is formed as a loop circuit around the signal pattern 20. This prevents crosstalk noise to and from the signal pattern 20.

【0006】[0006]

【発明が解決しようとしている課題】従来、プリント配
線基板の製造工程における検査方法として、電気的に導
通検査を行うベアボードチェッカーや人手による目視検
査が知られているが、図4,図5に示すループ回路部に
ついてはループ部のオープン(切断)個所19がある場
合ベアボードチェッカーにては検出が不可能である。一
般にベアボードチェッカーの動作は、被検査パターンの
先端部、すなわち一本の線の場合その両端、T分岐の場
合3点の先端部に、ピンあるいは導電ゴム等で接触して
導通をとり、そのパターン自身のオープンおよび他のパ
ターンとのショート(短絡)を検出する。図4のような
回路の場合ランド11とランド14にピンを接触させる
ことになるが、オープン個所19が存在してもランド1
1−パターン18−ランド14の経路で電流が流れるた
めにオープンの検出ができない。したがってこのような
場合人間の目視検査にたよる以外方法がなく、短時間に
精度よく、また確実に検査することが困難であった。
Conventionally, a bare board checker for electrically conducting a continuity check and a visual inspection by a human are known as an inspection method in a manufacturing process of a printed wiring board. In the loop circuit section, if there is an open (cut) point 19 in the loop section, the bare board checker cannot detect it. In general, the operation of the bare board checker is conducted by contacting the tip end of the pattern to be inspected, that is, both ends in the case of a single line, and the tip ends of three points in the case of T-branch with a pin or a conductive rubber to conduct the pattern. Detects its own open and short circuit with other patterns. In the case of the circuit as shown in FIG. 4, the pins are brought into contact with the land 11 and the land 14, but even if the open portion 19 exists, the land 1
Opening cannot be detected because current flows in the path of 1-pattern 18-land 14. Therefore, in such a case, there is no method other than relying on a human visual inspection, and it is difficult to perform an accurate and reliable inspection in a short time.

【0007】本発明の目的は、ループ回路があってもオ
ープン(切断)を短時間に精度よく、また確実に検査で
きるプリント配線基板を提供することにある。
It is an object of the present invention to provide a printed wiring board which can accurately and reliably inspect open (cut) in a short time even if there is a loop circuit.

【0008】[0008]

【課題を解決するための手段】本発明のプリント配線基
板は、絶縁基板上に任意に形成された回路パターンの一
部が、電気的にループ回路を形成しているプリント配線
基板において、前記ループ回路の一部が容易に接続でき
るように切断された形状となっていることを特徴とす
る。
A printed wiring board according to the present invention is a printed wiring board in which a part of a circuit pattern arbitrarily formed on an insulating substrate electrically forms a loop circuit. It is characterized in that a part of the circuit is cut so that it can be easily connected.

【0009】[0009]

【作用】本発明によれば、ループ内の任意の個所が予め
切断された状態でプリント配線基板を製造し、互いに対
峙した2点の切断点を利用してベアボードチェッカー等
でプリント配線基板が良品であることを確認し、その後
前記2点を接続して使用することにより、最初に設計し
た通りの電気的に優れたプリント配線基板を製造するこ
とができるようにしたものである。
According to the present invention, a printed wiring board is manufactured in a state where any portion in the loop is cut in advance, and the printed wiring board is a non-defective product by a bare board checker or the like using two cut points facing each other. It is possible to manufacture an electrically excellent printed wiring board as originally designed, by confirming that, and then connecting and using the two points.

【0010】[0010]

【実施例】図1は本発明の一実施例を示す図である。FIG. 1 is a diagram showing an embodiment of the present invention.

【0011】信号の出力ピンに設けられたランド1とパ
ターン7によって順次接続された信号の入力ピン用に設
けたランド2,3,4のうち最遠点にあるランド4にお
ける信号遅延の影響を抑止するために設けたパターン8
の任意の点でパターンを切断しその対峙する端点にスル
ーホールのランド5,6を設けてある。
Of the lands 2, 3 and 4 provided for the signal input pins which are sequentially connected by the pattern 1 and the land 1 provided to the signal output pin, the influence of the signal delay on the land 4 at the farthest point is considered. Pattern 8 provided to suppress
The pattern is cut at an arbitrary point, and through-hole lands 5 and 6 are provided at the opposing end points.

【0012】図2は本実施例の基となったロジック回路
の配線図である。
FIG. 2 is a wiring diagram of the logic circuit which is the basis of this embodiment.

【0013】本実施例によれば、例えばランド1,4に
ピンを接触しチェックをした場合、パターン7または8
のどちらか片方がオープンしていても検出できる。すな
わち、ランド5および6にピンを接触しチェックするこ
とにより、ランド5−1−2−3−4−6の経路のうち
どこかにオープン個所があれば検出することができる。
検査終了後はランド5,6間をジャンパー線で接続す
る。
According to the present embodiment, for example, when the pins are brought into contact with the lands 1 and 4 for checking, patterns 7 or 8
Can be detected even if either one of them is open. That is, by contacting the pins with the lands 5 and 6 and checking them, it is possible to detect if there is an open portion somewhere in the route of the land 5-1-2-3-4-6.
After the inspection is completed, connect lands 5 and 6 with jumper wires.

【0014】前述の実施例では予め作った切断点をジャ
ンパー線で接続することになっているが、部品実装時確
実に、安価に接続することができれば何でもよく、例え
ば、図3(a)に示すように、切断したパターンの対峙
する端点と幅広部5a,6aとしたり、図3(b)に示
すように、凹部を形成した幅広部5bおよび凸部を形成
した幅広部6bを対峙させるようにしてもよい。あるい
は、抵抗がほぼゼロのリード部品やチップ部品、ショー
ト回路を組み込んだIC等を実装する方法、半田付によ
って接続する方法等も考えられる。
In the above-described embodiment, the cutting points made in advance are connected by jumper wires, but any connection can be made as long as reliable and inexpensive connection can be made at the time of mounting the parts. For example, as shown in FIG. As shown, the end points of the cut pattern and the wide portions 5a and 6a are opposed to each other, or, as shown in FIG. 3B, the wide portion 5b having the concave portion and the wide portion 6b having the convex portion are opposed to each other. You can Alternatively, a method of mounting a lead component or a chip component having almost zero resistance, an IC having a short circuit incorporated therein, a method of connecting by soldering, or the like can be considered.

【0015】また、配線パターンがループ状になってい
ない場合でも、その経路が長かったり、隣接パターンと
接近したりしていて、そのパターンを切断しておき、チ
ェックをした方がよい場合もあり、この技術を応用する
ことができる。
In addition, even if the wiring pattern is not in a loop shape, the route may be long or may be close to an adjacent pattern, and it may be better to cut the pattern and check it. , This technology can be applied.

【0016】[0016]

【発明の効果】本発明はループ回路の一部を切断した状
態にしておくことにより、ループ回路の切断検査を短時
間に精度よく、また確実に行うことができるので、品質
のよいプリント配線基板を製造することができる。
As described above, according to the present invention, the cut inspection of the loop circuit can be performed accurately and surely in a short time by keeping a part of the loop circuit cut. Can be manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す図である。FIG. 1 is a diagram showing an embodiment of the present invention.

【図2】図1の実施例の基となったロジック回路の配線
図である。
FIG. 2 is a wiring diagram of a logic circuit on which the embodiment of FIG. 1 is based.

【図3】(a),(b)はそれぞれ切断部分のパターン
形状の例を示す図である。
3A and 3B are diagrams showing examples of the pattern shape of a cut portion.

【図4】従来例を示す図である。FIG. 4 is a diagram showing a conventional example.

【図5】従来例を示す図である。FIG. 5 is a diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

1 信号出力用のランド 2,3,4 入力信号用のランド 5,6 切断点のランド 5a,5b,6a,6b 幅広部 7,8 パターン 1 Land for signal output 2, 3, 4 Land for input signal 5, 6 Land for cutting point 5a, 5b, 6a, 6b Wide part 7, 8 patterns

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板上に任意に形成された回路パタ
ーンの一部が、電気的にループ回路を形成しているプリ
ント配線基板において、 前記ループ回路の一部が容易に接続できるように切断さ
れた形状となっていることを特徴とするプリント配線基
板。
1. In a printed wiring board in which a part of a circuit pattern arbitrarily formed on an insulating substrate electrically forms a loop circuit, the part of the loop circuit is cut so that it can be easily connected. A printed wiring board, which has a formed shape.
JP3341723A 1991-12-02 1991-12-02 Printed wiring board Pending JPH05149990A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3341723A JPH05149990A (en) 1991-12-02 1991-12-02 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3341723A JPH05149990A (en) 1991-12-02 1991-12-02 Printed wiring board

Publications (1)

Publication Number Publication Date
JPH05149990A true JPH05149990A (en) 1993-06-15

Family

ID=18348280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3341723A Pending JPH05149990A (en) 1991-12-02 1991-12-02 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH05149990A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003044807A (en) * 2001-07-30 2003-02-14 Toppan Printing Co Ltd Non-contact ic card, inlet for non-contact ic card, and method for inspecting the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003044807A (en) * 2001-07-30 2003-02-14 Toppan Printing Co Ltd Non-contact ic card, inlet for non-contact ic card, and method for inspecting the same

Similar Documents

Publication Publication Date Title
US6462570B1 (en) Breakout board using blind vias to eliminate stubs
US7492146B2 (en) Impedance controlled via structure
US20080217052A1 (en) Wiring board and method of manufacturing wiring board
US6798212B2 (en) Time domain reflectometer probe having a built-in reference ground point
US5263240A (en) Method of manufacturing printed wiring boards for motors
US6867597B2 (en) Method and apparatus for finding a fault in a signal path on a printed circuit board
JP3842050B2 (en) Press-fit pin connection inspection method and system
JPH05149990A (en) Printed wiring board
CN110557882B (en) Circuit board for transmitting and testing high-speed signal
JPH02237091A (en) Printed wiring board
CN215676855U (en) Back drilling depth test module and PCB
JPH06260799A (en) Circuit board inspecting method, and circuit board
JP2002299805A (en) Method of checking circuit board and mounting position
JP2000100504A (en) Connector and printed wiring board
JPH0563327A (en) Printed wiring board with land for inspection use and inspecting method thereof
JPH05322955A (en) Inspection method of printed wiring board
JPS6171371A (en) Inspection of pattern of electric conductor
CN114449728A (en) PCB easy to test and electronic equipment
JP2000506303A (en) Method for manufacturing connection portion of data transmission line, and plug connector
JPS62130364A (en) Inspecting method for printed wiring board
JPH1117291A (en) Printed wiring board
JPH03244142A (en) Method of testing semiconductor device
JP2001230543A (en) Printed wiring board
JPH0572296A (en) Semiconductor integrated circuit
JPH0621180A (en) Inspecting method for misregistration of solder-resist layer of printed wiring board