JPH05145765A - Image encoding/decoding device - Google Patents

Abstract

PURPOSE:To partially curtail an address generator circuit corresponding to a multiplier, a buffer memory, or a butterfly arithmetic output by executing simultaneously a discrete cosine convertion (DCT) processing ad a scalar quantization (SO) processing. CONSTITUTION:When an $0 coefficient setting mode signal is in an enable state, each coefficient is written in a DCT & SQ coefficient table 6, and write is inhibited in a disenable state. An SO coefficient value to be written is inputted to a DCT+SO part 5 through a selector 2. Simultaneously. the corresponding DCT coefficient is also inputted through a selector 1. Effective DCT and SO coefficients are calculated from them, and written in the table 6 through a gate 7. Also, those coefficients are given to the part 3 through the selectors 4, 2. when loading of all SO coefficients is finished, they become a disenable state. When the DCT and the SO coefficients a multiplied from the DCT coefficient ad the loading SO coefficient, an increase of a circuit scale is prevented by using the multiplier at the time of data processing, and also, the SO processing multiplier is curtailed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for encoding and decoding multi-valued data such as halftone and color images.

[0002]

2. Description of the Related Art JPEG jointly used by CCITT and ISO for encoding and decoding halftone and color images
(Joint Photographic Experts Group) ADCT (Ad
aptiveDiscrete Cosign Transform) is known.

The processing function block inside this JPEG is
As shown in FIG. 4, the Discrete Cosign transform
A transform (hereinafter abbreviated as DCT) unit 11, a scalar quantization (hereinafter abbreviated as SQ) unit 12, and a variable length coding unit 12 such as Huffman coding are roughly composed of three processing blocks. Then, in the SQ unit 12,
An SQ coefficient table 14 storing SQ coefficients for performing SQ calculation is provided, and a Huffman code table 15 is provided in the variable length coding unit 13.

By the way, in the orthogonal transform coding method such as DCT, the target image signal is divided into blocks, the frequency component of the image signal of each block is obtained, and only the main frequency component is encoded. The data is compressed by.

The calculation of the DCT process is performed by the calculation formula shown in the following formula 1.

[0006]

[Equation 1]

In order to process this DCT processing at high speed, a plurality of multipliers are required, and also a multiplier and a divider are required in the SQ section.

As a technique for reducing the number of multipliers used,
As shown in Equation 1, there is a butterfly method (Forward DCT) for high-speed DCT calculation.

FIG. 5 shows a circuit block diagram in which general DCT processing and SQ processing are performed by separate multipliers.

The SQ coefficient is given to the gate 21, and this SQ coefficient is
The Q coefficient is written in the SQ coefficient table 22 according to the SQ coefficient setting mode control signal supplied to the gate 21.

The SQ coefficient written in the SQ coefficient table 22 is given to the division ROM 23 and the selector 24. An output from the division ROM 23 is given to the selector 24.

On the other hand, the block image read by an image reading unit (not shown) is given to the DCT unit 20 in a block unit of 8 pixels × 8 pixels, and the DCT coefficient and the block given to the DCT unit 20. The image and the image are subjected to DCT processing using a built-in multiplier. And D
The calculation result of the CT processing is written in the DCT calculation result toggle buffer memory 25. When the processing for one block is completed, the DCT operation result toggle buffer memory 25
From the DCT calculation result is given to the SQ processing unit 26. S
The SQ coefficient value is given to the Q processing unit 26, and the SQ processing unit 2
At 6, the calculation is performed with the corresponding SQ coefficient value in the 8 pixel × 8 pixel block, and the SQ processing result is output.

The encoding process in this circuit will be described. First, when loading the SQ coefficient, the SQ coefficient is input to the gate 21 and written in the SQ coefficient table 22. At the time of data encoding processing, the block image read out from the image reading unit is input in a block unit composed of 8 pixels × 8 pixels, and the image data and the DCT coefficient are stored in a built-in multiplier in the DCT unit 20. It is used to perform DCT processing and write it to the DCT operation result toggle buffer memory 25. When the processing for one block is completed, the DCT calculation result toggle buffer memory 25 outputs the DCT calculation result and 8 pixels x
An operation is performed with the corresponding SQ coefficient in the 8-pixel block to obtain the SQ processing result.

Regarding the relationship between the number of multipliers and the processing time chart at this time, a time chart when DCT processing and SQ processing are performed by one multiplier is shown in FIG. Figure 2 shows the time chart when used
It shows in (c). This obviously allows one multiplier to
Performing CT processing and SQ processing alternately is inefficient in processing performance. Therefore, in order to increase the throughput of DCT processing and SQ processing, separate multipliers are required.

When the butterfly method for high-speed DCT calculation shown in Equation 1 is used, it is possible to reduce the number of multipliers in the DCT processing section, but the algorithm outputs the DCT processing result in a special sequence. It In order to deal with this, the SQ processing unit has an address generator circuit of the same sequence, or
It is necessary to have an 8 pixel × 8 pixel RAM in the toggle configuration as an intermediate data buffer as shown in FIG.

[0016]

As described above, in order to realize this encoding / decoding system, many multipliers and buffer RAMs and circuits such as an address generator corresponding to the output of the butterfly operation shown in FIG. 3 are used. It had the drawback of needing it.

The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide an image coding / decoding device having a simple circuit configuration and improved processing performance.

[0018]

The present invention is used in DCT processing by using a multiplier used in data coding and decoding processing when writing or reading SQ coefficients used in the SQ processing section. DCT coefficient and S
DCT of the SQ coefficient used in the Q processing unit in real time
And a means for calculating the SQ coefficient, a means for writing to the DCT and SQ coefficient table, and a means for reading from the DCT and SQ coefficient table.

[0019]

In the present invention, the DCT process and the SQ process are simultaneously performed, so that the multiplier and the buffer memory or a part of the address generator circuit corresponding to the butterfly operation output can be deleted, and the processing performance can be improved by the reduction. It becomes possible to do.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of an encoding device to which the present invention is applied. FIG. 1 is a block diagram of a circuit that simultaneously performs DCT processing and SQ processing with one multiplier.

In the present invention, the DCT and SQ coefficient table 6 includes the DC calculated by the DCT and SQ processing circuit 3.
The T and SQ coefficients are written via gate 7. Further, the gate 7 is controlled by the SQ coefficient setting mode signal. That is, when the SQ coefficient setting mode signal is enabled, each coefficient is written in the DCT and SQ coefficient table 6, and when the SQ coefficient setting mode signal is disabled, writing is prohibited.

The SQ coefficient value to be written is input to the DCT and SQ processing section 3 via the selector 2.

Corresponding DCT coefficients are simultaneously input to the DCT and SQ processing section 3 via the selector 1. The DCT and SQ coefficients effective in the present invention are calculated from the two input data by using the internal multiplier of the DCT and SQ processing unit 3. The calculation method is step 3 in FIG.
Between DCT and F (u) 4 (C1, C2, C3, C
4, C5, C7) and the coefficient are multiplied or divided. This calculated data is written in the DCT and coefficient table 6 through the gate 7. From the DCT and coefficient table 6, the DCT and SQ coefficients calculated through the selector 4 are input to the DCT and SQ processing unit 3 through the selector 2. Further, the calculated DCT and SQ coefficients are RO for division.
The data from the ROM 5 is supplied to the M5 and is input to the DCT and SQ processing unit 3 via the selector 4 and the selector 2.

SQ for loading the above processing in real time
Do this for each coefficient. SQ when all SQ coefficients are loaded
The coefficient setting mode signal is disabled.

Next, the processing for writing the SQ coefficient at the time of encoding in this embodiment will be described. First, SQ
Enable the coefficient setting mode signal. Next, the SQ coefficient value to be written is input and the DCT is input via the selector 2.
And SQ processing section.

At the same time, the corresponding DCT coefficient is also input.
The DCT and SQ coefficients are calculated from the two input data by using the internal multiplier of the DCT and SQ processing unit 3. This calculated data is written in the DCT and coefficient table 6 through the gate 7. This process is performed for each SQ coefficient to be loaded in real time, and when the loading of all SQ coefficients is completed, the SQ coefficient setting mode signal is disabled.

After the encoding is started, the DC is calculated according to the Bataray operation algorithm based on the calculation formula shown in the equation 1.
The DCT and SQ processing can be performed by performing only the DCT processing sequence in the T and SQ processing unit 3.

In the embodiment of FIG. 1, in order to perform the DCT process and the SQ process at the same time, when the SQ coefficient value is loaded in advance, the DCT and the SQ coefficient value are calculated from the SQ coefficient value and the DCT coefficient value, and the DCT And by adding a means for loading to the SQ coefficient table, the DCT processing and the SQ processing can be performed instead of the conventional means for performing the SQ processing after the DCT processing.
It is possible to perform the processing in the same cycle. Figure 2
A time chart of this processing is shown in (a). Figure 2
In each of the configurations (a), (b) and (c), 3
Output timings of DCT and SQ processing of one block are shown in (S), (A), (B), and (C). (S) is the start of block input. The output timing in the present invention is (C) when the common multipliers of (A) and (b) are used, and (B) when the different multipliers of (c) are used.
Is.

As described above, the DCT coefficient and the SQ to be loaded
By using a multiplier for calculating DCT and SQ coefficients from coefficients, which is used during data processing,
It is configured to prevent an increase in circuit scale. This allows S
It is possible to reduce the number of multipliers for Q processing.

Further, in the present invention, a buffer memory (register) of 8 pixels × 8 pixels × 11 bits, which is necessary when the butterfly method of the calculation formula shown in Formula 1 is used.
Alternatively, it is possible to reduce the number of special address generator circuits, and as shown in the time chart of FIG. 2, there is no delay in processing due to buffer control as compared with FIGS. 5 and 6.

[0031]

As described above, according to the present invention, it is possible to reduce the number of multipliers and the number of buffer RAMs or special address generators by adopting a configuration in which DCT processing and SQ processing are performed in the same manner. Moreover, the processing performance is improved by the reduction.

Furthermore, when an image coding / decoding device or LSI is realized by using the present invention, it is possible to improve the reliability by downsizing the device, reducing complexity, and reducing the number of parts.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart when the circuit configuration according to the present invention is used, a common multiplier is used, and various multipliers are used.

FIG. 3 is an explanatory diagram illustrating a butterfly operation method of DCT processing.

FIG. 4 is a general block diagram of an ADCT encoding system.

FIG. 5 is a general block configuration diagram of a conventional ADCT encoding system.

[Explanation of symbols]

 3 DCT and SQ processing unit 6 DCT and SQ coefficient table 7 Gate

Claims (1)

[Claims] 1. A device for performing encoding and decoding of a black and white intermediate image and a color image, means for reading an image signal composed of a plurality of pixels in block units, and orthogonal transformation for the read image signals in block units. Transform means for performing, means for quantizing the transform coefficient subjected to the orthogonal transform, means for computing the quantized coefficient to be loaded and orthogonal transform coefficient, and means for writing and reading the computed coefficient to and from the table memory. , When writing or reading the coefficient, the multiplier used in the data encoding / decoding process is used to obtain the orthogonal transform coefficient used in the orthogonal transform process and the quantized coefficient used in the quantization processing unit in real time. An image code characterized by calculating orthogonal transformation coefficients and quantized coefficients and writing or reading the calculated coefficients in a coefficient table. Device.