JPH05145518A - Data demodulator - Google Patents

Abstract

PURPOSE:To obtain a data demodulator in which no bit inversion is caused to demodulated data in a spread spectrum communication. CONSTITUTION:An SS-CSK signal is multiplied with COSomegat and SINomegat by multipliers 12, 13 and COS component data and SIN component data are inputted respectively to 1st and 2nd digital correlation sections 16, 17. A PN code pattern corresponding to data '1' or '0' is set as reference data without bit inversion at a 1st correlation section 16. Moreover, the PN code pattern is set as reference data subjected to bit inversion by a 2nd correlation section 17. The output of each correlation section is compared respectively with a threshold level at comparators 27, 28 and the obtained comparison outputs are added and the result becomes demodulated data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data demodulating apparatus suitable for spread spectrum communication system, and more particularly to asynchronous SS-CSK (Code Shift Keying) communication using a digital correlator. SS-
Carrier phase of CSK signal and COS wave and SIN on receiving side
The present invention relates to an improved data demodulating device for avoiding bit inversion of demodulated data due to wave phase uncertainty.

[0002]

2. Description of the Related Art SS-CSK using a digital correlator
A signal asynchronous demodulator is shown in FIG. In the figure, 1
And 2 are A / D converters, 3 and 4 are digital correlators,
Reference numerals 5 and 6 are multipliers, and 7 is an adder.

FIG. 5 shows the basic circuit configuration of the digital correlator shown in FIG. In the figure, S and R are registers, ADD is an adder, and Ex-NOR ₁ to _N are exclusive OR gates.

In FIG. 5, N-bit reference data is serially loaded in an N-bit register R in synchronization with a clock RCL. The information data is N
The bit register S is serially loaded in synchronization with the clock SCL. Then, the coincidence / non-coincidence of the contents of the respective registers is detected by the respective exclusive OR gates Ex-NOR ₁ to _N , and the total of the respective coincident detection outputs is added by the adder A.
Output data obtained by DD is obtained.

The operation of the asynchronous demodulator of the SS-CSK signal shown in FIG. 4 using the digital correlator will be described below. The received SS-CSK signal r (t) can be expressed as in Equation 1.

[0006]

[Equation 1]

In the apparatus of FIG. 4, as shown in FIG.
The correlation values of the COS component and the SIN component are obtained by multiplying COSωt and SINωt equal to the modulation carrier frequency of the CSK signal and the SS-CSK signal by the multipliers 5 and 6, and the A / D converters 1 and 2 perform A / D conversion. After doing
Data demodulation is performed by performing baseband processing. That is, the correlation values of the digital data of the COS component and the SIN component are, for example, by the digital correlators 3 and 4 in which the reference data equal to the result of the exclusive OR of the data “1” at the time of transmission and the PN code is set. Desired. Then, data demodulation is performed based on the value obtained by adding the correlation value by the adder 7.

[0008]

However, the received SS
-Since the carrier phase of the CSK signal and the phase relationship between COS ωt and SIN ωt on the receiving side are uncertain, the received S
In the range in which the phase shifts of COSωt and SINωt with respect to the S-CSK signal are delayed by π / 2 to π [radian], they behave apparently as COSωt → SINωt to −COSωt SINωt → −COSωt to −SINωt. As a result, bit inversion occurs in the demodulated data, and what was originally "1" data is now
There is a problem that the data changes to "0".

An object of the present invention is to provide a data demodulating apparatus suitable for spread spectrum communication in which demodulated data does not cause bit inversion.

[0010]

In order to achieve the above object, the first invention of the present application has a digital correlator corresponding to COS component data and a digital correlator corresponding to SIN component data. The correlator does not bit-invert the PN code pattern corresponding to the data 1 or 0, and the first digital correlator set as the reference data, the digital correlator corresponding to the COS component data, and the S
A digital correlator corresponding to IN component data,
A second correlator that compares the outputs of the second digital correlator set as reference data in which each correlator bit-inverts the PN code pattern and the first and second digital correlator with a predetermined threshold value. The gist of the invention is that it comprises first and second comparing means, and means for adding the outputs of the first and second comparing means. A second invention of the present application is a digital correlator corresponding to COS component data and an S
A digital correlator corresponding to IN component data, each correlator does not bit-invert the PN code pattern corresponding to data 1 or 0, or a digital correlator set as bit-inverted reference data; Bit inversion means for generating data in which the partial output is bit-inverted, output of the digital correlation section, and output of the bit inversion means are respectively compared with predetermined threshold values.
And the means for adding the outputs of the first and second comparing means.

[0011]

Since the data demodulating device of the present invention is configured as described above, data can be obtained even in the state where the carrier phase of the received signal and the phases of the COS wave and the SIN wave on the receiving side are uncertain and bit inversion occurs. It can be demodulated normally.

[0012]

Embodiments of the present invention shown in the drawings will be described below.
FIG. 1 shows an embodiment of a digital demodulation unit according to the present invention. In the figure (a), 10 is an oscillator of COSωt,
11 is a P + π / 2 phase shifter, 12 and 13 are multipliers, 1
4 and 15 are A / D converters, 16 and 17 are first and second digital correlation units, 18 is an addition unit, 19 is a comparison unit,
20 is an OR circuit. The first and second digital correlators 16 and 17 are composed of digital correlators 21, 22, 23 and 24, respectively, as shown in FIG. 1B, and the adder 18 includes adders 25 and 26. The comparison unit 19 includes comparators 27 and 28.

In FIG. 1 (a), COSωt and SI
Nωt is generated and input to the multipliers 12 and 13, respectively. Then, the correlation value between the SS-CSK signal received by the multipliers 12 and 13 and COSωt and SINωt is obtained, and the data of the COS component and the SIN component converted into digital data by the A / D converters 14 and 15 are: First and second digital correlator 16, respectively
17 is input.

It is assumed that the pattern of the PN code 1 corresponding to the data "1" is set as the reference data in the digital correlation units 16 and 17, for example. As the PN code, for example, an m-sequence code is used. Received SS-CSK signal and COSω
If the phase relationship between t and SINωt does not cause bit inversion, the output of the digital correlator is as shown in FIG.
As shown in, and if bit inversion occurs,
It becomes as shown in FIG.

When data is demodulated by comparing the output of the digital correlator with a threshold value, the data cannot be demodulated normally when bit inversion occurs as shown in FIG. 2 (b). Therefore, since the data is normally demodulated even in the state where the bit inversion occurs, as shown in FIG.
The digital correlator 21 and the digital correlator 22 in which the reference data PN in which the pattern of the code 1 is not bit-inverted are set, and the correlator 23 and the digital correlator 2 in which the reference data bar PN in which the bit is inverted is set.
The A / D-converted data of the COS component and the SIN component is input to 4.

Then, the digital correlation unit 2 of FIG.
1 and the output of the digital correlator 22 and the outputs of 23 and 24 are added by the adders 25 and 26, and the threshold value and the comparator 2 are respectively added.
7 and 28 are compared, respective comparison outputs are added by the OR circuit OR, and data demodulation is performed.

When a pure binary number is used as the format of the output data of the digital correlator, the code chip numbers N and -N shown in FIG. 2 are, for example, in the case of N = 31 m sequence code, N ... 31-N ... 0.

Therefore, in order to simplify the structure for performing the data demodulation, as shown in FIG. 3, the digital correlation unit 17 of FIG. Each of the bit-inverted data generated by 29 may be compared with a threshold value by the comparators 27 and 28 to perform data demodulation.
Of course, conversely, the digital correlator 16 may be deleted and the output of 17 may be used.

[0019]

As described above, according to the present invention, the bit inversion state of demodulated data that occurs when asynchronously demodulating an SS-CSK signal using a digital correlator is avoided and data demodulation is performed normally. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the above embodiment.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional data demodulation device.

FIG. 5 is a block diagram showing a configuration of a digital correlator.

FIG. 6 is an operation explanatory diagram of the apparatus of FIG.

[Explanation of symbols]

 16, 17 Digital correlation section 19 Comparison section

Claims (2)

[Claims] 1. A digital correlator corresponding to COS component data and a digital correlator corresponding to SIN component data, each correlator corresponding to data 1 or 0.
A first digital correlator set as reference data without bit inversion of the N code pattern, a digital correlator corresponding to COS component data, and a SIN
A digital correlator corresponding to component data, each correlator being set as reference data in which the PN code pattern is bit-inverted, and the first and second digital correlator. A data demodulating device, comprising: first and second comparing means for comparing the outputs of the above with respective predetermined threshold values, and means for adding the outputs of the first and second comparing means. 2. A PN having a digital correlator corresponding to COS component data and a digital correlator corresponding to SIN component data, each correlator corresponding to data 1 or 0.
A digital correlator that does not bit-invert the code pattern or is set as bit-inverted reference data, a bit invertor that generates data that is bit-inverted from the output of the correlator, an output of the digital correlator, and a bit invertor A data demodulating device comprising: first and second comparing means for respectively comparing the outputs of the above with respective predetermined threshold values, and means for adding the outputs of the first and second comparing means.