JPH05145174A - Manufacture of semiconductor light emitting element - Google Patents

Abstract

PURPOSE:To reduce leakage current by forming a current blocking layer and semiconductor layers for double heterostructure on a substrate having a mesa stripe formed. CONSTITUTION:After a mesa stripe 57 having a dielectric mask 35 is formed on a p-type InP substrate 31 by photolithography and etching, an n-type InP current blocking layer 41 and a p-type InP current blocking layer 43 are formed by selective crystal growth. Following this, semiconductor layers for double heterostructure, namely, a p-type InP clad layer 49, a p-type InGaAsP activated layer 47, an n-type InP clad layer Lye, and an n-type InGaAsP electrode layer (a contact layer) 51 are crystal-grown in this order by a second crystal growth. Consequently, leak current can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor light emitting device.

[0002]

2. Description of the Related Art Semiconductor light emitting devices are widely used for long-distance optical communication and optical measuring instruments. Such a semiconductor light emitting device can oscillate at a low threshold current and can operate at a high output,
In addition, characteristics such as stable oscillation in the transverse mode are required.

Conventionally, as a semiconductor light emitting device of this type, for example, documents (IEEE Journal of Quantum Electronics (IEEE, JQE), Vo
l. QE-21, No. 5 (pages 452 to 457), 19
There was one disclosed in May 1985). this is,
On a p-type InP substrate as a base made of a compound semiconductor, a mesa-shaped section and a p-type InP clad layer, InG
It had a stripe-shaped double heterostructure portion including an aAsP active layer and an n-type InP clad layer, and a current confinement layer to embed the double heterostructure portion.

A method of manufacturing the semiconductor light emitting device will be described below with reference to FIGS. 5A to 5C, which are manufacturing process diagrams, and FIGS. 6A and 6B. In addition,
Both figures are sectional views of the device taken along a direction orthogonal to the laser stripe.

First, on the p-type InP substrate 11, p-type In
P layer 13, InGaAsP layer 15 and n-type InP layer 1
7 is formed in this order by the crystal growth method. Next, a stripe-shaped mask 19 made of SiO ₂ is formed on the n-type InP layer 17 (see FIG. 5A). It should be noted that this figure shows two of the many elements formed on the substrate 11 (the same applies up to FIG. 6A below). Next, these semiconductor layers are etched off from above the portion of the n-type InP layer 17 exposed from the mask 19 to the substrate 11 to form a mesa stripe 21 (see FIG. 5B).

Next, only on the substrate portion exposed by the above-described etch-off, that is, on the substrate 11, the mesa stripe 2 is formed.
The n-type InP layer 23 and the p-type InP layer 25 serving as current blocking layers are crystal-grown on the portions corresponding to both sides of 1 by selective crystal growth (see FIG. 5C).

Next, the n-side electrode 27 is formed on the front surface side of the substrate 11.
However, p-type electrodes are respectively formed on the back surface of the substrate 11 (FIG. 6A). After that, a predetermined portion (I- in FIG. 6A)
Element isolation is performed by (I line) to obtain individual light emitting elements (FIG. 6B).

In this semiconductor light emitting device, the injected current is applied to the p-type InP substrate 1 at the portion of the mesa stripe 21.
1-p type InP clad layer 13-InGaAaP active layer 15-n type InP clad layer 17 flows in this order. on the other hand,
Other than the mesa stripe 21, the p-type InP substrate 11-n
The current does not flow because the p-type InP current blocking layer 23 becomes the p-type InP current blocking layer 25 and the n-type InP current blocking layer 23 and the p-type InP current blocking layer 25 are reverse biased. That is, the injected current is concentrated only on the mesa stripes 21 having the active layer 15, so that the threshold current can be reduced and the luminous efficiency can be improved.

[0009]

However, in the above-described conventional manufacturing method, when the n-type InP current blocking layer 23 is grown, the layer 23 may rise up to the upper portion of the mesa stripe 21. It was Therefore, n
Type InP upper cladding layer 17 and n type InP current blocking layer 2
Since the structure is in contact with 3, there is a problem that the cause of the leak current is inherent. In order to obtain a predetermined breakdown voltage in the semiconductor light emitting device, the current blocking layer needs to have a certain thickness, so that the rise is likely to occur.

A method of increasing the height of the mesa stripe 21 can be considered in order to prevent such rising. However, in that case, the width W (see FIG. 6B) of the mesa stripe becomes wide due to the relationship of the aspect ratio (actually, W in the above document was about 4 μm), and as a result, the radiation beam pattern was high. There is a drawback that it becomes the next mode.

The present invention has been made in view of the above problems, and therefore, the object of the present invention is to solve the above problems in manufacturing an internal current constriction type semiconductor light emitting device on a base made of a compound semiconductor. It is to provide a manufacturing method which can be solved.

[0012]

In order to achieve this object, according to the present invention, an underlayer made of a compound semiconductor,
A method of manufacturing an internal current confinement type semiconductor light emitting device, comprising: (a) a step of forming a mask made of a dielectric material in a predetermined shape on a base, and (b) being covered with the mask of the base. Forming a mesa-shaped portion on the underlying portion, (c) growing an internal current confinement layer composed of at least two current blocking layers having different conductivity types on the base on which the mesa-shaped portion is formed, and (d) Removing the mask from the underlying layer on which the internal current constriction layer has been grown, and then forming each semiconductor layer for the double hetero structure on the underlying layer.

The term "underlayer" as used in the present invention refers to a compound semiconductor substrate itself, a laminated body composed of a compound semiconductor substrate and a buffer layer, and the like. However, it is better to have a buffer layer in consideration of crystal quality and the like.

A SiO ₂ thin film is preferably used as a mask made of a dielectric material. However, any other suitable thin film may be used as long as it is not attacked by the etching solution and the current blocking layer does not grow. Further, the mask having a predetermined shape refers to a mask having a plane shape that substantially corresponds to the laser stripe.

The semiconductor layers for the double hetero structure referred to in the present invention refer to at least the lower clad layer semiconductor layer, the active layer semiconductor layer and the upper clad layer semiconductor layer. Of course, in each semiconductor layer for the double hetero structure,
In addition to the three types of semiconductor layers, various other semiconductor layers added according to the type of the semiconductor light emitting device (for example, a diffraction grating is applied when the present invention is applied to a DFB type semiconductor light emitting device). Optical waveguide layer) is also included.

[0016]

According to the structure of the present invention, the width is 1 to 1.5 μm and the height is n on the p-type InP substrate by photolithography and etching before forming the double hetero structure.
After forming a mesa stripe having a dielectric mask on the surface and having a mesa stripe that is as thick as or higher than the thickness of the InP current blocking layer, n-type I is formed by selective crystal growth.
The nP current blocking layer and the p-type InP current blocking layer are crystal-grown. After that, a double hetero structure is formed by the second crystal growth. The mesa stripe part made on the base is
The upper clad layer and the current blocking layer of the same conductivity type as the upper clad layer are separated from each other by the height of the mesa stripe as compared with the conventional case. Also, the dielectric mask prevents the current blocking layer from growing on the underlying mesa stripe portion. As a result, the active layer width is narrow and the n-type InP clad layer
It is possible to manufacture an element having a structure in which the type InP current blocking layer is not in contact.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a method for manufacturing a semiconductor light emitting device according to the present invention will be described below with reference to the drawings.

1A to 1C and 2A to
3C and FIG. 3 are manufacturing process diagrams provided for the description of the embodiment. Each drawing is a schematic cross-sectional view showing an element in a main process in the manufacturing process, which is cut in a direction orthogonal to its longitudinal direction. FIG. 4 is a perspective view showing another embodiment. Further, in the following description, specific materials and numerical conditions will be described, but these materials and conditions are merely preferable examples, and the present invention is not limited thereto.

First, as shown in FIG. 1A, p-type In
An ordinary liquid crystal growth method (hereinafter referred to as “LP
"E method"), the p-type InP buffer layer 33 is formed.
Is grown to a film thickness of 0.5 to 1.5 μm, for example.
As a result, the base 10 of this embodiment is obtained (see FIG. 1).
(A)). Then, for example, Si which becomes an etching mask
After a dielectric thin film 35 such as O ₂ is formed on the entire upper surface of the underlayer 10, it is processed into a stripe-shaped etching mask 35 made of SiO ₂ by ordinary photolithography and etching (see FIG. 1B). ). The width W _O of the stripe-shaped etching mask 35 is about 1.3 to 1.8 μm in this embodiment.

Next, using the formed stripe-shaped SiO ₂ as a mask, the semiconductor layers 33 and 31 are etched, for example, with a mesa stripe 37 having a height of 0.5 to 1.0 μm by an etching solution such as a mixed solution of bromine and methanol. Etching is performed so as to form (see FIG. 1C).

Next, as shown in FIG. 2A, the n-type InP current blocking layer 41 and the p-type InP current blocking layer 43 are formed by the LPE method while leaving the mask 35 made of SiO ₂ on the mesa stripe 37. And are successively grown. In this growth, these layers do not grow on the mask 35 but selectively grow only on the underlayer 11. In addition, each of these layers 4
When growing Nos. 1 and 43, the thickness of the n-type InP current blocking layer 41 is changed to the upper clad layer 49 (FIG. 2B) formed later and this layer 41 so that good characteristics of the light emitting element can be obtained. Make sure there is no contact with and the maximum thickness. This may have the same thickness as the height of the mesa stripe 37, or may have a thickness slightly smaller than that. For example, the thickness of the blocking layer 41 is preferably in the range of 0.5 to 1 μm.

Next, after removing the SiO ₂ mask 35 with, for example, hydrofluoric acid (see FIG. 2 (B)), as shown in FIG. 2 (C), each of the double hetero structures is formed by the third LPE method. A semiconductor layer, that is, a p-type InP clad layer 45,
p-type InGaAsP active layer 47, n-type InP clad layer 49 and n-type InGaAsP electrode layer (contact layer)
51 is crystal-grown in this order.

After that, a normal wafer process is performed and p
A p-side electrode 53 is provided on the back surface of the n-type InP substrate 31 and an n-type InGa substrate.
An n-side electrode 55 is formed on each AsP contact layer 51 (see FIG. 3), and further element isolation is performed to obtain a semiconductor light emitting element.

Although the embodiment of the method for manufacturing a semiconductor light emitting device according to the present invention has been described above, the present invention is not limited to the above embodiment. The present invention can be applied to the case where the conductivity types of the substrate and the respective semiconductor layers are all opposite to those in the embodiment.

For example, in the above embodiment, Si is used as the etching mask 35 when forming the mesa stripe 37.
Although an O ₂ thin film is used, this may be another dielectric thin film as long as it is not attacked by the etching solution. Also, as for the etching liquid, other appropriate etching liquid can be used if the controllability and reproducibility of etching are good.

In the above-mentioned embodiment, the semiconductor light emitting device having the Fabry-Perot type optical resonator in which the cleaved surface of the semiconductor light emitting device is used as a reflecting mirror has been described, but as another example, the fabrication using the cleaved surface is performed. The method of the present invention can be applied to a distributed feedback semiconductor light emitting device using an internal diffraction grating as an optical resonator instead of the Perot type optical resonator. In this case, as shown in FIG. 4, for example, p-type InP
A diffraction grating 57 having a pitch matching the oscillation wavelength is formed on the buffer layer 33, and the p-type In shown in FIG.
Other than using the p-type InGaAsP waveguide layer 59 instead of the P clad layer 45, it can be carried out in the same manner as described in the first embodiment.

Therefore, the types of LDs to which the present invention can be applied are not limited to those of the structure and material of FIG.
Any internal current constriction type may be used. Therefore, GaA
It can also be applied to a semiconductor light emitting device using another material such as s-based.

[0028]

As is apparent from the above description, according to the method for manufacturing a semiconductor light emitting device of the present invention, the same as the clad layer (upper clad layer) immediately above the active layer is formed before the double hetero structure is formed. Since the current blocking layer and each semiconductor layer for the double hetero structure are sequentially formed after forming the mesa stripe that is higher than the thickness of the conductivity type current blocking layer, the active layer width can be narrowed and the crystal growth layer It is possible to reduce the leak current due to the contact between the cladding layer immediately above the active layer and the current blocking layer of the same conductivity type as that of the rising current.

Therefore, according to the manufacturing method of the present invention, as compared with the conventional manufacturing method in which the leakage current is generated and the yield is poor, the semiconductor light emitting element having excellent light emission efficiency and low threshold current can be obtained.

[Brief description of drawings]

FIG. 1A to FIG. 1C are manufacturing process diagrams for explaining an embodiment of a method for manufacturing a semiconductor light emitting device according to the present invention.

2A to 2C are diagrams for explaining an embodiment. FIG.
FIG. 4 is a manufacturing process diagram that follows FIG.

FIG. 3 is a manufacturing process diagram following FIG. 2 for explaining the embodiment.

FIG. 4 is a perspective view showing an example.

5A to 5C are process diagrams for explaining the conventional art.

6A and 6B are process diagrams following FIG. 5 for explaining the conventional technique.

[Explanation of symbols]

 10: Base 31, 31a: p-type InP substrate 33, 33a: p-type InP buffer layer 35: etching mask 37: mesa stripe 41: n-type InP current blocking layer 43: p-type InP current blocking layer 45: p-type InP clad Layer 47: p-type InGaAsP active layer 49: n-type InP clad layer 51: n-type InGaAsP electrode layer 53: p-side electrode 55: n-side electrode 57: p-type InGaAsP waveguide layer

Claims (2)

[Claims] 1. A method for manufacturing an internal current constriction type semiconductor light emitting device on a base made of a compound semiconductor, comprising: (a) forming a mask of a predetermined shape made of a dielectric on the base; (B) forming a mesa-shaped portion of the base covered with the mask; and (c) an internal current composed of at least two current blocking layers having different conductivity types with respect to the base on which the mesa-shaped portion is formed. A step of growing a confinement layer; and (d) removing the mask from the underlying layer on which the internal current constriction layer has been grown, and then forming each semiconductor layer for a double hetero structure on the underlying layer. And a method for manufacturing a semiconductor light emitting device. 2. The method for manufacturing a semiconductor light emitting device according to claim 1, wherein the height of the mesa-shaped portion is set to be approximately the same as the thickness of the current blocking layer of the same conductivity type as the semiconductor layer for the upper cladding layer. A method for manufacturing a semiconductor light emitting device, which is characterized.