JPS63250886A - Manufacture of semiconductor laser element - Google Patents
Manufacture of semiconductor laser elementInfo
- Publication number
- JPS63250886A JPS63250886A JP62084570A JP8457087A JPS63250886A JP S63250886 A JPS63250886 A JP S63250886A JP 62084570 A JP62084570 A JP 62084570A JP 8457087 A JP8457087 A JP 8457087A JP S63250886 A JPS63250886 A JP S63250886A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type inp
- type
- current confinement
- mesa
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 230000003287 optical effect Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000005253 cladding Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 2
- 239000007791 liquid phase Substances 0.000 claims 2
- 230000015556 catabolic process Effects 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 4
- 230000010355 oscillation Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000025 interference lithography Methods 0.000 description 2
- -1 12-/-5io Substances 0.000 description 1
- 101150054880 NASP gene Proteins 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/223—Buried stripe structure
- H01S5/2237—Buried stripe structure with a non-planar active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/24—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a grooved structure, e.g. V-grooved, crescent active layer in groove, VSIS laser
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、低閾値電流でかつ、単−縦モードで発振する
と共に、高出力を得ることができる半導体レーザ素子の
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor laser device that has a low threshold current, oscillates in a single longitudinal mode, and can obtain high output. .
（従来の技術）
縦単一モード発振が可能な半導体レーザとしてＤＦＢ（
Ｄｉｓｔｒｉｂｕｔｅｄ ｆｅｅｄｂａｃｋ）型半導体
レーザが提案されている。(Prior technology) DFB (
Distributed feedback) type semiconductor lasers have been proposed.
従来、このような分野の技術としては、例えば、Ｅｌｅ
ｃｔｒｏｎｉｃｓ Ｌｅｔｔｅｒｓ ｖｏｌ、１８
（２３） Ｐ、１００６ＪＯＯ８（１９８２）
ｒＮＥＷ １．５ ｔｔ ｍ ＷＡＶＥＬＥ
ＮＧＴＩＩ Ｇａ１ｎＡｓＰ／ＩｎＰＤ］５ＴＲ１１
１ｔｌＴＥＴ） ＦＥＥＤＢＡ（Ｊ ＬＡＳ［！ＲＪ
ニ記載されるものがあった。Conventionally, as a technology in this field, for example, Ele
ctronics Letters vol, 18
(23) P, 1006JOO8 (1982)
rNEW 1.5 tt m WAVELE
NGTII Ga1nAsP/InPD]5TR11
1tlTET) FEEDBA(J LAS[!RJ
There were two things listed.
第２図は係る従来の埋め込みＤＦＢ型半型体４休レーザ
素子造工程図である。FIG. 2 is a process diagram for manufacturing such a conventional buried DFB half-shaped laser device.
まず、第２１Ｄ（ａ）に示されるように、１回目の液相
エピタキシャル成長（ＬＰＥ）によってｎ型ＩｎＰ基板
１上にｎ型ＩｎＰクラッド層２と、Ｇａ１ｎＡｓＰ活性
層３と、ｐ型Ｇａ１ｎＡｓＰ ＊、導波路層４とを順次
に成長させる。続いて、フォログラフィノクリソグラフ
ィによってレジストパターンをｐ 型Ｇａ１ｎＡｓＰ光
導波路Ｎ４の上側面に形成し、次に、ケミカルエツチン
グ技術によってｐ型Ｇａ１ｎＡｓＰ光導波路層４の不要
部分のエツチングを行って、この光導波路層４の表面を
適正なピンチ及び深さの波形グレーティング（ｃｏｒｒ
ｕｇａｔｉｏｎ ｇｒａｔｉｎｇ） ４ ａを形成する
。First, as shown in 21D(a), an n-type InP cladding layer 2, a Ga1nAsP active layer 3, a p-type Ga1nAsP The wave path layer 4 is grown sequentially. Subsequently, a resist pattern is formed on the upper surface of the p-type Ga1nAsP optical waveguide N4 by holographic lithography, and then unnecessary portions of the p-type Ga1nAsP optical waveguide layer 4 are etched by chemical etching technology to form this optical waveguide. The surface of layer 4 is coated with a corrugated grating (corr) of appropriate pinch and depth.
ugation grating) 4a.
次に、第２図（ｂ）に示されるように、２回目のＬＰＥ
によってｐ型ＩｎＰクラッド層５と、ｐ型Ｇａ１ｎＡｓ
ＰキャンプＮ６とを順次に成長させる。Next, as shown in FIG. 2(b), the second LPE
p-type InP cladding layer 5 and p-type Ga1nAs
P camp N6 is grown sequentially.
次に、通常の埋め込み構造の半導体レーザの製造時に用
いられると同様なフォトエツチング手法を用いてｐ型Ｇ
ａ１ｎ４ｓｌ’キャップ層６と、ｐ型！ｎＰクラッド層
５と、ｐ型Ｇａ１ｎＡｓＰ光導波路層４と、Ｇａ１ｎＡ
ｓＰ活性層３と、ｎ型ＩｎＰクラッド層２のそれぞれの
不要部分の除去を行って、第２図（ｃ）に示されるよう
に、逆メサ形状の積層体７を形成する。この場合、Ｇａ
１ｎＡｓＰ活性層の幅讐。は低閾値電流及び安定な基本
モード発振のため１．５μｍ以下にする必要がある。Next, p-type G is etched using a photoetching method similar to that used in manufacturing semiconductor lasers with an ordinary buried structure.
a1n4sl' cap layer 6 and p-type! nP cladding layer 5, p-type Ga1nAsP optical waveguide layer 4, and Ga1nA
Unnecessary portions of the sP active layer 3 and the n-type InP cladding layer 2 are removed to form an inverted mesa-shaped stacked body 7, as shown in FIG. 2(c). In this case, Ga
Width of 1nAsP active layer. must be 1.5 μm or less for low threshold current and stable fundamental mode oscillation.
次に、３回目のＬＰＨによって、ｐ型ＩｎＰ Ｔ；、流
狭窄層８と、ｎ型ＩｎＰ電流狭窄層９とを順次成長させ
、メサ型形状の積層体７をその両側において埋め込みよ
って、第２図（ｄ）に示されるように、レーザ素子を得
る。Next, by a third LPH, a p-type InP current confinement layer 8 and an n-type InP current confinement layer 9 are sequentially grown, and the mesa-shaped stacked body 7 is buried on both sides to form a second layer. A laser device is obtained as shown in Figure (d).
また、図示しないが、ｎ型ＩｎＰ基板１の下側面に負電
極、ｐ型ＧａｌゎＡｓＰキャップ層６の上側面に正電極
をそれぞれ設けてこの半導体レーザ素子を構成する。Although not shown, a negative electrode is provided on the lower surface of the n-type InP substrate 1, and a positive electrode is provided on the upper surface of the p-type GalAsP cap layer 6 to configure this semiconductor laser device.
この半導体レーザ素子に所定のバイアスを印加してこれ
を動作させると、ｐ型ＩｎＰ電流狭窄層８とｎ型ＩｎＰ
電流狭窄層９との界面は逆バイアスとなるため、順バイ
アスとなっているＧａｒｎＡｓＰ活性層３の部分に電流
が効率よ（注入される。従って、この半導体レーザを低
閾値電流で発振させることができる。When a predetermined bias is applied to this semiconductor laser element and it is operated, the p-type InP current confinement layer 8 and the n-type InP
Since the interface with the current confinement layer 9 is reverse biased, current is efficiently injected into the forward biased portion of the GarnAsP active layer 3. Therefore, this semiconductor laser can be oscillated with a low threshold current. can.
更に、Ｇａ１ｎＡｓＰ活性層３で発生した光の一部はｐ
型Ｇａ１ｎＡｓＰ光導波路層４に導かれ、この光導波路
層の適正ピッチ及び深さの波形グレーティング４ａによ
ってブラッグ反射され、単−縦モードで発振する。Furthermore, a part of the light generated in the Ga1nAsP active layer 3 is p
The light is guided to the Ga1nAsP type optical waveguide layer 4, is Bragg-reflected by the waveform grating 4a of the optical waveguide layer with appropriate pitch and depth, and oscillates in a single longitudinal mode.
ところで、この構造の半導体レーザ素子は、電流狭窄Ｎ
８及び９でメサ型積層体７の側面が埋め込まれた構造と
なっているため、活性層３を迂回するリーク電流を減少
又は無くすためには、ｐ型ＩｎＰ電流狭窄層８の成長の
際にこの電流狭窄層８の上側面を活性層３の側面と接す
る高さで停止させ、その上にｎ型ＩｎＰ電流狭窄層９を
成長させるようにして両層の界面が活性ＪＷ３の側面と
接するように形成するのが最も良い。By the way, the semiconductor laser device with this structure has current confinement N
8 and 9 have a structure in which the side surfaces of the mesa-type stacked body 7 are buried, so in order to reduce or eliminate leakage current that bypasses the active layer 3, it is necessary to The upper surface of this current confinement layer 8 is stopped at a height where it contacts the side surface of the active layer 3, and the n-type InP current constriction layer 9 is grown on top of it, so that the interface between both layers is in contact with the side surface of the active JW 3. It is best to form
（発明が解決しようとする問題点）
しかしながら、上記した従来の半導体レーザ素子におい
ては、活性層の幅−０は逆メサ積層体を形成する際のエ
ツチングにより決定される。従って、加工技術上の制約
から活性層の幅を更に小さくすることが困難であり、よ
り低閾値電流で発振させることができないという問題が
あった。また、ｎ型基板を用いているため、電流狭窄構
造がｎ−ｐ−ｎ構造となる。このため、ｐ型基板を用い
た場合のｐ−ｎ−ｐ構造と比較して電流狭窄の際の特性
が悪いから半導体レーザ素子に高電圧を印加できず、高
出力を得ることができないという問題があった。(Problems to be Solved by the Invention) However, in the above-described conventional semiconductor laser device, the width -0 of the active layer is determined by etching when forming an inverted mesa stack. Therefore, there is a problem in that it is difficult to further reduce the width of the active layer due to processing technology constraints, and oscillation cannot be achieved with a lower threshold current. Furthermore, since an n-type substrate is used, the current confinement structure is an npn structure. For this reason, compared to the p-n-p structure using a p-type substrate, the current confinement characteristics are poor, so a high voltage cannot be applied to the semiconductor laser element and high output cannot be obtained. was there.
本発明は、上記問題点を除去し、低閾値電流で、かつ、
単−縦モードで発振すると共に高出力を得ることができ
、しかもその製造が簡易な半導体レーザ素子の製造方法
を提供することを目的とする。The present invention eliminates the above problems, has a low threshold current, and
It is an object of the present invention to provide a method for manufacturing a semiconductor laser device which can oscillate in a single longitudinal mode and obtain high output, and which is easy to manufacture.
（問題点を解決するための手段）
本発明は、上記問題点を解決するために、ストライプ状
の溝の両側に電流狭窄層を有し、その溝内部に光導波路
層、活性層及びクラッド層から成るダブルテヘロ構造を
有する半導体レーザ素子の製造方法において、基板をｐ
型ＩｎＰ基板とし、エツチング兼成長マスクとなるスト
ライプ状の３４０ｇ膜を形成し、その３４０ｇ膜をマス
クとして前記ｐ型ＩｎＰ基板をエツチングし、その基板
上にメサ型ストライプを形成し、そのＳｉＯ□膜を選択
結晶成長マスクとし、メサ型ストライプの両側にそれぞ
れｎ型ＩｎＰ電流狭窄層とｐ型ＩｎＰ電流狭窄層とを成
長させ、それらの電流狭窄層とメサ上部とでストライプ
状の溝を形成し、その後、前記ＳｉＯ□膜を除去し、Ｌ
ＰＩ！でクラッド層、活性層及び光導波路層を成長させ
、その光導波路層上に所定のピッチと深さの波形グレー
ティングを形成し、その波形グレーティング上にＬＰＥ
でクラッド層を成長させるようにしたものである。(Means for Solving the Problems) In order to solve the above problems, the present invention has a current confinement layer on both sides of a striped groove, and an optical waveguide layer, an active layer, and a cladding layer inside the groove. In the method for manufacturing a semiconductor laser device having a double Tehero structure consisting of
A stripe-shaped 340g film is formed as an etching and growth mask on an InP substrate, and the p-type InP substrate is etched using the 340g film as a mask to form a mesa-type stripe on the substrate. is used as a selective crystal growth mask, an n-type InP current confinement layer and a p-type InP current confinement layer are grown on both sides of the mesa-shaped stripe, and a striped groove is formed by these current confinement layers and the upper part of the mesa, After that, the SiO□ film is removed, and the L
PI! A cladding layer, an active layer, and an optical waveguide layer are grown on the optical waveguide layer, a wavy grating with a predetermined pitch and depth is formed on the wavy grating, and LPE is formed on the wavy grating.
The cladding layer is grown using the following steps.
（作用）
本発明によれば、上記のように、ｐ型基板を用いること
により、内部電流狭窄層はｐ−ｎ−ｐ接合構造となり、
この電流狭窄層の耐圧は向上する。(Function) According to the present invention, as described above, by using a p-type substrate, the internal current confinement layer has a p-n-p junction structure,
The breakdown voltage of this current confinement layer is improved.
また、基板をメサ状に加工した後、電流狭窄層を形成す
るため、高耐圧に耐えるように充分厚くすることができ
、高出力動作が可能である。更に、湾曲した活性層の幅
はメサ上部の幅及び電流狭窄層で形成された溝の深さで
決まるため、１μｍ程度の狭い幅の活性層を制御よく形
成でき、低闇値電流での発振が可能である。Furthermore, since the current confinement layer is formed after processing the substrate into a mesa shape, it can be made sufficiently thick to withstand high breakdown voltage, and high output operation is possible. Furthermore, since the width of the curved active layer is determined by the width of the upper part of the mesa and the depth of the groove formed by the current confinement layer, it is possible to form an active layer with a narrow width of about 1 μm with good control, and oscillation at low dark value currents can be achieved. is possible.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の実施例を示す半導体レーザ素子の製造
工程図である。FIG. 1 is a manufacturing process diagram of a semiconductor laser device showing an embodiment of the present invention.
まず、第１図（ａ）に示されるように、ｐ型ｒｎＰ基板
１１の表面に、通常のフォトリソ手法により、ＳｉＯ□
膜１２全１２ライプ状に形成する。このＳｉＯ□膜１２
全１２工程でエツチングマスク及び選択成長マスクとし
て働く。ストライプ幅Ｗは後に成長させる活性層の湾曲
した部分の幅を決定するもので、安定な単−縦モード発
振を得るようにするために１μｍ程度にする。First, as shown in FIG. 1(a), a SiO□
The film 12 is formed into a total of 12 stripes. This SiO□ film 12
It acts as an etching mask and selective growth mask in all 12 steps. The stripe width W determines the width of the curved portion of the active layer to be grown later, and is set to about 1 μm in order to obtain stable single-longitudinal mode oscillation.
次に、第１図（ｂ）に示されるように、ＳｉＯ□膜１２
全１２チングマスクとしてｐ型ＩｎＰ基板１１の不要部
分を除き、メサ型ストライプを形成する。メサの高さｈ
は、次に成長させる電流狭窄層の厚みが充分耐圧がとれ
るように１．５〜２．０μｍにする。Next, as shown in FIG. 1(b), the SiO□ film 12
A mesa-shaped stripe is formed by removing unnecessary portions of the p-type InP substrate 11 as a total of 12 etching masks. Mesa height h
The thickness of the current confinement layer to be grown next is set to 1.5 to 2.0 μm so as to have a sufficient breakdown voltage.
次に、第１図（ｃ）に示されるように、１回目のＬＰＥ
でＳｉＯ□膜１２全１２成長マスクとしてメサの両側に
ｎ型ＩｎＰ電流狭窄層１３とｐ型！ｎＰ電流狭窄層１４
とを順次成長させる。この際、ｎ型［ｎＰ電流狭窄層１
３とｐ型ＩｎＰ電流狭窄層１４の厚みは共に約１μ工程
度以上にすると素子に高電圧を印加しても充分耐圧があ
り、電流狭窄層として有効に働く。Next, as shown in FIG. 1(c), the first LPE
As a growth mask for all 12 SiO□ films 12, there are n-type InP current confinement layers 13 on both sides of the mesa and p-type! nP current confinement layer 14
and grow sequentially. At this time, n-type [nP current confinement layer 1
When both the thickness of the p-type InP current confinement layer 3 and the p-type InP current confinement layer 14 are about 1 μm or more, they have sufficient withstand voltage even when a high voltage is applied to the device, and work effectively as a current confinement layer.
また、ｐ型ＩｎＰ電流狭窄１１１４はメサ上部より少し
高くなるまで成長させ、この電流狭窄１１４の側面Ａと
ｐ型ＩｎＰ Ｉｓ板１１のメサ上部とで溝が形成される
ようにする。この場合、メサ上部からｐ型ＴｎＰ電流狭
窄Ｎ１４の上面までの溝の深さｄ、 （第１図（ｄ）
参照〕は、次に成長させる活性層の湾曲がゆるやかにな
るように、又、光導波路層表面が平坦になるように浅く
する０例えば、０．５μｍ程度とする。この点、ｐ型Ｉ
ｎＰ 基板１１をメサ状にエツチングしない状態〔第１
図（ａ）参照〕のままで、ｎ型ＩｎＰ電流狭窄層とｐ型
ｒｎＰ電流狭窄層とを成長させる場合には、これらの厚
みは合計で０．５μｍ程度しかとれず、充分な耐圧を得
ることができない。Further, the p-type InP current confinement 1114 is grown to be slightly higher than the upper part of the mesa, so that a groove is formed between the side surface A of this current confinement 114 and the upper part of the mesa of the p-type InP Is plate 11. In this case, the depth of the groove from the top of the mesa to the top surface of the p-type TnP current confinement N14 is d, (Fig. 1(d)
Reference] is made shallow, for example, about 0.5 μm, so that the active layer to be grown next has a gentle curvature and the surface of the optical waveguide layer is flat. At this point, p-type I
State in which the nP substrate 11 is not etched into a mesa shape [first
When growing an n-type InP current confinement layer and a p-type rnP current confinement layer as shown in Figure (a), the total thickness of these layers is only about 0.5 μm, and a sufficient breakdown voltage can be obtained. I can't.
次に、第１図（ｄ）に示されるように、ＳｉＯ２膜１２
をエツチングし取り除く。Next, as shown in FIG. 1(d), the SiO2 film 12
Etch and remove.
次に、第１図（ｅ）に示されるように、ｐ型ＩｎＰクラ
ンドＪＷ１５、Ｇａ１ｎＡｓＰ活性［１６、ｎ型Ｇａ１
ｎＡｓＰ光導波路Ｎ１７を２回目のＬＰＥで順次成長さ
せる。Next, as shown in FIG. 1(e), p-type InP clan JW15, Ga1nAsP activity [16, n-type Ga1
The nAsP optical waveguide N17 is sequentially grown in the second LPE.
この場合、Ｇａ１ｎＡｓＰ活性Ｊ’Ｗ１６はＬＰＥのた
め、溝内部でゆるやかに湾曲し、光導波路Ｊｌｉ１７の
成長により、表面はフラットになる。即ち、ＬＰＨの特
性上、溝は埋められるように各層は成長し、Ｇａ１ｎＡ
ｓＰ活性層１６は湾曲した形になり、これにより、横方
向の屈折率差ができ、基本モード発振が可能となる。In this case, the Ga1nAsP active J'W16 is gently curved inside the groove due to LPE, and the surface becomes flat due to the growth of the optical waveguide Jli17. That is, due to the characteristics of LPH, each layer grows so that the groove is filled, and the Ga1nA
The sP active layer 16 has a curved shape, which creates a lateral refractive index difference and enables fundamental mode oscillation.
また、湾曲したＧａ１ｎＡｓＰ活性層１６の上部のｎ型
Ｇａ１ｎＡｓＰ光導波路層１７の厚さｄ！はＤＦＢ型で
半導体レーザとして動作するために、通常この光導波路
Ｎ１７の組成とこの光導波路層１７上に形成される波形
グレーティングのピンチ及び深さによっているが、０．
２〜０．３ μｍ程度である。この場合ｄ。Also, the thickness d of the n-type Ga1nAsP optical waveguide layer 17 above the curved Ga1nAsP active layer 16! Since it is a DFB type and operates as a semiconductor laser, it usually depends on the composition of this optical waveguide N17 and the pinch and depth of the waveform grating formed on this optical waveguide layer 17.
It is about 2 to 0.3 μm. In this case d.
が０．５μｍ程度と浅く、又、光導波路層１７がＩｎＰ
よりも平坦になりやすいＧａ１ｎＡｓＰであるために、
ｄｚ＝０．２〜０．３μｍでも光導波路層１７の上面は
平坦になる。The optical waveguide layer 17 is shallow at about 0.5 μm, and the optical waveguide layer 17 is made of InP.
Because Ga1nAsP is more likely to be flat than
Even when dz=0.2 to 0.3 μm, the upper surface of the optical waveguide layer 17 becomes flat.
次に、第１図Ｃｆ＞ に示されるように、この光導波路
Ｊ１１７の上面に、フォログラフィックリソグラフイと
化学エツチングにより適正なピンチ及び深さの波形グレ
ーティング１７ａを形成する。Next, as shown in FIG. 1Cf>, a waveform grating 17a with appropriate pinch and depth is formed on the upper surface of this optical waveguide J117 by holographic lithography and chemical etching.
次に、第１図（ｇ）に示されるように、波形グレーティ
ング１７ａの上に３回目のＬＰＥでｎ型ＩｎＰクラッド
層１８を成長させることでＤＦＢ型レーザ素子を得るこ
とができる。Next, as shown in FIG. 1(g), a DFB type laser device can be obtained by growing an n-type InP cladding layer 18 on the waveform grating 17a by a third LPE.
図示しないが、ｐ型ＩｎＰ基板１１下側に正電極、ｎ型
ＩｎＰクラッド層１８の上側に負電極を形成し、所定の
バイアスを印加するとｎ型ＩｎＰ電流狭窄層１３とｐ型
ＩｎＰ電流狭窄層１４との界面が逆バイアスとなり、順
バイアスとなる湾曲したＧａ１ｎＡｓＰ活性ＪＩｉ１６
に電流が効率よく流れる。また、Ｇａ１ｎＡｓＰ活性層
１６で発生した光の一部は光導波路層１７に導かれ、波
形グレーティングＩＬＩのためブラッグ反射を起こすこ
とになり、ＤＦＢ型レーザ素子特有の発振が起こる。Although not shown, a positive electrode is formed below the p-type InP substrate 11 and a negative electrode is formed above the n-type InP cladding layer 18. When a predetermined bias is applied, the n-type InP current confinement layer 13 and the p-type InP current confinement layer The curved Ga1nAsP active JIi16 has a reverse bias and a forward bias at the interface with 14.
current flows efficiently. Further, a part of the light generated in the Ga1nAsP active layer 16 is guided to the optical waveguide layer 17 and causes Bragg reflection due to the waveform grating ILI, causing oscillation peculiar to a DFB type laser element.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、ｐ型基
板を用いることにより、内部電流狭窄層はｐ−ｎ−ｐ接
合構造となるため、この電流狭窄層の耐圧は向上する。(Effects of the Invention) As described above in detail, according to the present invention, by using a p-type substrate, the internal current confinement layer has a p-n-p junction structure, so that the breakdown voltage of this current confinement layer is will improve.
また、基板をメサ状に加工した後、電流狭窄層を形成す
るため、高耐圧に耐えるように充分厚くすることができ
、高出力動作が可能となる。更に、湾曲した活性層の幅
はメサ上部の幅及び電流狭窄層で形成された溝の深さで
決まるため、１μｍ程度の狭い幅の活性層を制御よく形
成でき、低閾値電流での発振が可能である。Furthermore, since the current confinement layer is formed after the substrate is processed into a mesa shape, it can be made sufficiently thick to withstand high breakdown voltage, and high output operation is possible. Furthermore, since the width of the curved active layer is determined by the width of the upper part of the mesa and the depth of the groove formed by the current confinement layer, it is possible to form an active layer with a narrow width of about 1 μm with good control, and oscillation at a low threshold current is prevented. It is possible.
第１図は本発明の実施例を示す半導体レーザ素子の製造
工程図、第２図は従来の埋め込みＤＦＢ型半導体レーザ
素子の製造工程図である。
１ｔ・ｐ型ＩｎＰ基板、１２−・−５ｉｏ、膜、１３・
ｎ型ＩｎＰ電流狭窄層、１４・・・ｐ型［ｎＰ電流狭窄
層、１５・・・ｐ型ＩｎＰクラフト層、１６−Ｇａ１ｎ
ＡｓＰ活性層、１７−ｎ型Ｇａ１ｎＡｓＰ光導波路層、
１７ａ・・・波形グレーティング、１８・・・ｎ型Ｉｎ
Ｐクラッド層。FIG. 1 is a manufacturing process diagram of a semiconductor laser device according to an embodiment of the present invention, and FIG. 2 is a manufacturing process diagram of a conventional buried DFB type semiconductor laser device. 1t/p-type InP substrate, 12-/-5io, film, 13/
n-type InP current confinement layer, 14... p-type [nP current confinement layer, 15... p-type InP craft layer, 16-Ga1n
AsP active layer, 17-n type Ga1nAsP optical waveguide layer,
17a... Waveform grating, 18... n-type In
P cladding layer.
Claims (1)
に光導波路層、活性層及びクラッド層から成るダブルテ
ヘロ構造を有する半導体レーザ素子の製造方法において
、 （ａ）ｐ型ＩｎＰ基板上にストライプ状のマスクを形成
する工程と、 （ｂ）該マスクを用いて前記ｐ型ＩｎＰ基板をエッチン
グし、メサ型ストライプを形成する工程と、 （ｃ）前記マスクを用いて選択結晶成長を行い、前記メ
サ型ストライプの両側にそれぞれｎ型ＩｎＰ電流狭窄層
とｐ型ＩｎＰ電流狭窄層とを成長させ、該電流狭窄層と
メサ上部とでストライプ状の溝を形成する工程と、 （ｄ）前記マスクを除去し、液相エピタキシャル成長に
よりクラッド層、活性層及び光導波路層を成長させる工
程と、 （ｅ）該光導波路層上に所定のピッチと深さの波形グレ
ーティングを形成する工程と、 （ｆ）該波形グレーティング上に液相エピタキシャル成
長によってクラッド層を成長させる工程とを順次施すよ
うにしたことを特徴とする半導体レーザ素子の製造方法
。[Scope of Claims] A method for manufacturing a semiconductor laser device having a double Tehero structure comprising a current confinement layer on both sides of a striped groove and an optical waveguide layer, an active layer, and a cladding layer inside the groove, comprising: (a) (b) etching the p-type InP substrate using the mask to form a mesa-shaped stripe; (c) using the mask. performing selective crystal growth to grow an n-type InP current confinement layer and a p-type InP current confinement layer on both sides of the mesa-shaped stripe, respectively, and forming a stripe-shaped groove with the current confinement layer and the upper part of the mesa; (d) removing the mask and growing a cladding layer, an active layer, and an optical waveguide layer by liquid phase epitaxial growth; and (e) forming a waveform grating with a predetermined pitch and depth on the optical waveguide layer. and (f) growing a cladding layer on the corrugated grating by liquid phase epitaxial growth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62084570A JPS63250886A (en) | 1987-04-08 | 1987-04-08 | Manufacture of semiconductor laser element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62084570A JPS63250886A (en) | 1987-04-08 | 1987-04-08 | Manufacture of semiconductor laser element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63250886A true JPS63250886A (en) | 1988-10-18 |
Family
ID=13834326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62084570A Pending JPS63250886A (en) | 1987-04-08 | 1987-04-08 | Manufacture of semiconductor laser element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63250886A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0231488A (en) * | 1988-07-20 | 1990-02-01 | Mitsubishi Electric Corp | Semiconductor laser device and its manufacture |
| US5111471A (en) * | 1990-07-16 | 1992-05-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor laser device |
| US5179040A (en) * | 1990-07-16 | 1993-01-12 | Mitsubishi Denki Kabushiki Kaisha | Method of making a semiconductor laser device |
-
1987
- 1987-04-08 JP JP62084570A patent/JPS63250886A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0231488A (en) * | 1988-07-20 | 1990-02-01 | Mitsubishi Electric Corp | Semiconductor laser device and its manufacture |
| US5111471A (en) * | 1990-07-16 | 1992-05-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor laser device |
| US5179040A (en) * | 1990-07-16 | 1993-01-12 | Mitsubishi Denki Kabushiki Kaisha | Method of making a semiconductor laser device |
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