JPH05144946A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a technique which can form a fine wiring on a semiconductor wafer. CONSTITUTION:After a connection hole is formed in an insulating film which is deposited on a semiconductor wafer 1, a conductive film is deposited on the insulating film and the conductive film is etched. Thereby, when forming a wiring connected to conductor elements Q1, Q2, a process consisting of deposition of an insulating film, formation of a connection hole, deposition of a conductive film and etching is divided into two to reduce a processing step of an insulating film and a conductive film in a separate process and to enlarge a process margin.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique, and more particularly to a technique effectively applied to the formation of fine wiring.

[0002]

2. Description of the Related Art Circuit elements and wirings constituting a semiconductor integrated circuit are formed by a lithographic technique for transferring a pattern on a photomask onto a semiconductor wafer by using light such as g-line and i-line.

In recent years, the design rule of circuit elements and wirings has been miniaturized to the submicron order due to the high integration of semiconductor integrated circuits, and the dimensional accuracy and the positional accuracy of patterns transferred onto a semiconductor wafer are deteriorated. Alternatively, a decrease in manufacturing yield due to a pattern defect or adhered foreign matter is a serious problem. Also, from resist application to exposure,
The problem is that the process leading to development becomes long and costs are high.

Therefore, a technique called a self-alignment process has been proposed. This is to perform the next process using the resist pattern used in the previous process as it is when forming an integrated circuit on a semiconductor wafer. Especially, it is put to practical use in the process where high overlay accuracy is required. Has been done.

Further, as a method for improving the accuracy of the pattern transferred onto the wafer, a phase shift technique has been proposed in which an optical phase shifter is provided in a part of the pattern formed on the photomask.

For example, in Japanese Examined Patent Publication No. 62-59296, a transparent film is provided on one of a pair of transmissive regions sandwiching a light-shielding region on a photomask, and a light is transmitted between the two transmissive regions during exposure. There is disclosed a phase shift technique in which the interference light is weakened at a portion which should originally be a light-shielding area on the wafer by causing a phase difference in the.

Further, instead of the above-mentioned light exposure technology, as described in “Electronic Materials / November Issue / Separate Volume” P110 to P114, published by Kogyo Kogyo Kaisha, Ltd., November 18, 1986, An electron beam direct writing technique of exposing a photoresist coated on a wafer by drawing a pattern using an electron beam has been put into practical use in the manufacture of an application specific LSI (ASIC) and the like.

[0008]

For example, miniaturization of a MOSFET is performed by thinning a gate insulating film or an interlayer insulating film and reducing a gate length or a gate width. However, the film thickness of the conductor layer forming the word line or the data line cannot be reduced at the same rate as the insulating film and the gate are reduced.

This is because if the conductor layers forming the word lines and the data lines are thinned, the parasitic resistance increases, the delay of the word lines and the data lines increases, and the circuit speed cannot be increased. Therefore, the size ratio in the vertical direction with respect to the size in the horizontal direction increases as the integrated circuit becomes finer.

In this way, as the integrated circuit becomes finer,
Since the relative step difference becomes large, the process margin such as photoresist coating, etching, and film deposition becomes narrow, and it becomes difficult to select the processing conditions and inspect the processing pattern, resulting in a decrease in manufacturing yield.

For example, when the aspect ratio (hole depth / hole diameter) of the connection hole formed in the interlayer insulating film becomes about 1, a conductive film is formed in the connection hole by using the CVD method or the like. At the time of embedding, the side wall of the hole becomes a shadow and the film deposition rate at the bottom of the hole decreases, so that a cavity is formed in the conductive film inside the hole, and the reliability of the connection of the multilayer wiring decreases.

Therefore, an object of the present invention is to provide a technique capable of forming fine wiring.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0014]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

(1) After forming a connection hole in an insulating film deposited on a semiconductor wafer, depositing a conductive film on the insulating film, and then etching the conductive film to form a lower portion of the insulating film. When forming a wiring or a wiring connected to a semiconductor element, a series of steps including the deposition of the insulating film, the formation of the connection hole, the deposition of the conductive film, and the etching are performed twice or more.

(2) When a semiconductor element pattern is transferred onto a semiconductor wafer, a light reduction projection exposure method is used, and when a wiring pattern is transferred, an electron beam exposure method is used.

[0017]

According to the above-mentioned means (1), since the processing step of the insulating film and the conductive film in each step is reduced, a large process margin such as photoresist coating, etching, and film deposition can be obtained. As a result of facilitating the selection of the processing conditions and the inspection of the processing pattern, fine wiring can be easily formed and the wiring density can be greatly improved.

According to the above-mentioned means (2), by combining the light reduction projection exposure method and the electron beam exposure method,
Since it is possible to achieve both fine wiring and an exposure area, it is possible to eliminate restrictions on the wiring area and easily form fine wiring.

[0019]

First Embodiment A method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention will be described with reference to FIGS. Figure 1 (a)
2E are cross-sectional views of the semiconductor substrate shown in each step, and FIG.
Is a flow chart.

First, a semiconductor element Q ₁ , such as MOSFET,
Semiconductor wafer 1 made of silicon single crystal on which Q ₂ is formed 1
After depositing an insulating film 2a made of silicon oxide or the like, a photoresist is spin-coated on the insulating film 2a.

Subsequently, after exposing and developing the photoresist, the insulating film 2a is dry-etched using the photoresist as a mask to form the connection holes 3 reaching the semiconductor elements Q ₁ and Q _2.
a is formed. Then, the photoresist is removed by ashing (FIG. 1 (a)).

Next, a conductive film 4a is formed on the insulating film 2a.
Deposit. The conductive film 4a is, for example, an aluminum alloy,
It is composed of refractory metal, refractory metal silicide, polycrystalline silicon, etc. (FIG. 1 (b)).

Next, a photoresist is spin-coated on the conductive film 4a, the photoresist is exposed and developed, and then the conductive film 4a is dry-etched using the photoresist as a mask, whereby the semiconductor elements Q ₁ , A wiring 5a connected to Q ₂ is formed. Then, the photoresist is removed by ashing (FIG. 1 (c)).

The photoresist spin-coated on the conductive film 4a is of the opposite type to the photoresist spin-coated on the insulating film 2a. That is, if the photoresist spin-coated on the insulating film 2a is a positive type, the negative photoresist is spin-coated on the conductive film 4a.

As a result, the photomask used for forming the connection hole 3a can be used as it is for forming the conductive film 4a, so that the connection hole 3a and the conductive film 4a can be formed by one photomask. it can.

Next, a second insulating film 2b made of silicon oxide or the like is deposited on the semiconductor wafer 1 on which the wiring 5a is formed, a photoresist is spin-coated on the second insulating film 2b, and then the photoresist is exposed and developed. To do. When exposing this photoresist, the photomask used for forming the connection hole 3a is used.

Then, the insulating film 2b is dry-etched using the photoresist as a mask to form a second connection hole 3b above the wiring 5a. After that, the photoresist is removed by ashing (FIG. 1 (d)).

Next, a conductive film 4b is formed on the insulating film 2b.
Is deposited, and a photoresist is spin-coated on top of it, and then this photoresist is exposed and developed. Also in this case, a photoresist of the opposite type to the photoresist spin-coated on the insulating film 2b is used.

Then, the conductive film 4b is dry-etched using the photoresist as a mask to form a second wiring 5b on the wiring 5a. Then, the photoresist is removed by ashing (FIG. 1 (e)).

As described above, the semiconductor element Q ₁ , Q ₂ can be obtained by performing the series of steps including the deposition of the insulating film, the formation of the connection hole, the deposition of the conductive film and the etching in two steps.
According to the present embodiment in which the wiring connected to is formed, the following effects can be obtained.

(1) Since the processing step of the insulating film and the conductive film in each step can be reduced, a large process margin such as photoresist coating, etching and film deposition can be secured.

(2) Since the processing step of the insulating film and the conductive film in each step becomes small, the film thickness of the photoresist can be thinned at the time of exposure, and accordingly, fine processing can be easily performed.

(3) Since the thickness of the photoresist can be made thin, the alignment mark on the semiconductor wafer 1 can be easily detected, so that the overlay accuracy of the lower layer pattern and the upper layer pattern can be improved. ..

(4) Since the thickness of the photoresist can be reduced, the selection range of the photoresist can be widened. That is, since problems such as dry etching resistance are less likely to occur when selecting a photoresist, prioritizing resolution enables finer processing.

(5) Since the processing step of the insulating film and the conductive film in each step is reduced, the inspection after processing becomes easy. In other words, it is a serious problem that deep connection holes cannot be inspected even if they can be processed.
Since this can be solved, the reliability of the processing of the fine pattern can be increased.

(6) By the above items (1) to (5), it is possible to easily form a wiring having a film thickness to line width ratio of 1 or more, and to significantly improve the wiring density.

In the above description, the case where the wiring forming process is performed twice is explained, but it is also possible to perform the wiring forming process three times or more. In this case, the number of manufacturing steps is further increased, but since the processing step of the insulating film and the conductive film in each step can be further reduced, the process margin for photoresist coating, etching, film deposition, etc. is further increased. Therefore, finer wiring can be formed.

In the above description, the case of forming the wiring connected to the semiconductor element has been described, but the present invention can also be applied to the case of forming the upper layer wiring connected to the lower layer wiring.

In this case, as shown in FIG.
By forming the connection hole 3b having a larger diameter along the extending direction of the upper layer wiring 5d above the connection hole 3a having a larger diameter along the extending direction of c, the inside of the connection holes 3a and 3b can be formed. The connection reliability of the wirings 5a and 5b can be further improved.

[0040]

Second Embodiment FIG. 4 is an overall configuration diagram of an electron beam drawing apparatus 100 used in this embodiment.

The semiconductor wafer 1 is mounted on a sample table 102 on an XY stage 101 which is movable in a horizontal plane. An electron beam resist is applied to the surface of the semiconductor wafer 1.

An electron beam source 103 is provided above the sample table 102.
Is provided, and the electron beam is emitted toward the semiconductor wafer 1. That is, the exposure area can be expanded to the movable area of the XY stage 101.

A beam former 104, a sub-deflector 105, and a main deflector 1 are provided between the electron beam source 103 and the sample stage 102.
An electron optical system including 06 and the objective lens 107 is provided.

The electron beam emitted from the electron beam source 103 is
By passing through the electron optical system, a beam having a designated size is irradiated onto an arbitrary position on the semiconductor wafer 1 which is a workpiece.

The beam shaper 104 includes a shaper controller 10
8. The calculation signal generator 109 is connected to the calculator 110. The main deflector 106 includes a main deflection controller 111,
Via the main deflection signal generator 112, the sub deflector 105
Are connected to the computing unit 110 via the sub-deflection control unit 114 and the sub-deflection signal generation unit 115, respectively, and to the second buffer memory 113 capable of high-speed access.

The second buffer memory 113 has a mark position detector 116, a height detector 117, and a laser interferometer 118.
It is connected to a coordinate conversion unit 119 which performs analog / digital conversion and coordinate conversion of the signal from. Objective lens 10
Reference numeral 7 denotes the objective lens control unit 120 and the second buffer memory 1
It is connected to the control computer 121 via 13.

The arithmetic unit 110 is connected to the control computer 121 via a first buffer memory 122 which can be accessed at high speed. Further, the sample table 102 is connected to the control computer 121 via the sample table controller 123.

The control computer 121 comprises a mass storage device such as a hard disk, an input / output device such as a VDT, a CPU and the like. The drawing data storage unit 124 connected to the control computer 121 stores graphic information to be exposed on the semiconductor wafer 1, and the graphic information appropriately selected by the control program is stored in the first buffer memory as necessary. It is configured to be transferred to 122.

Regarding the mark position coordinates and height of the semiconductor wafer 1, prior to drawing, the relevant position of the semiconductor wafer 1 is scanned with an electron beam from the electron beam source 103 or light from the light source 125 to scan the sample stage 102. Information is obtained by laser measurement of the position, and the coordinates are converted into, for example, the reference coordinate system of the electron beam drawing apparatus 100 and stored in the second buffer memory 113.

Then, corresponding to the drawing of individual graphic information,
The control program is configured to control the main deflection control unit 111 and the sub deflection control unit 114. The height of the semiconductor wafer 1 is detected by obliquely irradiating the surface thereof with light from the light source 125 and detecting the reflected light.

In the arithmetic section 110, a control signal relating to the beam shape of the electron beam, the deflection amount, etc. is calculated based on the graphic information held in the first buffer memory 122, and the beam from the shaper control section 108 is calculated. Control of the molding machine 104,
Control of the main deflector 106 and the sub deflector 105 via the main deflection control unit 111 and the sub deflection control unit 114, and control of the objective lens 107 via the objective lens control unit 120 are performed.

In performing these controls, the second buffer memory 113 selectively reads out correction coefficients stored in advance corresponding to the position and height of the semiconductor wafer 1 for each area on the semiconductor wafer 1 described later. Then, the main deflection control unit 111, the sub-deflection control unit 114, and the objective lens control unit 120 are provided.

Next, an exposure method using the electron beam drawing apparatus 100 will be described with reference to FIGS.

FIG. 5 is a plan view of the semiconductor wafer 1 showing the 5: 1 reduction projection exposure method. In the figure, 702
Orientation Flat, 731 and 73
Reference numeral 2 denotes an exposure area in which exposure has already been completed (an area that can be exposed by one exposure operation, and is hereinafter referred to as a unit exposure area), and 733 to 736 are unit exposure areas to be exposed. It is formed on almost the entire area of the surface.

The exposure is usually performed in the numerical order shown here. However, the LSI formed on the semiconductor wafer 1
If the product type differs depending on the chip, or if the size of the chip is larger than the unit exposure area, the exposure order will change.

Here, the size of the chip is larger than the unit exposure area, and the unit exposure area 731 and the unit exposure area 7 in the figure are used.
It is assumed that 32 and 32 form one semiconductor chip 741.

When manufacturing such a large-area LSI, it is necessary to align the semiconductor elements constituting the LSI in the lower layer and the upper layer, but the positional relationship on the plane has a relative margin. Therefore, in the step of forming the semiconductor element on the semiconductor wafer 1, the semiconductor element pattern on the photomask is formed by using the optical reduction projection exposure method.
In the step of transferring to the above and then forming the wiring connecting the semiconductor elements, the wiring pattern is formed by using the electron beam exposure method.

FIG. 6 is an explanatory diagram showing the coordinate relationship between the unit exposure area and the electron beam exposure area of the optical reduction projection exposure. Here, it is assumed that the coordinate system is different for each unit exposure area of the light reduction projection exposure. That is, it is possible to correct the electron beam exposure for each unit exposure region of the light reduction projection exposure. If the same light reduction exposure unit is used, the optical distortion will be the same, and the same correction will be performed within the unit exposure area.

First, as shown in FIGS. 7 and 8, the pattern on the semiconductor wafer 1 is divided into a unit exposure area and a unit exposure area prior to the exposure, and a position coordinate system of the pattern in the unit exposure area is set. The error with the coordinate system of the electron beam writer is measured.

Therefore, an array of position measuring marks is formed on the semiconductor wafer 1 in advance by using a photomask in which an array of position measuring marks is formed at equal intervals in the unit exposure area. The position of the position measurement mark on the semiconductor wafer 1 is determined by scanning each mark with an electron beam and measuring the position of the XY stage 101 with a laser interferometer 118. The height of the surface of the semiconductor wafer 1 is
Light is emitted obliquely from the light source 125, and the reflected light is detected by the height detector 117.

Subsequently, the measured value is converted into the coordinate conversion unit 119.
Then, the coordinate conversion is performed in the coordinate system of the electron beam drawing apparatus 100, and the coordinate conversion data is stored in the mark position / height data storage unit of the control computer 121 and transferred to the second buffer memory 113.

Next, the drawing pattern data of the unit exposure area is extracted from the drawing data storage section 124 of the control computer 121 and transferred to the first buffer memory 122.
Further, it is transferred to the calculation unit 110.

The arithmetic section 110 performs arithmetic processing of the pattern data transferred from the buffer memory 122 to calculate drawing coordinate data, and converts this into a control signal relating to the beam shape and deflection amount of the electron beam. The signals are output to the molding signal generator 109, the main deflection signal generator 112, and the sub deflection signal generator 115, respectively.

The molding machine control unit 108 includes the molding signal generation unit 1
The beam shaper 104 is controlled based on the control signal output from the signal generator 09. The main deflection signal generator 112 and the sub-deflection signal generator 115, together with the coordinate conversion data of the position of the pattern in the unit exposure area stored in the second buffer memory 113, the control signal, the main deflection controller 111 and the sub-deflection controller. Output to 114. The coordinate conversion data of the height of the semiconductor wafer 1 in the unit exposure area is output to the objective lens controller 120.

Main deflection control section 111, sub deflection control section 114
Further, the objective lens control unit 120 corrects the drawing coordinate data in the unit exposure area based on the coordinate conversion data of the position and height of the mark in the unit exposure area, and based on the corrected drawing coordinate data. By controlling the main deflector 106, the sub deflector 105, and the objective lens 107, a pattern in the unit exposure area is drawn.

On the other hand, to perform drawing between unit exposure areas,
First, one unit exposure area and a unit exposure area adjacent thereto are designated. Subsequently, the coordinate conversion data of the positions and heights of the marks in the two unit exposure areas are extracted from the mark position / height data storage unit of the control computer 121 and transferred to the coordinate conversion unit 119. Here, coordinate conversion data between the two unit exposure areas is created from the two coordinate conversion data, and this is converted into the second buffer memory 113.
Transfer to.

Next, the drawing pattern data between the unit exposure areas is extracted from the drawing data storage unit 124 of the control computer 121, transferred to the first buffer memory 122, and further transferred to the arithmetic unit 110. .. Computing unit 110
Calculates the drawing coordinate data by performing the arithmetic processing of the drawing pattern data transferred from the first buffer memory 122, and converts the drawing coordinate data into a control signal to generate the molding signal generator 10.
9 to the main deflection control unit 111 and the sub-deflection control unit 114, respectively.

Main deflection control section 111, sub deflection control section 114
The objective lens control unit 12 corrects the drawing coordinate data in the unit exposure area based on the coordinate conversion data of the position and height of the mark in the unit exposure area, and based on the corrected drawing coordinate data. By controlling the main deflector 106, the sub deflector 105, and the objective lens 107, a pattern in the unit exposure area is drawn.

Then, by adding the above-mentioned error, drawing is performed so that the patterns in the unit exposure area are accurately superimposed. The pattern between the unit exposure areas is such that the above-mentioned error is reversed at each boundary so that a connection error does not occur between the unit exposure areas.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. Needless to say.

In the above embodiment, the case where the wiring is formed on the semiconductor wafer has been described, but the present invention can be applied to the case where the wiring is formed on the printed wiring board or the like.

[0072]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the present invention, it is possible to reduce the processing step of the insulating film and the conductive film in each step, so that the process margin such as photoresist coating, etching, and film deposition becomes large. As a result, fine wiring can be easily formed, so that the wiring density can be significantly improved.

(2) According to the present invention, by combining the optical reduction projection exposure method and the electron beam exposure method, it is possible to achieve both fine wiring and an exposure area, and to eliminate the restriction of the wiring area. Therefore, fine wiring can be easily formed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a main part of a semiconductor wafer showing each step of a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a flow chart showing a method of manufacturing a semiconductor integrated circuit device in the order of steps.

FIG. 3 is a diagram schematically showing the shape of a connection hole formed in an insulating film.

FIG. 4 is a diagram showing an overall configuration of an electron beam drawing apparatus.

FIG. 5 is a plan view of a semiconductor wafer showing an optical reduction exposure method.

FIG. 6 is an explanatory diagram showing a coordinate relationship between a unit exposure area and an electron beam exposure area of light reduction projection exposure.

FIG. 7 is a flowchart illustrating an electronic exposure method within a unit exposure area of optical reduction projection exposure.

FIG. 8 is a flowchart illustrating an electronic exposure method between unit exposure regions of light reduction projection exposure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 semiconductor wafer 2a insulating film 2b insulating film 3a connection hole 3b connection hole 4a conductive film 4b conductive film 5a wiring 5b wiring 5c lower layer wiring 5d upper layer wiring 100 electron beam drawing apparatus 101 XY stage 102 sample stage 103 electron beam source 104 beam former Reference numeral 105 Sub-deflector 106 Main deflector 107 Objective lens 108 Shaper controller 109 Molding signal generator 110 Calculation unit 111 Main deflection controller 112 Main deflection signal generator 113 Second buffer memory 114 Sub-deflection controller 115 Sub-deflection signal generator Part 116 Mark position detector 117 Height detector 118 Laser interferometer 119 Coordinate conversion part 120 Objective lens control part 121 Control computer 122 First buffer memory 122 123 Sample stage control part 124 Drawing data storage part 125 Light source 702 Orientation flag 731-736 exposure region 741 semiconductor chips Q ₁ semiconductor element Q ₂ semiconductor element

Claims (5)

[Claims] 1. A wiring below the insulating film by forming a connection hole in the insulating film deposited on a semiconductor wafer, depositing a conductive film on the insulating film, and then etching the conductive film. Alternatively, when a wiring connected to a semiconductor element is formed, a series of steps including deposition of the insulating film, formation of a connection hole, deposition of a conductive film and etching is repeated twice or more. Production method. 2. A connection hole having a large diameter along the extending direction of the wiring of the upper layer of the insulating film is provided above the connection hole having a large diameter along the extending direction of the wiring of the lower layer of the insulating film. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed. 3. The method according to claim 1, wherein after the connection hole is formed using a negative type or positive type photoresist, a wiring is formed using a photoresist opposite to the photoresist. A method for manufacturing the semiconductor integrated circuit device described. 4. When a semiconductor device pattern formed on a photomask is transferred onto a semiconductor wafer, a light reduction projection exposure method is used, and when a wiring pattern between the semiconductor devices is transferred onto the semiconductor wafer, 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein an electron beam exposure method is used. 5. When transferring a semiconductor device pattern formed on a photomask onto a semiconductor wafer by using an optical reduction projection exposure method, the semiconductor device pattern is transferred separately to a plurality of unit exposure regions, and the plurality of unit exposure regions are transferred. A method of manufacturing a semiconductor integrated circuit device, wherein an electron beam exposure method is used when the wiring pattern between the semiconductor elements extending over the unit exposure region of is transferred onto a semiconductor wafer.