JPH05144252A - Memory ic - Google Patents

Memory ic

Info

Publication number
JPH05144252A
JPH05144252A JP3307420A JP30742091A JPH05144252A JP H05144252 A JPH05144252 A JP H05144252A JP 3307420 A JP3307420 A JP 3307420A JP 30742091 A JP30742091 A JP 30742091A JP H05144252 A JPH05144252 A JP H05144252A
Authority
JP
Japan
Prior art keywords
memory
power supply
reference voltage
input
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3307420A
Other languages
Japanese (ja)
Inventor
Shizuo Ida
静男 井田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3307420A priority Critical patent/JPH05144252A/en
Publication of JPH05144252A publication Critical patent/JPH05144252A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To obtain a memory IC which can comply, even in terms of an interface, with a situation that many power supplies for a system are intermingled. CONSTITUTION:Selectors 6, 7 and a reference-voltage generation circuit 8 are provided at the inside of a memory IC 1. Outputs of the selectors 6, 7 are selected form the outside. Thereby, power-supply voltages of an input part 3 and an I/O part 4 can be decided. It is possible to obtain the memory IC which complies with a situation that power supplies for a system are intermingled.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電源電圧が混在するシ
ステムに適したメモリICに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory IC suitable for a system having mixed power supply voltages.

【0002】[0002]

【従来の技術】図2は従来のメモリICを示す図であ
る。1はメモリIC、2はメモリアレイとその周辺に必
要なセンスアンプ等を含めたメモリアレイ部、3はアド
レス関連の入力部、4はデータのI/O部、5は電源端
子である。なお、VCCは電源電圧を示す。
2. Description of the Related Art FIG. 2 is a diagram showing a conventional memory IC. Reference numeral 1 is a memory IC, 2 is a memory array section including a memory array and a sense amplifier necessary for the periphery thereof, 3 is an address-related input section, 4 is a data I / O section, and 5 is a power supply terminal. Note that V CC indicates a power supply voltage.

【0003】従来のICメモリ1は上記のように構成さ
れ、入力部3にアドレス情報が入力されると、その内容
に応じてI/O部4にデータを入力するかまたはI/O
部4から出力データを出すことになる。また、この時の
ICメモリ1の電源電圧VCCは電源端子5より印加さ
れ、メモリIC1の内部では、この電源電圧VCCが各ブ
ロック、つまり入力部3、メモリアレイ部2、I/O部
4に供給される。
The conventional IC memory 1 is configured as described above, and when address information is input to the input unit 3, data is input to the I / O unit 4 or I / O is input according to the content of the address information.
Output data will be output from the unit 4. The power supply voltage V CC of the IC memory 1 at this time is applied from the power supply terminal 5, in the internal memory IC1, the power supply voltage V CC is each block, i.e. the input unit 3, the memory array unit 2, I / O section 4 is supplied.

【0004】[0004]

【発明が解決しようとする課題】上記のような従来のメ
モリICでは、今後システムでの電源電圧の混在化に対
し単一電源しか対応できないという問題点があった。
The conventional memory IC as described above has a problem that only a single power supply can cope with the mixed power supply voltage in the system in the future.

【0005】本発明は、上記のような問題点を解消する
ためになされたもので、外部よりのセレクタ端子を設定
することにより、内部の電源電圧を自由に設定できるメ
モリICを得ることを目的とする。
The present invention has been made to solve the above problems, and an object thereof is to obtain a memory IC in which an internal power supply voltage can be freely set by setting a selector terminal from the outside. And

【0006】[0006]

【課題を解決するための手段】本発明に係るメモリIC
は、外部電源電圧を受けてメモリアレイ部用の基準電圧
を発生する基準電圧発生回路と、この基準電圧発生回路
からの基準電圧と外部電源電圧とが入力され、外部から
の選択信号を受けて出力を切り換えるセレクタを設けた
ものである。
Means for Solving the Problems A memory IC according to the present invention
Is a reference voltage generation circuit that receives an external power supply voltage and generates a reference voltage for the memory array section, and the reference voltage and the external power supply voltage from the reference voltage generation circuit are input to receive a selection signal from the outside. A selector for switching the output is provided.

【0007】[0007]

【作用】本発明においては、外部電源電圧が基準電圧発
生回路によって基準電圧に変換され、外部からの選択信
号によって出力が選択されるセレクタを介して外部電源
電圧または基準電圧が出力される。
In the present invention, the external power supply voltage is converted into the reference voltage by the reference voltage generating circuit, and the external power supply voltage or the reference voltage is output through the selector whose output is selected by the selection signal from the outside.

【0008】[0008]

【実施例】以下、この発明の実施例を図を用いて説明す
る。図1において、1〜5は従来メモリICと同じであ
る。6,7は外部からの選択信号を受けて各ブロックの
電源電圧を選択するセレクタであり、8は前記メモリア
レイ部2への電源電圧VCCを供給するための基準電圧発
生回路であり、9,10はセレクタ6,7をコントロー
ルするセレクタ入力端子である。
Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, 1 to 5 are the same as the conventional memory IC. Reference numerals 6 and 7 are selectors for receiving a selection signal from the outside to select the power supply voltage of each block, 8 is a reference voltage generation circuit for supplying the power supply voltage V CC to the memory array section 2, and 9 , 10 are selector input terminals for controlling the selectors 6, 7.

【0009】すなわち、このように構成された本実施例
のメモリICにおいては、内部の基準電圧発生回路8で
外部電源より低い基準電圧VCCを発生させてメモリアレ
イ部2に供給して動作させる構成としているので、回路
電流の削減が可能になっている。また、セレクタ入力端
子9,10に入力する選択信号によりセレクタ6,7の
出力の組み合わせとして4通り選択することができる。
例えば、セレクタ6,7が共にA側を選択した場合は、
入力部3、I/O部4の電源が内部の基準電圧に接続さ
れることになり、この時、メモリIC1内はすべて同一
電源とする。また、セレクタ6,7が共にB側に接続さ
れた場合は、入力部3、I/O部4が同一の外部電源と
なり、メモリアレイ部2だけが内部基準電圧となる。ま
た、セレクタ6,7がそれぞれA,Bを排他的に選択す
ると、入力部3とメモリI/O部4は別々の電源で動作
することになる。メモリIC1の基本動作としては、従
来ICと同じであり、アドレスの情報によりI/O部4
のデータが入出力されるシステムで2電源を使用してい
た場合、そのインタフェースにおいて自由に入力部3、
I/O部4の電源を選択できる。
That is, in the memory IC of the present embodiment having such a configuration, the internal reference voltage generation circuit 8 generates the reference voltage V CC lower than the external power supply and supplies it to the memory array section 2 for operation. Because of the configuration, it is possible to reduce the circuit current. In addition, it is possible to select four combinations of outputs of the selectors 6 and 7 according to selection signals input to the selector input terminals 9 and 10.
For example, when the selectors 6 and 7 both select the A side,
The power supplies of the input unit 3 and the I / O unit 4 are connected to the internal reference voltage, and at this time, the same power supply is used in the memory IC1. When both the selectors 6 and 7 are connected to the B side, the input section 3 and the I / O section 4 serve as the same external power source, and only the memory array section 2 serves as the internal reference voltage. When the selectors 6 and 7 exclusively select A and B, respectively, the input unit 3 and the memory I / O unit 4 operate with different power supplies. The basic operation of the memory IC1 is the same as that of the conventional IC, and the I / O unit 4 is
If two power supplies are used in the system that inputs and outputs the data, the input unit 3,
The power source of the I / O unit 4 can be selected.

【0010】なお、上記実施例は、2電源電圧で説明し
たが、電源数はこの限りではなく、複数本の場合にも同
様の構成の考え方でよく、上記実施例と同様の効果を奏
する。
Although the above embodiment has been described with two power supply voltages, the number of power supplies is not limited to this, and a similar concept may be applied to the case of a plurality of power supplies, and the same effect as the above embodiment can be obtained.

【0011】[0011]

【発明の効果】本発明は、以上説明したように、外部電
源電圧を受けてメモリアレイ部用の基準電圧を発生する
基準電圧発生回路と、この基準電圧発生回路からの基準
電圧と外部電源電圧とが入力され、外部からの選択信号
を受けて出力を切り換えるセレクタを設けたので、シス
テムの多電源対応でのICインタフェースを容易にで
き、さらには、メモリIC内部の低消費電力が図れる効
果がある。
As described above, the present invention provides a reference voltage generating circuit which receives an external power supply voltage and generates a reference voltage for a memory array section, and a reference voltage and an external power supply voltage from the reference voltage generation circuit. Since a selector for inputting and is input and receiving a selection signal from the outside to switch the output is provided, it is possible to easily realize an IC interface compatible with multiple power supplies of the system, and further, it is possible to achieve low power consumption inside the memory IC. is there.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のメモリICの一実施例を示す構成図で
ある。
FIG. 1 is a configuration diagram showing an embodiment of a memory IC of the present invention.

【図2】従来のメモリICを示す構成図である。FIG. 2 is a configuration diagram showing a conventional memory IC.

【符号の説明】[Explanation of symbols]

1 メモリIC 2 メモリアレイ部 3 入力部 4 I/O部 5 電源端子 6 セレクタ 7 セレクタ 8 基準電圧発生回路 9 セレクタ入力端子 10 セレクタ入力端子 1 Memory IC 2 Memory Array Section 3 Input Section 4 I / O Section 5 Power Supply Terminal 6 Selector 7 Selector 8 Reference Voltage Generation Circuit 9 Selector Input Terminal 10 Selector Input Terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 データが記憶されるメモリアレイ部と、
このメモリアレイ部内のデータの読み出し,書き込みを
行うメモリを特定するためのアドレスが入力されるアド
レス入力部と、前記メモリアレイ部に対するデータの入
出力が行われるデータのI/O部とを有するメモリIC
において、外部電源電圧を受けて前記メモリアレイ部用
の基準電圧を発生する基準電圧発生回路と、この基準電
圧発生回路からの基準電圧と前記外部電源電圧とが入力
され、外部からの選択信号を受けて出力を切り換えるセ
レクタを設けたことを特徴とするメモリIC。
1. A memory array unit for storing data,
A memory having an address input section for inputting an address for specifying a memory for reading and writing data in the memory array section and a data I / O section for inputting / outputting data to / from the memory array section IC
, A reference voltage generating circuit that receives an external power supply voltage to generate a reference voltage for the memory array section, a reference voltage from the reference voltage generation circuit and the external power supply voltage are input, and a selection signal from the outside is input. A memory IC having a selector for receiving and switching the output.
JP3307420A 1991-11-22 1991-11-22 Memory ic Pending JPH05144252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3307420A JPH05144252A (en) 1991-11-22 1991-11-22 Memory ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3307420A JPH05144252A (en) 1991-11-22 1991-11-22 Memory ic

Publications (1)

Publication Number Publication Date
JPH05144252A true JPH05144252A (en) 1993-06-11

Family

ID=17968845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3307420A Pending JPH05144252A (en) 1991-11-22 1991-11-22 Memory ic

Country Status (1)

Country Link
JP (1) JPH05144252A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007172812A (en) * 2005-12-22 2007-07-05 Samsung Electronics Co Ltd Semiconductor memory device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63207000A (en) * 1987-02-24 1988-08-26 Oki Electric Ind Co Ltd Semiconductor device
JPH02285811A (en) * 1989-04-27 1990-11-26 Seiko Epson Corp Semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63207000A (en) * 1987-02-24 1988-08-26 Oki Electric Ind Co Ltd Semiconductor device
JPH02285811A (en) * 1989-04-27 1990-11-26 Seiko Epson Corp Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007172812A (en) * 2005-12-22 2007-07-05 Samsung Electronics Co Ltd Semiconductor memory device

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