JPH05143057A - Dual-port ram control circuit for image processing - Google Patents

Abstract

PURPOSE:To enable high-speed operation and to enhance versatility by generating a DT clock at least at the end of a horizontal synchronizing period and when a down counter counts down to zero. CONSTITUTION:A DT cycle monitor circuit 4 is provided with a multiplexer(MPX) 11 which inputs a certain fixed value and a display address (Disp Adr). The circuit 4 monitors the DT cycle and then the DT clock can be generated in the horizontal period and when the counted value of the down counter 12 reaches 0. Therefore, when the size of a serial-out register(SOR) is 512 bits at the time of application to a CRT monitor with, for example, 1280X1024 resolution, the DT clock is generated even halfway in the scanning of a horizontal line and display data can be transferred before the SOR becomes empty, thereby enabling the high-speed operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual port RAM control circuit for image processing, and more particularly to a dual port RAM control circuit used as an image display buffer in an image display system in a personal computer, a workstation or the like.

[0002]

2. Description of the Related Art A dual port RAM 1 used as an image display buffer has a serial out register (SOR) 3 added to the output side of a memory cell array 2 of a normal dynamic RAM (DRAM), as shown in FIG. , DT (data transfer) cycle monitoring circuit 4 transfers display data from memory cell array 2 of DRAM to SOR 3 in response to a DT clock generated at the end of the horizontal synchronization period.

On the other hand, a CRT (not shown) used as a display, for example, displays a flickering screen unless the display data is sent at a constant cycle within the afterimage time. You must keep sending the display data. For example, in the case of a CRT monitor having a resolution of about 1280 × 1024, display data is transferred at a speed of about 100 MHz per dot. Normally, the access speed of the dual port RAM is 40 nsec to 25 nsec (25
MHz-40MHz), so multiple dual-port R
AM is used in parallel to obtain this 100 MHz speed. In any case, in the case of the CRT monitor having the above resolution, the display data is continuously read at a speed of about 40 nsec.

[0004]

By the way, the output of a 1M bit dual port RAM is usually x4 (4 bits).
In this case, the size of SOR3 of the dual port RAM 1 is 512 bits. This means that it is necessary to transfer the data from the memory cell array 2 of the main body DRAM to the SOR 3 again after the display data is read out 512 times at the longest. For example, the horizontal (horizontal) resolution is 1280. If so, the DT clock must be generated during the scanning of the horizontal line. However, in the conventional dual port RAM control circuit,
Since the DT clock is only generated at the end of the horizontal synchronization period, there is a problem that the above high speed operation cannot be supported.

When the area not used for display is provided at the horizontal end of the dual port RAM 1, the DT clock must be generated at the end of the horizontal synchronizing period, as described above. Such a case is a case where the area of the dual port RAM 1 is set larger than the display area and the processing such as panning can be performed by changing the display start address.

The present invention has been made in view of the above points, and an object thereof is to provide a dual port RAM control circuit for image processing, which has high versatility and can operate at high speed.

[0007]

In the dual port RAM control circuit for image processing according to the present invention, the DT cycle monitoring circuit for monitoring the DT cycle of the dual port RAM has a fixed value preset in synchronization with the SOR clock. Has a down counter for down counting, and generates the DT clock at least at the end of the horizontal synchronization period and when the down counter counts zero.

[0008]

In the image processing dual-port RAM control circuit having the above structure, by generating the DT clock at the end of the horizontal synchronization period and a relatively short period, the display data can be transferred before the SOR becomes empty, and the high speed operation is achieved. Is possible. Also, by setting a fixed value appropriately, dual port R
The versatility can be enhanced without sacrificing the performance (drawing efficiency) of the AM.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a DT cycle monitoring circuit in a dual port RAM control circuit for image processing according to the present invention. In the figure, the DT cycle monitoring circuit 4 according to the present invention is provided with a multiplexer (MPX) 11 having two inputs of a fixed value (for example, “32”) and a display address (Disp Adr). Synchronizes with the horizontal sync signal (H-sync) and selects and outputs the lower bit of the display address at the end of the period and a fixed value in other periods.

The value selected by the MPX 11 is supplied to the down counter 12. This down counter 12 is NA
Horizontal sync signal (H-syn) supplied via ND gate 13
c) Alternatively, the output value of the MPX11 is loaded in response to the output of the count "0", and the down count is performed in synchronization with the SOR clock which is the shift clock of SOR3 (see FIG. 2). The count “0” output of the down counter 12 or the horizontal synchronizing signal (H-sync) is output via the NAND gate 14 to D
It is output as the T clock.

According to the monitoring of the DT cycle by the DT cycle monitoring circuit 4 having the above-mentioned structure, the horizontal synchronization period (see FIG.
(See (A)) and the count value of the down counter 12 =
Since it is possible to generate DT clocks when 0 (see FIG. 3B), for example, when applied to a CRT monitor with a resolution of about 1280 × 1024, SOR3
When the size is 512 bits, the DT clock is generated even during the scanning of the horizontal line, and the display data can be transferred before the SOR3 becomes empty, so that the high speed operation becomes possible.

In this example, the DT clock is generated during the horizontal synchronization period, but it is sufficient that the DT clock can be generated at least at the end of the horizontal synchronization period. The point is that the display on the SOR3 is performed before the start of the display period. All that is required is that the data transfer has been completed.

By the way, in FIG. 2, the dual port RAM 1 is accessed by two systems of drawing and displaying. Then, the drawing is performed by random access, and in this example, 200n
It is assumed that the cycle time is around s. On the other hand, SOR3
Has a size of 512 bits, and the SOR clock is 4
When 0 × ns is set and 512 × (40 ns / 200 ns) is obtained, one DT cycle is performed almost every 100 drawing cycles. This DT cycle is one time, which is about the same as drawing. The drawing efficiency in this case is
1/100 compared to when no DT cycle arrives
Just worse.

Considering the case where the DT cycle arrives more frequently, for example, if the DT cycle arrives once every SOR clock 256, it becomes worse by 2/100 and the SOR clock 128 arrives. 4/10 if the DT cycle arrives once
It gets worse by 0, and once every SOR clock 64, D
When the T cycle arrives, it deteriorates by 8/100, when the DT cycle arrives at the SOR clock 32 once, it deteriorates by 16/100, and the DT cycle arrives at the SOR clock 16 once. 32/100 worse.

Special attention should be paid to the SOR
Even if the size of 3 becomes larger, the deterioration rate of the drawing efficiency does not change. Therefore, the DT cycle is 1
If set to about 28 to 32 (32 in this example),
It can be seen that versatility can be increased without sacrificing performance (drawing efficiency). In this example, S
The case where the OR clock is used at the performance limit has been described, but if the cycle of the SOR clock is reduced, the deterioration of the performance will be less.

On the other hand, as a counter that operates at high speed,
It is common to use a synchronous type such as look-ahead for carry. However, in this example, since it is sufficient to be able to detect at high speed only at the moment when the count value becomes zero, the down counter 12 is a ripple counter which is asynchronously controlled and has a configuration as shown in FIG. This ripple counter is configured to be operable at a speed for operating one bit and no matter how long the number of bits is. Further, although all the upper bits become zero and the least significant bit finally becomes zero, this state can be detected earliest.

For example, assuming that the down counter 12 is set to "4", that is, (100), the change of each bit at this time will be examined.
The content of the count is (100) → (011) → (01
It changes like 0) → (001) → (000). The second bit should operate at half the speed of the first bit,
It is understood that the third bit should operate at a speed 1/4 that of the first bit. Therefore, by using the ripple counter as the down counter 12, it is possible to detect zero very quickly.

In particular, as is apparent from FIG. 4, the respective outputs of the FFs (flip-flops) 21 _{1 to} 21 ₃ of the upper 3 bits are input to the NAND gate 23 via the AND gate 22, but the least significant the output of the FF 21 ₀ bits directly as input NAND gate 23, the transfer path of the least significant bit is configured to be the shortest, so that attained faster of zero detection.

[0019]

As described above, according to the present invention,
A DT cycle monitoring circuit that monitors a DT cycle of a dual port RAM has a down counter that counts down from a preset fixed value in synchronization with an SOR clock, and at the end of the horizontal synchronization period and when the down counter counts zero. With the configuration that generates the DT clock, the display data can be transferred before the SOR becomes empty, so that high-speed operation is possible and by setting a fixed value appropriately, the performance of the dual port RAM can be improved. The versatility can be improved without sacrificing much.

[Brief description of drawings]

FIG. 1 is a dual port RAM for image processing according to the present invention.
It is a block diagram which shows one Example of the DT cycle monitoring circuit in a control circuit.

FIG. 2 is a block diagram showing an example of a dual port RAM control circuit for image processing.

FIG. 3 is a waveform diagram for explaining the operation of the DT cycle monitoring circuit according to the present invention.

4 is a block diagram showing an example of a configuration of a down counter in FIG.

[Explanation of symbols]

 1 Dual Port RAM 2 Memory Cell Array (DRAM) 3 Serial Out Register (SOR) 4 DT Cycle Monitoring Circuit 11 Multiplexer (MPX) 12 Down Counter

Claims (2)

[Claims] 1. A data transfer cycle monitor circuit for generating a data transfer clock while monitoring a data transfer cycle of a dual port RAM, wherein the data transfer cycle monitor circuit uses a clock of a serial out register of the dual port RAM. A dual port for image processing, comprising a down counter for synchronously counting down from a preset fixed value, and generating the data transfer clock at least at the end of a horizontal synchronization period and when the down counter counts zero. RAM control circuit. 2. The dual port RAM control circuit for image processing according to claim 1, wherein a ripple counter is used as the down counter.