JPH0513687A - Semiconductor constant current source circuit - Google Patents

Abstract

PURPOSE:To provide a constant current source circuit with which a good current value can be set at the time of post-manufacture inspection without a terminal for an external bias required. CONSTITUTION:A semiconductor constant current source circuit comprises an FET 110, an FET 111 whose drain is connected with a drain of the FET 110 and a resistor net 150 containing a plurality of resistors 120 and pull-down terminals 130 between a source of the FET 110 and a source of the FET 111. Further the pull-down terminals 130 can be selectively connected to a negative terminal 160 of a power source being an external circuit. A gate of the FET 110, a gate of the FET 111 and a source of the FET 110 are connected with one another.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant current source circuit for an IC which can be adjusted at the time of inspection after manufacturing.

[0002]

2. Description of the Related Art A constant current source circuit is one that applies a constant current bias to a circuit block inside an IC. For example, it is widely used in a constant current source circuit of a differential circuit, a DC level shift circuit, and the like. In a compound semiconductor IC, the constant current source circuit is generally composed of an FET. The constant current source circuit composed of this FET utilizes good drain current characteristics in the saturation region of the FET, and has an advantage that the circuit structure becomes very simple. The circuit is configured as shown in FIGS. 6 to 9 and utilizes that the drain current (hereinafter, I _D ) becomes a constant value in the saturation region.

The circuit shown in FIG. 6 is the simplest, and the drain current (hereinafter referred to as I _DSS ) in the saturation region when the gate and source of the depletion type FET 610 are short-circuited (zero bias) is a constant current. It is the current value of the source circuit. In this figure, V _SS represents the negative side of the power supply, and I
_This indicates that the _DSS current is being drawn. Figure 7
The circuit shown in is a self-bias type circuit in which a resistor 620 is inserted between the gate and the source of the depletion type FET 610. The current value of this constant current source circuit is the FET.
Provided by the transfer static characteristic (I _D -V _GS characteristics) and the resistance value r in "V _GS = -r × I _D" and becomes I _D, FET
Is a bias condition that V _GS <0. Under this bias condition, when the drain conductance (g _d ) of the FET can be reduced, the constant current source circuit has better performance than the circuit of FIG. This figure shows that the current I _D is being drawn. The constant current source circuit shown in FIG. 8 is such that an IC is provided with a terminal 730 for external bias, and a predetermined gate bias voltage is externally applied to this terminal. The bias voltage is a resistor 84 between the externally applied voltage and the V _SS potential.
The pressure is applied at a partial pressure of 0,850. Both of the depletion type and the enhancement type FETs can be used for these, and they are a dual power source type constant current source circuit. In the circuits of these figures, the current of I _D which is generated by the transfer static characteristic and the gate-source voltage (hereinafter, V _GS ) is absorbed.

The constant current source circuit composed of these FETs is
It has the feature that it can be configured with a small number of elements.

[0005]

Recently, compound semiconductor ICs have been proposed.
Is being actively developed, and the degree of integration is also improving. I
In C, the constant current source is a basic circuit element, and FET
The constant current source means is important even in a compound semiconductor IC using as a basic element. Although the constant current source is configured using the FET as described above, the compound semiconductor IC has a problem in that the controllability of I _DSS is difficult and its variation is large due to various causes. Since the circuits of FIGS. 6 and 7 are easily affected by the variation of I _DSS , the constant current bias to other circuit blocks inside the IC varies and the yield decreases. The circuits of FIGS. 8 and 9 can adjust the current by an externally applied voltage, but require an external bias terminal and require fine adjustment on the user side. Against this background, particularly in the compound semiconductor IC, there has been a demand for a constant current source circuit means capable of adjusting to an optimum current value desired at the time of inspection after manufacturing and not requiring an extra external adjusting terminal.

In view of the above-mentioned points, the present invention has an object to provide a semiconductor constant current source circuit capable of setting a good current value at the time of post-manufacturing inspection without requiring a terminal for external bias in the IC. And

[0007]

SUMMARY OF THE INVENTION A current source circuit according to the present invention comprises a first FET having a gate and a source connected to each other, a drain connected to the first FET and a gate connected to the source of the first FET. A second FET connected to
The second FET is provided with a plurality of resistors between the source and the gate of the second FET and a resistor network including terminals provided at end points of the resistors. Further, these terminals can be selectively connected to an external circuit.

[0008]

The resistance value between one of the terminals of the resistor network and the source of the second FET changes if the terminal changes. Further, the resistance value between one of the terminals of the resistor network and the gate of the second FET also changes if the terminal changes. When the terminal of the resistor network is pulled down to the power supply on the low potential side, the second FE
The gate of T is biased by the voltage drop caused by the drain current of the first FET and the resistance between the terminal of the resistor network and the gate of the second FET. By selectively pulling down the terminals of the resistor network to the power supply on the low potential side,
The drain current of the second FET can be set to a desired current value by changing the resistance value between the terminal and the source and gate of the second FET and changing the bias point of the second FET.

[0009]

Embodiments of the present invention will be described with reference to FIGS. FIG. 1 shows a constant current source circuit according to the first embodiment of the present invention. The constant current source circuit of FIG.
0, a FET 111 whose drain is connected to the FET 110, a source of the FET 110, and a FET 111
And a resistor network 150 including a plurality of resistors 120 and pull-down terminals 130. In addition, one of the pull-down terminals 130 and a terminal 160 (hereinafter, V _SS terminal 160) on the negative side of the power supply (hereinafter, V _SS ) as an external circuit.
Bonding wires 140 are provided to connect to.

The FETs 110 and 111 are of the depletion type, and the gate and the source of the FET 110 are connected to the gate of the FET 111. FET 110,1
11 is operating in the saturation region. In the resistance network 150,
A large number of resistors 120 are connected in series, and each resistor 12
A pull-down terminal 130 is provided at the end point of 0. The same reference numeral “120” is used for each resistor 120, but the size of each resistor is not necessarily the same and F
Since it is used for ET gate bias (at most ± several hundred mV), a relatively low resistance is used. One of the pull-down terminals 130 at these end points is connected to the V _SS terminal 160 by a bonding wire 140.

Regarding the adjustment of the current of this constant current source circuit,
Conceptually, this is done by adjusting the variable resistor shown in the circuit of FIG. This will be schematically described with reference to FIG.

For simplicity, V _SS terminal 160 and FET 11
The resistance between the gate and the gate of R ₁ is R ₁ , V _SS terminal 160 and FE
The resistance between the source of T111 and the source is R ₂ . FET1
Assume that 10 and 111 have the same characteristics (that is, the threshold voltage and the gate width are the same). Assuming that R ₁ = R ₂ = R, since the FETs 110 and 111 have the same characteristics, they operate at the same bias point (V _GS , V _DS ) and the FET 1
Drain current of 10,111 (I ₁ , I ₂ (=
I _DSS )) and the source potential are equal. The current of the constant current source circuit at this time is “I _DSS × 2”. This is the equilibrium point.

From this equilibrium point, R ₁ and R ₂ are displaced,
When “R ₁ = R + Δr, R ₂ = R−Δr”, FE
The current flowing through T110 is in the saturation region and VGS = 0.
Since it is (constant), it hardly changes. The source potential of the FET 110, that is, the gate potential of the FET 111 increases only when R ₁ increases, that is, Δr · I _DSS increases. FET 11
The source potential of 1 is the amount of decrease in R _2, that is, Δr
・ Although it contributes to the reduction of I _DSS , this causes FET
Since the gate-source voltage and the drain-source voltage of the FET 111 increase, the drain current I ₂ increases, and as a result, the source potential of the FET 111 also contributes to the increase. If the increment of I ₂ is Δi, then g _m , g
Letting _d be the mutual conductance of the FET 111 and 0 drain conductance, the following relationship holds: Δi = g _m (2 · I _DSS · Δr) + g _d · I _DSS · Δr = (2 · g _m + g _d ) · I _DSS · Δr To do. 2 · I _DSS · Δr is a change in the gate-source voltage of the FET 111 due to changes in R ₁ and R ₂ , and I _DSS · Δr is also the drain of the FET 111-
This is the change in the voltage between the sources. The contribution of Δi to the change in the source potential of the FET 111 is R ₂ · Δi = (R−Δr) · Δi = R · I _DSS · (2 · g _m + g _d ) · Δr, and, eventually, the source potential of the FET 111. the net change is a _{R · I DSS · (2 ·} g m + g d) · Δr-I DSS · Δr = {R · (2 · g m + g d) -1} · I DSS · Δr. If a sufficiently small value of R that satisfies R · (2g _m + g _d ) << 1 is selected here, the source potential of the FET 111 will decrease by about I _DSS · Δr in the net. Does not contradict. After all, F by Δr
The gate voltage of ET111 rises, the gate-source voltage increases (I ₂ increases), and the current of the constant current circuit increases. In the case of reducing the current of the constant current source circuit, it may be replaced with “Δr → −Δr ′” in the above equation. That is, "R
₁ = R−Δr ′, R ₂ = R + Δr ′ ″. In this way, by increasing or decreasing R ₁ and R ₂ , the current of the constant current source circuit can be changed. In an actual circuit, the FETs 110 and 111 are not always required.
Need not have the same characteristics. For example, as another embodiment, as shown in FIG.
The gate width ratio “W1: W2” of T110 and 111 is set to “1:
k ”, and“ R ₁ : R ₂ = k: 1 ”. By doing so, the same consideration can be made. Also in this case, by increasing or decreasing R ₁ and R ₂ ,
The current of the constant current source circuit can be changed.

In the adjustment of the constant current source circuit of FIG. 1, in the post-manufacturing inspection stage, the current value when the pull-down terminal 130 and the V _SS terminal 160 are connected in order from the left with a probe is measured and the Pull-down terminal 13 with the current value of
0 is connected to the V _SS terminal 160 by the bonding wire 140. By making such adjustments, the FET
Since the variation in I _DSS can be absorbed and the current value can be adjusted to a desired value, the process margin is increased and the IC manufacturing yield is improved. Especially, it is difficult to control the characteristics of FET
It is useful for s, InP type FET circuits. In addition, the user does not need to make adjustments, and it is not necessary to provide a terminal for external bias like the circuits shown in FIGS.
The number of terminals in the package can be reduced. This circuit is made monolithically in the IC, so FE
Widely applicable to T differential amplifier circuit, DC level shift circuit, etc.

Next, a second embodiment of the present invention will be described.

In the constant current source circuit of the second embodiment shown in FIG. 5, in the resistor network 550, the source of the FET 110 and the FET 111.
Is characterized in that R ₃ and R ₄ are provided between each of the sources and V _SS . Also in the adjustment of the constant current source circuit, adjustment is performed in the same manner as in the first embodiment described above, and the pull-down terminal 130 having the best current value is connected to the V _SS terminal 160 by the bonding wire 140. This is equivalent to the circuit of FIG. 1 in which R ₃ and R ₄ are connected in parallel between the source of the FET 110 and the source of the FET 111 and the V _SS terminal, but R ₃ and R ₄ are connected in parallel. Since it is connected, V _SS depends on the selection of the pull-down terminal 130.
There is an advantage that a change in the resistance value between the terminal 160 and the sources of the FETs 110 and 111 becomes small, and fine current adjustment becomes possible.

The present invention can be variously modified in addition to the above-described embodiments.

Regarding the resistance network, there are various circuit configurations depending on the degree of variation of the elements and the required specifications for adjustment. If the circuit can be adjusted efficiently and a good bias point can be given to the FET, the configuration will be different. It doesn't matter.

[0019]

As described above, according to the present invention, the drain current of the second FET is changed and the constant current source is changed by selecting the connection between the terminal of the resistor network and the external circuit during the post-manufacturing inspection. Since the circuit current is adjusted and variations in the FET can be absorbed by the adjustment, the process margin is improved and the IC manufacturing yield is improved. In addition, the user does not need to make adjustments, and an extra terminal such as an external bias terminal for adjustment can be omitted.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a circuit diagram for explaining the operation of the first embodiment of the present invention.

FIG. 4 is a circuit diagram for explaining the operation of the first embodiment of the present invention.

FIG. 5 is a circuit diagram of a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional example.

FIG. 7 is a circuit diagram of a conventional example.

FIG. 8 is a circuit diagram of a conventional example.

FIG. 9 is a circuit diagram of a conventional example.

[Explanation of symbols]

 110 ... FET 111 ... FET 120 ... Resistor 130 ... Pull-down terminal 150 ... Resistor network 550 ... Resistor network

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[Procedure amendment]

[Submission date] February 21, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 27/04 V 8427-4M

Claims (1)

Claim: What is claimed is: 1. A first F having a gate and a source connected to each other.
ET, a second FET whose drain is connected to the first FET and whose gate is connected to the source of the first FET, and a plurality of resistors between the source and the gate of the second FET. A semiconductor constant current source circuit, comprising: a resistor network composed of terminals provided at the end points of the resistors, the terminals being selectively connectable to an external circuit.