JPH05136663A - Waveform response improving circuit - Google Patents

Abstract

PURPOSE:To shape an input signal with high quality by implementing a prescribed arithmetic operation from an input signal and the output signals of two delay means. CONSTITUTION:A delay means 1 delays an input signal and the signal is outputted to a delay means 2, a computing element 26, a maximum value selecting means 6, a minimum value selecting means 7, subtractors 9, 10, and an adder 13. The means 2 receives the output of the means 1 and delays the signal by the delay time of the means 2 and outputs the result to the computing element 26 and the means 6, 7. The input signal and the output signals of the means 1, 2 are given to the computing element 26, from which the quadratic differentiation waveform of the output of the means 1 is extracted and it is outputted to an amplitude adjustment means 8. The means 8 adjusts the output of the computing element 26 and outputs the result to a median selection means 27. The means 6 selects the maximum value of the outputs of the means 1, 2 and outputs the selected value to the subtractor 9, and the means 7 receives the input signal and the output signals of the means 1, 2 and outputs a selected minimum value to the subtractor 10 respectively. The subtractor 9 subtracts the output of the means 1 from the output of the means 6 and gives the result to the means 27 and similarly the subtractor 10 subtracts the output of the means 1 from the output of the means 7 and gives the result to the means 27. Thus, the input signal is shaped with high quality.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform response improving circuit capable of improving a waveform response without a preshoot which induces a synchronization disturbance and an overshoot which causes a white contour on a screen. Is.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional waveform response improving circuit. In FIG. 6, 1 is a first delay means for delaying an input signal for a fixed time, 2 is a second delay means for delaying an output signal of the first delay means 1 for a fixed time, and 3 is a first delay means. Is a first subtractor that subtracts the input signal from the output signal of the delay means 1, and 4 is a second subtractor that subtracts the output signal of the second delay means 2 from the output signal of the first delay means 1. Is.

Reference numeral 5 is a first adder for adding the output signal of the first subtractor 3 and the output signal of the second subtractor 4. The output signal amplitude of the first adder 5 is amplitude adjusting means 8
By this, it can be changed arbitrarily. The second adder 13 is adapted to add the output means of the first delay means 1 and the output signal of the amplitude adjusting means 8.

Next, the operation will be described. The input signal 1a {shown by the solid line in FIG. 7 (a)} is subtracted from the output signal 2a {shown by the broken line in FIG. 7 (a)} of the first delay means 1 by the first subtractor 3 to obtain the first The output signal 2a of the second delay means 2 is subtracted from the output signal 2a of the second delay means 2 (shown by the alternate long and short dash line in FIG. 7A) by the second subtractor 4, and the respective output signals are subjected to the first addition. The second differential waveform 6a of the output signal of the first delay means 1 is added by the adder 5 (FIG. 7).
(Shown in (b)) is extracted, and the amplitude of this waveform is arbitrarily changed by the amplitude adjusting means 8 and added to the output signal 2a of the first delay means 1 by the adder 13 to obtain the waveform shown in FIG.
Is the waveform input signal 2a shown by the broken line in FIG. 7 (c). } Is obtained.

[0005]

Since the conventional waveform response improving circuit is constructed as described above, for example, when an attempt is made to improve the rising portion of the output signal waveform, the preceding stage of the rising portion of the output signal waveform is considered. Pre-shoot, and also overshoot in the latter stage,
There is a problem that on-screen pre-shoot induces synchronization disturbance, and over-shoot induces a white contour at the rising portion of the waveform, which deteriorates the image quality. As approximation techniques, there are JP-A-62-133871 and JP-A-2-182803.

The present invention has been made in order to solve the above problems. For example, even when an attempt is made to improve the rising portion of the output signal, a preshoot is provided before the rising portion of the waveform of the output signal. It is an object of the present invention to obtain a waveform response improving circuit which can prevent an overshoot in the subsequent stage and can shape an input signal waveform with high quality.

[0007]

A waveform response improving circuit according to a first aspect of the present invention selects a maximum value of an input signal, an output signal of a first delay means and an output signal of a second delay means. Maximum value selecting means, minimum value selecting means for selecting the maximum value of the input signal, the output signal of the first delay means and the output signal of the second delay means, and the first delay from the output signal of the maximum value selecting means A first subtractor for subtracting the output signal of the means, a second subtractor for subtracting the output signal of the first delay means from the output signal of the minimum value selecting means, the input signal and the output of the first delay means An arithmetic unit for extracting a second derivative waveform of the output signal of the first delay unit from the signal and the output signal of the second delay unit, an output signal of this arithmetic unit, an output signal of the first subtractor, and a second Intermediate value selecting means for selecting an intermediate value with the output signal of the subtractor of It is provided with a an adder for adding the output signals of the first delay means stages.

According to the second aspect of the present invention, the waveform response improving circuit selects the maximum value of the input signal, the output signal of the first delay means and the output signal of the second delay means. Means for selecting the maximum value of the output signal of the first delay means, the output signal of the second delay means and the output signal of the third delay means, and the second delay means of the second delay means. Third maximum value selecting means for selecting maximum values of the output signal, the output signal of the third delay means and the output signal of the fourth delay means, the input signal, the output signal of the first delay means and the second The first minimum value selecting means for selecting the minimum value of the output signal of the delay means, the minimum value of the output signal of the first delay means, the output signal of the second delay means and the output signal of the third delay means are displayed. Second minimum value selecting means for selecting, output signal of second delay means and output signal of third delay means Third minimum value selecting means for selecting the minimum value of the output signal of the fourth delay means, output signal of the first maximum value selecting means, output signal of the second maximum value selecting means, and third maximum value. Fourth selecting the minimum value of the output signal of the selecting means
Minimum value selecting means, a first subtractor for subtracting the output signal of the fourth maximum value selecting means from the output signal of the second maximum value selecting means, and a first subtracter for outputting the output signal of the second minimum value selecting means. A second subtractor for subtracting the output signal of the minimum value selection means of 4;
Intermediate value selecting means for selecting an intermediate value among the output signal of the arithmetic unit, the output signal of the first subtractor and the output signal of the second subtractor, the output signal of the intermediate value selecting means and the second delay means. And an adder for adding the output signal of the.

[0009]

According to the first aspect of the invention, the maximum value selecting means causes the input signal, the output signal of the first delay means and the second signal.
The maximum value of the output signal of the delay means is selected, and the minimum value selection means selects the input signal, the output signal of the first delay means and the second value.
The minimum value of the output signal of the delay means is selected, and the output signal of the first delay means is subtracted from the output signal of the maximum value selection means by the first subtractor to form the first differential waveform, and the minimum The output signal of the first delay means is subtracted from the output signal of the value selection means by the second subtractor to form a second differential waveform, and the input signal and the outputs of the first and second delay means are given by the arithmetic unit. A third differential waveform is formed from the signal and the second differential waveform of the first delay means, and the first to third differential waveforms are selected by the intermediate value selecting means to form the fourth differential waveform. The fourth differential waveform is added to the output signal of the first delay means by an adder,
This improves the waveform so that there is no preshoot or overshoot.

According to the second aspect of the invention, the first maximum value selecting means selects the maximum value of the input signal and the output signals of the first and second delay means, and the second maximum value selecting means. The maximum value of the output signals of the first to third delay means is selected, and the maximum value of the output signals of the second to fourth delay means is selected by the third maximum value selection means. The minimum value selecting means selects the minimum value of the input signal and the output signals of the first and second delay means, and the second minimum value selecting means selects the minimum value of the output signals of the first to third delay means. The third minimum value selecting means selects the minimum value of the output signals of the second to fourth delay means, and the fourth minimum value selecting means outputs the output signal of the first to third maximum value selecting means. The minimum value of the first minimum value is selected by the fourth maximum value selecting means. The minimum value of the stage or the third minimum value selecting means is selected, and the output signal of the fourth maximum value selecting means is subtracted from the output signal of the second maximum value selecting means by the first subtractor to obtain the first value. A differential waveform is formed, a second subtractor subtracts the output signal of the fourth minimum value selecting means from the output signal of the second minimum value selecting means to form a second differential waveform, and the second differential waveform is formed by the calculator. The output signals of the first to third delay means are calculated to form a third differential waveform, and the first to third differential waveforms are selected by the intermediate value selecting means to form a fourth differential waveform, By adding this fourth differential waveform to the second delay means by the adder, the waveform is improved without preshoot and overshoot.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a waveform response improving circuit of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of one embodiment thereof, and corresponds to the invention described in claim 1. In FIG. 1, the same parts as those in FIG. In FIG. 1, reference numeral 1 is a first delay means for delaying an input signal for a fixed time, and 2 is a second delay means for further delaying an output signal of the first delay means by the same fixed time as the first delay means 1. Is.

The output signal of the first delay means 1, the output signal of the second delay means 2 and the input signal are input to the arithmetic unit 27. The calculator 26 extracts a second-order differential waveform of the output signal of the first delay means 1 from the input signal, the output signal of the first delay means 1 and the output signal of the second delay means 2 to thereby adjust the amplitude. It is designed to be sent out to 8. The amplitude adjusting means 8 can arbitrarily adjust the amplitude of the output signal of the calculator 26.

The maximum value of the input signal, the output signal of the first delay means 1 and the output signal of the second delay means 2 is selected by the first maximum value selecting means 6. Similarly, the minimum value of the input signal, the output signal of the first delay means 1 and the output signal of the second delay means 2 is selected by the first minimum value selection means 7.

A third subtractor 9 subtracts the output signal of the first delay means 1 from the output signal of the first maximum value selection means 6. Also, the first minimum value selecting means 7
The output signal of the first delay means 1 is subtracted from the output signal of the above by the fourth subtraction means 10.

The intermediate value of the output signal of the amplitude adjusting means 8, the output signal of the third subtracting means 9 and the output signal of the fourth subtracting means 10 is selected by the intermediate value selecting means 27 and the second value is selected. It is designed to output to the adder 13. The second adder 13 is configured to add the output signal of the intermediate value selection means 27 and the output signal of the first delay means 1.

Next, the operation will be described. The first delay means 1 delays the input signal by a predetermined delay time, and then the second delay means 2, the calculator 26, the first maximum value selection means 6, the first minimum value selection means 7, and the third delay means 2. It outputs to the subtractor 9, the fourth subtractor 10, and the second adder 13, respectively.

The second delay means 2 inputs the output signal of the first delay means 1 and further delays the output signal of the first delay means 1 with the same delay time as that of the first delay means 1 to make an arithmetic unit. Two
6, the first maximum value selecting means 6 and the first minimum value selecting means 7.

The calculator 26 inputs the input signal, the output signal of the first delay means 1 and the output signal of the second delay means 2 and outputs the output signal of the first delay means 1 as a second derivative waveform. Output to the amplitude adjusting means 8. The amplitude adjusting means 8 is a calculator 26.
The intermediate value selecting means 27 by appropriately adjusting the amplitude of the output signal of
Output to.

Further, the first maximum value selecting means 6 selects the maximum value of the input signal, the output signal of the first delay means 1 and the output signal of the second delay means 2 and performs the third subtraction. The first minimum value selection means 7 selects the minimum value of the input signal, the output signal of the first delay means 1 and the output signal of the second delay means 2 and the third subtraction is performed. Output to the container 10.

The third subtractor 9 is the first maximum value selecting means 6
The output signal of the first delay means 1 is subtracted from the output signal of 1 and the subtraction result is output to the intermediate value selection means 27. Similarly, the fourth subtractor 10 subtracts the output signal of the first delay means 1 from the output signal of the first minimum value selection means 7, and outputs the subtraction result to the intermediate value selection means 27.

The intermediate value selecting means 27 is an intermediate between the output signal of the amplitude adjusting means 8, that is, the output signal of the arithmetic unit 26, the output signal of the third subtractor 9 and the output signal of the fourth subtractor 10. The value is selected and output to the second adder 13. The second adder 13 adds the intermediate value selected by the intermediate value selecting means 27 and the output signal of the first delay means 1 and outputs the addition result.

Next, a concrete embodiment based on the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a block diagram specifically showing the internal configuration of the arithmetic unit 26 and the intermediate value selecting means 27 of FIG. In the description of the configuration in FIG. 2, the same parts as those in FIG.
The parts different from those in Fig. 1 will be mainly described.

In FIG. 2, the output signal of the first delay means 1 is adapted to be sent to the first subtractor 3 and the second subtractor 4, and is also input to the first subtractor 3. A signal is input, and the output signal of the second delay means 2 is also input to the second subtractor 2. The output signals of the first and second subtractors 3 and 4 are sent to the first adder 5. The output signal of the first adder 5 is sent to the amplitude adjusting means 8. Thus, the first subtractor 3 and the second subtractor 4
And the first adder 5 constitute an arithmetic unit 26.

The output signal of the third subtractor 9 is sent to the second minimum value selecting means 11. The output signal of the amplitude adjusting means 8 is also input to the second minimum value selecting means 11. The output signal of the second minimum value selecting means 11 is sent to the second maximum value selecting means 12. In the second maximum value selection means 12,
The output signal of the fourth subtractor 10 is also input. By the second minimum value selecting means 11 and the second maximum value selecting means 12, the intermediate value selecting means 27 shown in FIG.
Are configured.

Next, the operation will be described with reference to the waveform chart of FIG. First, the input signal 1a as shown in FIG. 3 (a) is converted into the first delay means 1, the first subtractor 3, the first
Is input to the maximum value selecting means 6 and the first minimum value selecting means 7, respectively. Other configurations are the same as those in FIG.

When the input signal 1a is input to the first delay means 1, the input signal 1a is delayed by a predetermined delay time and the output signal 2a is output as shown by the broken line in FIG. 3 (a). The output signal 2a is sent to the second delay means 2, and at the same time, the first and second subtraction means 3, 4, the first maximum value selection means 6, the first minimum value selection means 7, and the second addition. To the container 13.

The output 2a of the first delay means 1 is input to the second delay means 2 so that the second delay means 2
Then, further for a predetermined time, that is, the first delay means 1
3 (a) is delayed by the same delay time as that of FIG.
The output signal 3a is output as indicated by the alternate long and short dash line. This output signal 3a is sent to the second subtractor 4, the first maximum value selecting means 6 and the first minimum value selecting means 7.

The first subtractor 3 to which the output signal 2a of the first delay means 1 and the input signal 1a are input, subtracts the input signal 1a from the output signal 2a of the first delay means 1 to obtain the signal shown in FIG.
The output signal 4a shown in (b) is output to the first adder 5. That is, (2a-1a) is subtracted.

Further, the second subtractor 4 is the first delay means 1
The output signal 3a of the second delay means 2 is subtracted from the output signal 2a. That is, (2a-3a) is subtracted. The output signal 4a of the first subtractor 3 and the output signal 5a of the second subtractor 4 are sent to the first adder 5.

As a result, the first adder 5 adds the output signal 4a of the first subtractor 3 and the output signal 5a of the second subtractor 4, that is, (4a + 5a). The amplitude of the output signal 6a of the first adder 5 can be arbitrarily changed by the amplitude adjusting means 8.

On the other hand, the input signal 1a, the output signal 2a of the first delay means 1 and the output signal 3a of the second delay means 2 are input to the first maximum value selection means 6, and these output signals are output. The maximum value is selected and output to the third subtractor 9.

Similarly, the first minimum value selecting means 7 selects the minimum value of the input signal 1a, the output signal 2a of the first delay means 1 and the output signal 3a of the second delay means 2, and the 4 to the subtracter 10.

The third subtractor 10 outputs the output signal 2a of the second delay means 2 from the output signal of the first maximum value selection means 6.
Is subtracted, and the output signal 7a as shown by the solid line in FIG. 3 (e) is output to the second minimum value selecting means 11. This third
The output signal 7a of the subtractor 9 is equal to max (1a, 2a, 3
It is represented as a) -2a.

The fourth subtractor 10 subtracts the output signal 2a of the first delay means 1 from the output signal of the first minimum value selection means 7, and outputs the output signal 8a as shown by the solid line in FIG. 3 (f). Is transmitted to the second maximum value selecting means 12. The output signal 8a of the fourth subtractor 10 is min (1a, 2a, 3a) -2.
It is expressed as a.

The second minimum value selecting means 11 selects the minimum value of the output signal of the amplitude adjusting means 8 and the output signal 9a of the third subtractor 9, and the output signal 9a is indicated by the broken line in FIG. 3 (f). It is output as shown and sent to the second maximum value selection means 12. The output signal 9a of the second minimum value selecting means 11 is m.
It is represented as in (6a, 7a).

The second maximum value selecting means 12 selects the maximum value of the output signal 9a of the second minimum value selecting means 11 and the output signal 8a of the fourth subtractor 10, and as shown in FIG. 3 (g). Output signal 10a is output to the second adder 13. This output signal 10a is expressed as max (8a, 9a).

The second adder 13 adds the output signal 10a of the second maximum value selecting means 12 to the output signal 2a of the first delay means 1 to obtain the solid line in FIG. 3 (h). The output signal 11a. The broken line in FIG. 3 (h) is the output signal 2 a of the first delay means 1. As is apparent from the output signal 11a of the second adder 13, it can be seen that the waveform can be improved without preshoot and overshoot.

Next, another embodiment of the present invention will be described. This another embodiment corresponds to the invention described in claim 2, and FIG. 4 is a block diagram showing its configuration.

In FIG. 4, reference numeral 14 is a first delay means for delaying the input signal 1a for a fixed time, and the output signal of the first delay means 114 is sent to the second delay means 101. .. This second delay means 101 is the first
The delay means 114 delays the same fixed time, and its output is the first subtractor 103, the second subtractor 104, the third delay means 102, the first maximum value selecting means 116, and the first minimum. Value selecting means 119, second maximum value selecting means 11
7, the second minimum value selecting means 120, the third maximum value selecting means 118, and the third minimum value selecting means 121, respectively.

The output signal of the first delay means 114 is used in addition to the second delay means 101 and the first subtractor 10
3, the first maximum value selecting means 116, the first minimum value selecting means 119, the second maximum value selecting means 117, and the second minimum value selecting means 120.

The output signal of the second delay means 101 is further delayed by the third delay means 102 by the same constant delay time as the first delay means 114, and the output signal is output to the second subtractor 104 and the fourth subtracter 104. The delay means 115, the second maximum value selection means 117, the second minimum value selection means 120, the third maximum value selection means 118, and the third minimum value selection means 121 are respectively sent.

The fourth delay means 115 is the third delay means 1
02 output signal is further delayed by the same constant delay time as the first delay means 114, and the third maximum value selecting means 11
8, and is sent to the third minimum value selecting means 121.

The first subtractor 103 is the second delay means 10
The output signal of the first delay means 114 is subtracted from the output signal of 1, and the output signal is sent to the first adder 105.

Similarly, the second subtractor 104 subtracts the output signal of the third delay means 102 from the output signal of the second delay means 101, and outputs the output signal as the first adder 105.
It is designed to output to.

The amplitude of the output signal of the first adder 105 can be arbitrarily changed by the amplitude adjusting means 108. Also, the second adder 113 outputs the output signal of the second delay means 101 and the fifth maximum value selection means 1 described later.
12 output signals are added.

The first maximum value selection means 116 selects the maximum value of the input signal, the output signal of the first delay means 114, and the output signal of the second delay means 101, and outputs the fourth output signal.
Is sent to the minimum value selecting means 122.

The first minimum value selection means 119 selects the minimum value of the input signal, the output signal of the first delay means 114, and the output signal of the second delay means 101, and the fourth maximum value selection means. An output signal is sent to 123.

The second maximum value selection means 117 selects the maximum value of the output signal of the first delay means 114, the output signal of the second delay means 101 and the output signal of the third delay means 102. An output signal is sent to the fourth minimum value selecting means 122.

The second minimum value selection means 120 selects the minimum value of the output signals of the first to third delay means 114, 101, 102 and outputs the output signal as the fourth maximum value selection means 12.
3 is sent.

The third maximum value selecting means 118 selects the maximum value of the output signals of the second to fourth delay means 101, 102, 115 and outputs the output signal as the fourth minimum value selecting means 12.
It is designed to be sent out to 2.

The third minimum value selection means 121 is adapted to select the minimum value of the output signals of the second to fourth delay means 101, 102, 115 and send it to the fourth maximum value selection means 123. There is.

The fourth minimum value selecting means 122 outputs the output signal of the first maximum value selecting means 116, the output signal of the second maximum value selecting means 117 and the output signal of the third maximum value selecting means 118. The minimum value is selected and the output signal is sent to the fourth subtractor 125.

The fourth maximum value selecting means 123 outputs the output signal of the first minimum value selecting means 119, the output signal of the second minimum value selecting means 120 and the output signal of the third minimum value selecting means 121. Select the minimum value and output the output signal to the third subtractor 12
It is designed to output to 4.

The third subtractor 124 uses the output signal of the second maximum value selecting means 117 to determine the fourth maximum value selecting means 12 from the output signal.
The output signal of 3 is subtracted, and the output signal is sent to the fifth minimum value selecting means 111.

Further, the fourth subtracter 125 uses the output signal of the second minimum value selection means 120 to determine the fourth minimum value selection means 1
The output signal of 22 is subtracted and the output signal is sent to the fifth maximum value selecting means 112.

The fifth minimum value selecting means 111 is adapted to select the minimum value of the output signal of the amplitude adjusting means 108 and the output signal of the third subtractor 124 and send it to the fifth maximum value selecting means 112. ing.

The fifth maximum value selecting means 112 outputs the output signal of the fifth minimum value selecting means 111 and the fourth subtracter 125.
The maximum value of the output signal of the second adder 113
The output signal is sent to.

Next, the operation of the embodiment of FIG. 4 will be described with reference to the waveform chart of FIG. As indicated by the solid line in FIG. 5A, the input signal 201a is the first delay means 114,
First maximum value selecting means 116, first minimum value selecting means 1
19 are input respectively.

The input signal 201a is input to the first delay means 114.
By inputting, a predetermined fixed time is delayed,
As shown by the broken line in FIG. 5A, the output signal 114a is supplied to the second delay means 101, the first subtractor 103, the first maximum value selection means 116, the first minimum value selection means 119, and the second output means 114a.
Maximum value selection means 117 and second minimum value selection means 120
To send to each.

The second delay means 101 is the first delay means 1
The output signal 114a of 14 is delayed by the same fixed time as the first delay means 114 to output the output signal as shown by the alternate long and short dash line in FIG. 5A, the third delay means 102, the first and second subtractors 103. , 104, first maximum value selection means 116, first minimum value selection means 119, second maximum value selection means 117,
Second minimum value selection means 120, third maximum value selection means 1
18, third minimum value selecting means 121, second adder 11
Send to 3.

The first subtractor 103 includes the second delay means 10
1 output signal to the first delay means 114 output signal 11
4a is subtracted and the result of the subtraction is calculated by the first adder 105
To send to.

The third delay means 102 receives the output signal 101a of the second delay means 101, delays the same delay time as the first delay means 114, and outputs the output signal 102.
a is output as indicated by the solid line in FIG. 5A, and the second subtractor 104, the fourth delay means 115, the second maximum value selection means 117, the first minimum value selection means 120, and the third To the maximum value selecting means 118 and the third minimum value selecting means 121.

The second subtractor 104 is the second delay means 10
The output signal 102a of the third delay means 102 is subtracted from the output signal 101a of 1 and the subtraction result, that is,
The output signal 104a of the second subtractor 104 is sent to the first adder 105.

As a result, the first adder 105 outputs the output signal 103a of the first subtractor 103 and the second subtractor 104.
5 and the output signal 104a of FIG.
Output as shown in (b). This first adder 105
Output signal 105a is (101a-114a) + (10
2a-101a) = 103a + 104a = 105a. The output signal 105a of the first adder 105 is arbitrarily changed by the amplitude adjusting means 108.

Further, the fourth delay means 115 outputs the output signal 102a of the third delay means 102 to the first delay means 1
The output signal 115a is sent to the third maximum value selecting means 120 and the third minimum value selecting means 121 after being delayed by the same constant delay time as that of 14, as shown by the broken line in FIG.

On the other hand, the first maximum value selection means 116 has the input signal 201a and the output signal 114 of the first delay means 114.
a, the maximum value of the output signal 101a of the second delay means 101a is selected and the output signal 116a is sent to the fourth minimum value selection means 122.

The first minimum value selecting means 119 outputs the input signal 2
01a, the output signal 101a of the second delay means 101, and the minimum value of the output signal 101a of the second delay means 101, and the output signal and 119a are selected as the fourth minimum value selection means 122.
And to the second adder 124.

The second maximum value selection means 117 is the output signal 11 of the first to third delay means 114, 101, 102.
The maximum value of 4a, 101a and 102a is selected and the output signal 117a is sent to the fourth minimum value selecting means 122.

The second minimum value selection means 120 is the output signal 11 of the first to third delay means 114, 101, 102.
The minimum value of 4a, 101a and 102a is selected and the output signal 120a is output to the fourth maximum value selection means 123.

The third maximum value selection means 118 is the output signal 10 of the second to fourth delay means 101, 102, 115.
The maximum value of 1a, 102a and 115a is selected and the output signal 118a is sent to the fourth minimum value selecting means 122.

The third minimum value selecting means 121 is the output signal 10 of the second to fourth delay means 101, 102, 115.
The minimum value of 1a, 102a and 115a is selected and the output signal 121a is sent to the fourth maximum value selecting means 123.

The fourth minimum value selecting means 122 selects each of the output signals 116a, 117a, 118a of the first to third maximum value selecting means 116, 117, 118 to select the output signals shown in FIG.
The output signal 122a as shown in FIG.
Output to 25.

Here, assuming that max {201a, 114a, 101a} = A max {114a, 101a, 102a} = B max {101a, 102a, 115a} = C, the output signal of the fourth minimum value selecting means 122. 12
2a is represented as min {A, B, C}.

Further, the fourth maximum value selecting means 123 is the first
Or, the maximum value of each output signal 119a, 120a, 121a of the third minimum value selection means 119, 120, 121 is selected and the output signal 122a is sent to the third subtractor 124.

Similarly, in the case of the output signal 123a of the fourth maximum value selecting means 123, min {201a, 114a, 101a} = D min {114a, 101a, 102a} = E min {101a, 102a, 115a. } = F, the output signal 12 of the fourth maximum value selection means 123
3a is represented as max {D, E, F}. In the case of the input signal as shown in FIG. 5A, min {A, B, C} = max {D, E, F}, so that the output signal 1 of the fourth minimum value selecting means 122 is
22a is an output signal 123 of the fourth maximum value selecting means 123.
It is also a.

The third subtractor 124 subtracts the output signal 123a of the fourth maximum value selecting means 123 from the output signal 117a of the second maximum value selecting means 117, and outputs the output as shown in FIG. 5 (d). The signal 124a is supplied to the fifth minimum value selection means 11
Output to 1.

The fifth minimum value selecting means 111 has the output signal 105a of the first adder 105 and the output signal 12 of the third subtractor 124, which have been arbitrarily adjusted in amplitude by the amplitude adjusting means 108.
The minimum value of 4a is selected and the output signal 111a is sent to the fifth maximum value selection means 112.

Further, the fourth subtractor 125 subtracts the output signal 122a of the fourth minimum value selecting means 122 from the output signal 120a of the second minimum value selecting means 120, as shown in FIG.
The output signal as shown in (e) is the fifth maximum value selecting means 1
Send to 12. The output signal 112a of the fifth maximum value selection means 112 is min {114a, 101a, 102.
a}.

The fifth maximum value selecting means 112 outputs the output signal 111a of the fifth minimum value selecting means 111 and the fourth subtracter 1
The maximum value of the output signals 125a of 25
The output signal 112a as shown in FIG.
It outputs to 13. This output signal 112a is expressed as max {min (115a, 124a), 125a}.

The output signal 112a of the fifth maximum value selection means 112 is added to the output signal 101a of the second delay means 101 in the second adder 113, and the result is shown in FIG.
The output signal 10 of the second delay means 101 indicated by the alternate long and short dash line
1a, the output signal 113 shown by the solid line in FIG.
a is output from the second adder 113. This output signal 113a can be improved in waveform without preshoot and overshoot.

[0081]

As described above, according to the invention described in claim 1, the maximum value and the minimum value of the input signal and the output signals of the first and second delay means are selected, and the first value is selected from each of them. By subtracting the output signal of the delay means, the first and second differential waveforms are formed, and the input signal and the output signal of the first and second delay means are calculated to output the first delay means. A secondary differential waveform of the signal is extracted, and the secondary differential waveform is formed into a third differential waveform having an arbitrary amplitude by the amplitude adjusting means.
The intermediate value between the third differential waveform and the third differential waveform is selected to form the fourth differential waveform, and the fourth differential waveform is added to the output signal of the first delay means. When trying to improve the rising portion of the waveform of the output signal, the amplitude adjusting means can be used to set the rising edge of the waveform as desired. This has the effect of suppressing the delay and shaping the input signal to high quality.

According to the invention described in claim 2, the maximum value of the input signal and the output signal of the first and second delay means is selected by the first maximum value selecting means, and the maximum value of the input signal and the First and second
The minimum value of the output signal of the delay means is selected by the first minimum value selection means, and the maximum value of the output signal of the first to third delay means is selected by the second maximum value selection means. The minimum value of the output signal of the third delay means is selected by the second minimum value selection means, and the maximum value of the output signals of the second to fourth delay means is selected by the third maximum value selection means. The minimum value of the second to fourth delay means is selected by the third minimum value selecting means, and the first
To the minimum value of the output signal of the third maximum value selection means
Of the output signals of the first to third minimum value selecting means, and the fourth maximum value selecting means selects the maximum value of the output signals of the first to third minimum value selecting means. To subtract the output signal of the minimum value selecting means to form a first differential waveform, and subtract the output signal of the fourth maximum value selecting means from the output signal of the second maximum value selecting means to generate the second differential waveform. A waveform is formed, an operation is performed from the output signals of the first to third delay means to form a third differential waveform, and an intermediate value of the first to third differential waveforms is selected. Since it is configured to add with the output signal of the second delay means, it is possible to improve the waveform without the preshoot in the front stage of the rising portion of the waveform of the output signal and in the rear stage without overshoot, and to improve the input signal quality. It has the effect of shaping.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a waveform response improving circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of the embodiment shown in FIG.

FIG. 3 is a waveform diagram for explaining the operation of the embodiment of FIG.

FIG. 4 is a block diagram showing a configuration of a waveform response improving circuit according to another embodiment of the present invention.

5 is a waveform chart for explaining the operation of the embodiment of FIG.

FIG. 6 is a block diagram showing a configuration of a conventional waveform response improvement circuit.

FIG. 7 is a waveform diagram for explaining the operation of the waveform response improvement circuit of FIG.

[Explanation of symbols]

 1 1st delay means 2 2nd delay means 3 1st subtraction means 4 2nd subtraction means 5 1st addition means 6 1st maximum value selection means 7 1st minimum value selection means 8 Amplitude adjustment means 9 3rd subtraction means 10 4th subtraction means 11 2nd minimum value selection means 12 2nd maximum value selection means 13 2nd adder 101 2nd delay means 102 3rd delay means 103 1st Subtracting means 104 Second subtracting means 105 First adding means 108 Amplitude adjusting means 111 Fifth minimum value selecting means 112 Fifth maximum value selecting means 113 Second adding means 114 First delaying means 115 Fourth Delay means 116 First maximum value selecting means 117 Second maximum value selecting means 118 Third maximum value selecting means 119 First minimum value selecting means 120 Second minimum value selecting means 121 Third minimum value selecting means 12 Fourth minimum value selection unit 123 fourth maximum value selection unit 124 third of the subtractor 125 a fourth subtractor

Claims (2)

[Claims] 1. A first delay means for delaying an input signal for a fixed time, a second delay means for delaying an output signal of the first delay means for a further fixed time, the input signal and the first delay. Means for extracting a secondary differential waveform of the output signal of the first delay means from the output signal of the means and the output signal of the second delay means, and an amplitude capable of arbitrarily varying the amplitude of the output signal of the calculator Adjusting means, the input signal and the first
Maximum value selecting means for selecting the maximum value of the output signal of the delay means and the output signal of the second delay means, the input signal, the output signal of the first delay means, and the output of the second delay means. From a minimum value selecting means for selecting the minimum value of the signal, a first subtractor for subtracting the output signal of the first delay means from the output signal of the maximum value selecting means, and an output signal of the minimum value selecting means. A second subtractor for subtracting the output signal of the first delay means, an intermediate value between the output signal of the amplitude adjusting means, the output signal of the first subtractor and the output signal of the second subtractor A waveform response improving circuit comprising: an intermediate value selecting means for selecting and an adder for adding an output signal of the intermediate value selecting means and an output signal of the first delay means. 2. A first delay means for delaying an input signal by a fixed time, a second delay means for further delaying an output signal of the first delay means by a fixed time, and an output signal of the second delay means. Delaying means for delaying for a fixed time, a fourth delaying means for delaying the third delaying means for a further fixed time, an output signal of the first delaying means and an output signal of the second delaying means. An arithmetic unit for extracting a differential waveform of the output signal of the second delay unit from the output signal of the third delay unit, an amplitude adjusting unit capable of arbitrarily varying the output signal amplitude of the arithmetic unit, and the input A signal, a first maximum value selection means for selecting a maximum value of the output signal of the first delay means and an output signal of the second delay means, the input signal and an output signal of the first delay means Select the minimum value of the output signal of the second delay means. A first minimum value selecting means for selecting, a second maximum value for selecting the maximum value of the output signal of the first delay means, the output signal of the second delay means and the output signal of the third delay means. Value selecting means, second minimum value selecting means for selecting a minimum value of the output signal of the first delay means, the output signal of the second delay means, and the output signal of the third delay means; A third maximum value selecting means for selecting the maximum value of the output signal of the second delay means, the output signal of the third delay means and the output signal of the fourth delay means; and of the second delay means. An output signal, an output signal of the third delay means, and a third minimum value selecting means for selecting a minimum value of the output signal of the fourth delay means; an output signal of the first maximum value selecting means; A fourth signal selecting the output signal of the second maximum value selecting means and a minimum signal of the third maximum value selecting means. Small value selecting means, output signal of the first minimum value selecting means, output signal of the second minimum value selecting means, and fourth maximum value selecting selecting the minimum value of the third minimum value selecting means. Means and the second
First subtractor for subtracting the output signal of the fourth maximum value selecting means from the output signal of the maximum value selecting means, and the fourth minimum value selecting means from the output signal of the second minimum value selecting means. Second subtractor for subtracting the output signal of the above, and an intermediate value selection for selecting an intermediate value among the output signal of the amplitude adjusting means, the output signal of the first subtractor, and the output signal of the second subtractor. A waveform response improving circuit comprising means and an adder for adding the output signal of the intermediate value selecting means and the output signal of the second delay means.