JP2003169232A - Signal processing apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing apparatus that can more suitably correct a contour of a video signal. <P>SOLUTION: A multiplier circuit 39 multiplies an output signal from a minimum value circuit 35 with an output signal from a maximum value circuit 38 and an adder circuit 40 sums the output signals from the minimum value circuit 35 and the maximum value circuit 38. An output signal from the adder circuit 40 is fed to a switch circuit 44 via an amplifier circuit 45 and a limiter circuit 46. A level detection circuit 43 detects the level of the output signal from the adder circuit 40 and allows a signal of 0 level to be given to a multiplier circuit 47 when the absolute value of the level is within a range of a prescribed threshold value. The multiplier circuit 47 multiplies an output signal from the multiplier circuit 39 with an output signal from the switch circuit 44 and provides its output to an adder circuit 55. An adder circuit 55 multiplies the signal generated similarly and fed from the multiplier circuit 53 with an output signal from the multiplier circuit 47 to produce a correction signal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus and method, and more particularly, to a signal processing apparatus and method that enables more suitable contour correction of video signals.

[0002]

2. Description of the Related Art Conventionally, for example, in a television receiver or the like, a contour correction circuit for correcting the contour of a video signal has been used in order to improve image quality.

FIG. 1 is a block diagram showing a conventional contour correction circuit disclosed in JP-A-11-4364.
Further, FIG. 2 is a diagram showing an example of a waveform of a signal generated in each part of the contour correction circuit shown in FIG. In addition,
A to S shown in FIG. 1 respectively indicate that the signals of the waveforms A to S shown in FIG. 2 are detected at that position.

The video signal input to the input terminal 1 is supplied to the delay circuit 2A which delays the phase for a predetermined time (T), and the output signal of the delay circuit 2A similarly changes the phase for a predetermined time (T). It is further supplied to the delay circuit 2B which delays by T).

Therefore, when the video signal of waveform A shown in FIG. 2 is input to the input terminal 1, the waveform of the output signal of the delay circuit 2A becomes the waveform B of FIG. 2 and the waveform of the output signal of the delay circuit 2B becomes The waveform C in FIG. 2 is obtained.

The video signal (original signal) input to the input terminal 1 is also input to the subtraction circuit 3 and subtracted from the output signal of the delay circuit 2A. Then, by the subtracting circuit 3,
A signal of waveform D shown in is generated. Further, both the output signal of the delay circuit 2A and the output signal of the delay circuit 2B are input to the subtraction circuit 4, and the signal of the waveform E shown in FIG. 2 is generated.

The output signal of the subtraction circuit 3 is supplied to the minimum value circuit 5 and the maximum value circuit 6, and the output signal of the subtraction circuit 4 is supplied to the minimum value circuit 7 and the maximum value circuit 8. These minimum value circuit 5 to maximum value circuit 8 are respectively
0 level potential is supplied.

The minimum value circuit 5 and the minimum value circuit 7 are circuits for extracting the negative polarity part of the input signal, and the maximum value circuit 6 and the maximum value circuit 8 are respectively input. It is a circuit for extracting the positive polarity portion of the signal.

Therefore, in the minimum value circuit 5, the signal of the waveform F in FIG. 2, which is the negative polarity part of the output signal of the subtraction circuit 3, is extracted. Similarly, in the minimum value circuit 7, the subtraction circuit 4 is extracted. The signal of waveform H in FIG. 2, which is the negative polarity part of the output signal of FIG.

Further, in the maximum value circuit 6, the signal of the waveform G in FIG. 2, which is the positive polarity portion of the output signal of the subtraction circuit 3, is extracted, and similarly, in the maximum value circuit 8, the subtraction circuit 4 is extracted. 2 is the positive polarity portion of the output signal of FIG.
Signal is extracted.

The signals extracted by the minimum value circuit 5 and the maximum value circuit 8 are supplied to the multiplication circuit 9 and the addition circuit 10, respectively, and the maximum value circuit 6 and the minimum value circuit 7 are supplied.
The signal extracted by is supplied to the multiplication circuit 11 and the addition circuit 12, respectively.

In the multiplication circuit 9, a signal having the waveform J shown in FIG. 2 is generated and supplied to the multiplication circuit 13. Further, in the adder circuit 10, a signal having the waveform K shown in FIG. 2 is generated, and this is multiplied by the multiplication circuit 13 via the amplification circuit 14 and the limiter circuit 15 having a predetermined gain (−k1).
Is supplied to. In the limiter circuit 15, the portion of the input waveform in which the absolute value shows a value equal to or larger than a predetermined threshold (the portion having an amplitude larger than the predetermined threshold) is cut, and the value signal of the waveform L shown in FIG. 2 is cut. Is generated.

In the multiplication circuit 11, a signal having the waveform N shown in FIG. 2 is generated and supplied to the multiplication circuit 16. Further, in the adder circuit 12, the signal of the waveform O shown in FIG. 2 is generated, and the signal has a predetermined gain (-k1).
1 through the amplifier circuit 17 and the limiter circuit 18 of
6 is supplied. The limiter circuit 18 generates the ternary signal of the waveform P shown in FIG. 2 in the same manner as the limiter circuit 15.

In the multiplication circuit 13, the signal of the waveform M shown in FIG. 2 is generated based on the signal supplied from the multiplication circuit 9 and the signal supplied from the limiter circuit 15. Further, in the multiplication circuit 16, a signal having the waveform Q shown in FIG. 2 is generated based on the signal supplied from the multiplication circuit 11 and the signal supplied from the limiter 18.

Output signals from the multiplying circuit 13 and the multiplying circuit 16 are respectively amplified by a gain (k2) amplifying circuit 19 and a gain (k2 ′) amplifying circuit 20, and then supplied to an adding circuit 21. . Then, the adder circuit 21
As a result, the correction signal of the waveform R shown in FIG. 2 is generated,
It is supplied to the adder circuit 22.

In the adder circuit 22, the correction signal supplied from the adder circuit 21 and the output signal of the delay circuit 2A are added, and the contour-corrected signal is output to the output terminal 23.

By the operation of each circuit described above, for example, as shown in FIG.
Compared with the original signal of the waveform A shown in (1), the video signal of the waveform S whose rising and falling contours are sharply corrected is taken out.

Therefore, a more suitable image can be displayed by the image signal extracted by the contour correction circuit.

[0019]

By the way, the actual original signal contains a considerable amount of noise, and due to this noise, for example, 0 of the signal input to the amplifier circuit 14 is generated.
There is a problem that the output signal of the limiter circuit 15 corresponding to the portion near the level is not stable. Similarly, the output signal of the limiter 18 is not stable.

The waveform K shown in FIG. 3 shows the waveform of the output signal of the adder circuit 10 in the vicinity of time t in FIG. 2, and as shown by the solid line in the figure, it actually contains noise. The signal is generated by the adder circuit 10. Note that FIG.
The waveform indicated by the alternate long and short dash line represents an ideal waveform.

The waveforms L ', M', and S'shown in FIG. 3 are the output signal of the limiter circuit 15, the output signal of the amplifier circuit 19, and the output signal of the amplifier circuit 19, which are generated based on the signal of the waveform K shown in FIG. The waveforms of the output signals of the adder circuit 22 are shown.

As shown by the waveforms L ', M', and S'in FIG. 3, when the output signal of the adder circuit 10 contains noise, the phase in which the rising or falling of each signal appears is stable. And a false rising waveform is generated.

When such a video signal is generated, it is observed as horizontal jitter in the displayed video, and a good image quality cannot be obtained.

The waveforms M ″ and S ″ in FIG. 3 are the output signal of the amplifier circuit 19 and the output of the adder circuit 22 which are obtained by reducing the gain as compared with the waveforms M ′ and S ′. The respective waveforms of the signals are shown, and even in the case where the phase such as rising changes, it is possible to suppress to a level that does not affect the video signal. However, this means that the video signal generated by the contour correction circuit of FIG. 1 is not much different from the original signal, which is not preferable for the contour correction circuit.

The present invention has been made in view of such a situation, and is to enable more suitable contour correction.

[0026]

A first signal processing device of the present invention comprises a first delay means for delaying an original signal by a predetermined time to generate a first delay signal, and a first delay signal. Is further delayed by a predetermined time to generate a second delay signal, and based on the original signal and the first delay signal,
First to generate a first contour signal corresponding to the contour of the original signal
Generating means for generating a second contour signal corresponding to the contour of the original signal based on the first delay signal and the second delay signal, the first contour signal and the second contour signal. A first multiplying unit that multiplies the first contour signal and the second contour signal by adding the first contour signal and the second contour signal, and a first adding unit that generates the first addition signal by adding the first contour signal and the second contour signal. The addition signal of 1 is changed to 0
A value or a predetermined positive / negative value, which is ternarized to generate a first ternary signal, and the first ternary signal and the first multiplication signal are multiplied together to generate a second multiplication signal. The second multiplication means and the correction means for correcting the contour of the first delay signal based on the second multiplication signal are provided, and the arithmetic means has the level of the first addition signal within a predetermined threshold value. At this time, the first ternary signal is generated as 0.

The first generating means constitutes a first contour signal, and comprises a first rising contour signal corresponding to a rising contour of the original signal and a first rising edge signal corresponding to a falling contour of the original signal. The falling contour signal is generated, and the second generation means corresponds to the second rising contour signal corresponding to the rising contour of the original signal and the falling contour of the original signal, which form the second contour signal. A second falling contour signal is generated, and the first multiplying unit generates the first rising contour signal and the second rising contour signal, and the first falling contour signal and the second falling contour signal. A third multiplication signal, each of which is multiplied to form a first multiplication signal,
And a fourth multiplication signal, and the adding means adds each of the first rising contour signal and the second rising contour signal and the first falling contour signal and the second falling contour signal. , Constructing a first summed signal,
The second addition signal and the third addition signal are generated, and the calculating means forms the first ternary signal when the levels of the second addition signal and the third addition signal are within the threshold value. , The second ternary signal and the third ternary signal are generated as 0, respectively, and the second multiplication means outputs the third multiplication signal and the second ternary signal, and the fourth multiplication signal and the third ternary signal. Each of the three ternary signals is multiplied to generate a fifth multiplication signal and a sixth multiplication signal, which form a second multiplication signal, and the correction means includes:
It is possible to correct the first delay signal based on the signal obtained by adding the fifth multiplication signal and the sixth multiplication signal.

The signal processing method of the first signal processing apparatus according to the present invention delays the original signal by a predetermined time to generate a first delay signal, and a first delay signal to the predetermined delay step. A second delay step of further delaying by a time of, and generating a first contour signal corresponding to the contour of the original signal based on the original signal and the first delay signal. 1 generation step, a second generation step of generating a second contour signal corresponding to the contour of the original signal based on the first delay signal and the second delay signal, the first contour signal and the second contour signal A first multiplication step of multiplying two contour signals to generate a first multiplication signal; and an addition step of adding the first contour signal and the second contour signal to generate a first addition signal,
An operation step of ternarizing the first addition signal into a zero value or a predetermined positive / negative value to generate a first ternary signal;
Second multiplication step of multiplying the ternary signal by the first multiplication signal to generate a second multiplication signal, and a correction step of correcting the contour of the first delay signal based on the second multiplication signal. And the first ternary signal is generated as 0 when the level of the first addition signal is within a predetermined threshold by the processing of the calculation step.

The second signal processing apparatus of the present invention delays the original signal by a predetermined time to generate the first delayed signal.
And a second delay means for further delaying the first delay signal by a predetermined time to generate a second delay signal,
A first generation that generates a first rising contour signal corresponding to a rising contour of the original signal and a first falling contour signal corresponding to a falling contour of the original signal based on the original signal and the first delay signal. And a second rising edge signal corresponding to the rising edge of the original signal and a second falling edge signal corresponding to the falling edge of the original signal based on the first delay signal and the second delay signal. The second generation means for generating, the first rising edge signal and the second rising edge signal, and the first falling edge signal and the second falling edge signal are respectively multiplied to obtain a first multiplication signal. ,
And a multiplication means for generating a second multiplication signal, a first addition means for adding the first multiplication signal and the second multiplication signal to generate a first addition signal, and a first rising contour signal,
Second adding means for generating a second addition signal corresponding to a signal obtained by adding the first falling edge signal, the second rising edge signal, and the second falling edge signal; Arithmetic means for ternarizing the addition signal of 2 into 0 value or a predetermined positive / negative value to generate a ternary signal;
And a correction means for correcting the contour of the first delay signal on the basis of the obtained signal.
The arithmetic means is characterized in that the ternary signal is generated as 0 when the level of the second addition signal is within a predetermined threshold value.

The signal processing method of the second signal processing apparatus according to the present invention delays the original signal by a predetermined time to generate a first delayed signal, and a first delayed signal to a predetermined delay step. A second delay step of further delaying by a time of 1 to generate a second delayed signal, and a first rising contour signal corresponding to the rising contour of the original signal based on the original signal and the first delayed signal. , A first generation step of generating a first falling contour signal corresponding to the falling contour,
A second rising edge signal corresponding to the rising edge of the original signal and a second falling edge signal corresponding to the falling edge of the original signal based on the first delay signal and the second delay signal; Second generation step, the first rising edge signal and the second rising edge signal, and the first
Multiplying each of the falling contour signal and the second falling contour signal to generate a first multiplication signal and a second multiplication signal, and adding the first multiplication signal and the second multiplication signal. Then, a first addition step of generating a first addition signal, a first rising contour signal, a first falling contour signal, a second rising contour signal, and a second
A second addition step of generating a second addition signal corresponding to the signal obtained by adding the falling contour signals of
An operation step of ternarizing the second addition signal into a zero value or a predetermined positive / negative value to generate a ternary signal, and multiplying the first addition signal and the ternary signal, and based on the obtained signal First
And a correction step for correcting the contour of the delayed signal, the ternary signal being generated as 0 when the level of the second addition signal is within a predetermined threshold value by the processing of the calculation step. .

A third signal processing device of the present invention delays the original signal by a predetermined time to generate a first delayed signal.
And a second delay means for further delaying the first delay signal by a predetermined time to generate a second delay signal,
A first generation that generates a first rising contour signal corresponding to a rising contour of the original signal and a first falling contour signal corresponding to a falling contour of the original signal based on the original signal and the first delay signal. And a second rising edge signal corresponding to the rising edge of the original signal and a second falling edge signal corresponding to the falling edge of the original signal based on the first delay signal and the second delay signal. The second generation means for generating, the first rising edge signal and the second rising edge signal, and the first falling edge signal and the second falling edge signal are respectively multiplied to obtain a first multiplication signal. ,
And a multiplication means for generating a second multiplication signal, a calculation means for calculating a logical sum of the first multiplication signal and the second multiplication signal, a first rising contour signal, a first falling contour signal, The addition means for generating an addition signal corresponding to the signal obtained by adding the second rising edge signal and the second falling edge signal, and the addition signal having a three-valued value of 0 or a predetermined positive / negative value And calculating means for generating a ternary signal, and a correction means for multiplying the ternary signal by the calculation result of the logical sum by the calculating means and correcting the contour of the first delay signal based on the obtained signal. The arithmetic means is characterized in that the ternary signal is generated as 0 when the level of the addition signal is within a predetermined threshold value.

In the signal processing method of the third signal processing apparatus according to the present invention, the original signal is delayed by a predetermined time to generate a first delayed signal, and the first delayed signal is predetermined. A second delay step of further delaying by a time of 1 to generate a second delayed signal, and a first rising contour signal corresponding to the rising contour of the original signal based on the original signal and the first delayed signal. , A first generation step of generating a first falling contour signal corresponding to the falling contour,
A second rising edge signal corresponding to the rising edge of the original signal and a second falling edge signal corresponding to the falling edge of the original signal based on the first delay signal and the second delay signal; Second generation step, the first rising edge signal and the second rising edge signal, and the first
Multiplying the falling contour signal and the second falling contour signal respectively to generate a first multiplication signal and a second multiplication signal, and logics of the first multiplication signal and the second multiplication signal. Addition corresponding to a calculation step of calculating the sum and a signal obtained by adding the first rising edge signal, the first falling edge signal, the second rising edge signal, and the second falling edge signal. An addition step of generating a signal, an operation step of ternarizing the addition signal into a zero value or a predetermined positive / negative value, and generating a ternary signal,
A calculation step of multiplying the calculation result of the logical sum by the processing of the calculation step and the ternary signal, and correcting the contour of the first delay signal based on the obtained signal is provided. A ternary signal is generated as 0 when the level is within a predetermined threshold.

A fourth signal processing apparatus of the present invention delays an original signal by a predetermined time to generate a first delayed signal.
And a second delay means for further delaying the first delay signal by a predetermined time to generate a second delay signal,
A first generation that generates a first rising contour signal corresponding to a rising contour of the original signal and a first falling contour signal corresponding to a falling contour of the original signal based on the original signal and the first delay signal. And a second rising edge signal corresponding to the rising edge of the original signal and a second falling edge signal corresponding to the falling edge of the original signal based on the first delay signal and the second delay signal. A second generating means for generating, and a first output for outputting the first rising contour signal and the second rising contour signal when the logical product of the first rising contour signal and the second rising contour signal is not 0. Means and second output means for outputting the first falling edge signal and the second falling edge signal when the logical product of the first falling edge signal and the second falling edge signal is not 0. , First For the first rising edge signal output by the output means and the first falling edge signal output by the second output means, and the second rising edge signal and the second falling edge signal. Calculating means for respectively calculating the logical sum of the above, the calculation result of the logical sum of the first rising contour signal and the first falling contour signal by the calculating means, the second rising contour signal and the second falling contour signal. Multiplication means for multiplying the result of calculating the logical sum of to generate a multiplication signal, a first rising contour signal, a first falling contour signal, a second rising contour signal,
And an addition means for generating an addition signal corresponding to a signal obtained by adding the second falling edge signal, and the addition signal is ternarized into 0 value or a predetermined positive / negative value, and a ternary signal is obtained. The calculating means is provided with a calculating means and a correcting means for multiplying the multiplication signal and the ternary signal and correcting the contour of the first delay signal based on the obtained signal. The calculating means has a predetermined level of the addition signal. It is characterized in that a ternary signal is generated as 0 when it is within the threshold.

According to a fourth aspect of the signal processing method of the present invention, there is provided a first delay step of delaying an original signal by a predetermined time to generate a first delayed signal, and a time delay of the first delayed signal. By a second delay step of further delaying only by, to generate a second delayed signal, and the original signal and the first delayed signal,
A first rising edge signal corresponding to a rising edge of the original signal and a first generation step of generating a first falling edge signal corresponding to a falling edge; a first delay signal and a second delay signal; A second generation step of generating a second rising edge signal corresponding to the rising edge of the original signal and a second falling edge signal corresponding to the falling edge of the original signal; When the logical product of the rising contour signal and the second rising contour signal is not 0, the first output step of outputting the first rising contour signal and the second rising contour signal, the first falling contour signal and the first output step When the logical product of the two trailing edge contour signals is not 0, the second output step of outputting the first trailing edge contour signal and the second trailing edge contour signal, and the processing of the first output step Logical sum of the first rising contour signal output from the first output and the first falling contour signal output by the processing of the second output step, and the second rising contour signal and the second falling contour signal. Of the logical sum of the first rising edge signal and the first falling edge signal by the processing of the calculating step, the second rising edge signal and the second falling edge. A multiplication step of multiplying the result of calculating the logical sum of the contour signals to generate a multiplication signal, a first rising contour signal, a first falling contour signal, a second rising contour signal, and a second falling contour An addition step of generating an addition signal corresponding to the signal obtained by adding the signals, and ternarizing the addition signal into 0 value or a predetermined positive / negative value to generate a ternary signal And a correction step of correcting the contour of the first delay signal based on the obtained signal by multiplying the multiplication signal and the ternary signal, and the level of the addition signal is predetermined by the processing of the calculation step. It is characterized in that a ternary signal is generated as 0 when it is within the threshold value of.

In the first signal processing apparatus and method of the present invention, the original signal is delayed by a predetermined time, the first delayed signal is generated, and the first delayed signal is further delayed by the predetermined time. A second delayed signal is generated. A first contour signal corresponding to the contour of the original signal is generated based on the original signal and the first delayed signal, and the first delayed signal and the second delayed signal are generated.
A second contour signal corresponding to the contour of the original signal is generated on the basis of the delay signal of 1, and the first contour signal and the second contour signal are multiplied to generate a first multiplication signal. Further, the first contour signal and the second contour signal are added to generate a first addition signal, and the first addition signal is ternarized into 0 value or a predetermined positive / negative value, A three-valued signal of
The first ternary signal and the first multiplication signal are multiplied to generate the second multiplication signal. Further, the contour of the first delay signal is corrected based on the second multiplication signal, and when the level of the first addition signal is within a predetermined threshold value, the first ternary signal is generated as 0. .

In the second signal processing apparatus and method of the present invention, the original signal is delayed by a predetermined time, the first delayed signal is generated, and the first delayed signal is further delayed by the predetermined time. A second delayed signal is generated. A first rising contour signal corresponding to the rising contour of the original signal and a first falling contour signal corresponding to the falling contour of the original signal are generated based on the original signal and the first delay signal. A second rising edge signal corresponding to the rising edge of the original signal and a second falling edge signal corresponding to the falling edge of the original signal are generated based on the first delay signal and the second delay signal. Further, the first rising edge signal and the second rising edge signal, and the first falling edge signal and the second falling edge signal are respectively multiplied to obtain a first multiplication signal and a second multiplication signal. Is generated, the first multiplication signal and the second multiplication signal are added, and the first addition signal is generated. In addition, a second addition signal corresponding to a signal obtained by adding the first rising edge signal, the first falling edge signal, the second rising edge signal, and the second falling edge signal is generated. Then, the second addition signal is ternarized into a zero value or a predetermined positive / negative value to generate a ternary signal. The first addition signal and the ternary signal are multiplied, and the first signal is obtained based on the obtained signal.
When the contour of the delay signal of is corrected and the level of the second addition signal is within a predetermined threshold value, a ternary signal is generated as 0.

In the third signal processing apparatus and method of the present invention, the original signal is delayed by a predetermined time, the first delayed signal is generated, and the first delayed signal is further delayed by the predetermined time. A second delayed signal is generated. A first rising contour signal corresponding to the rising contour of the original signal and a first falling contour signal corresponding to the falling contour of the original signal are generated based on the original signal and the first delay signal. A second rising edge signal corresponding to the rising edge of the original signal and a second falling edge signal corresponding to the falling edge of the original signal are generated based on the first delay signal and the second delay signal. Further, the first rising edge signal and the second rising edge signal, and the first falling edge signal and the second falling edge signal are respectively multiplied to obtain a first multiplication signal and a second multiplication signal. Is generated, the logical sum of the first multiplication signal and the second multiplication signal is calculated, and the first rising edge signal, the first falling edge signal, the second rising edge signal, and the second falling edge signal are generated. An addition signal corresponding to the signal obtained by adding the contour signals is generated. The addition signal is ternarized into a zero value or a predetermined positive / negative value to generate a ternary signal, the result of logical OR is multiplied by the ternary signal, and the first signal is obtained based on the obtained signal. The contour of the delayed signal is corrected. Also,
When the level of the addition signal is within a predetermined threshold value, the ternary signal is generated as 0.

In the fourth signal processing apparatus and method of the present invention, the original signal is delayed by a predetermined time, the first delayed signal is generated, and the first delayed signal is further delayed by the predetermined time. A second delayed signal is generated. A first rising contour signal corresponding to the rising contour of the original signal and a first falling contour signal corresponding to the falling contour of the original signal are generated based on the original signal and the first delay signal. A second rising edge signal corresponding to the rising edge of the original signal and a second falling edge signal corresponding to the falling edge of the original signal are generated based on the first delay signal and the second delay signal. Furthermore, when the logical product of the first rising contour signal and the second rising contour signal is not 0, the first rising contour signal and the second rising contour signal are output, and the first falling contour signal and the Two
When the logical product of the falling edge contour signals is not 0, the first falling edge signal and the second falling edge signal are output, and the output first rising edge signal and the output first rising edge signal are output. Logical sum of falling contour signals and second
Of the rising edge signal and the second falling edge signal are calculated. The calculation result of the logical sum of the first rising contour signal and the first falling contour signal is multiplied by the calculation result of the logical sum of the second rising contour signal and the second falling contour signal to generate a multiplication signal. The first rising edge signal, the first falling edge signal,
An addition signal corresponding to the signal obtained by adding the second rising contour signal and the second falling contour signal is generated. Further, the addition signal is ternarized into 0 value or a predetermined positive / negative value to generate a ternary signal, the generated multiplication signal and the ternary signal are multiplied, and the first signal is obtained based on the obtained signal. When the contour of the delay signal is corrected and the level of the added signal is within a predetermined threshold value, the ternary signal is generated as 0.

[0039]

FIG. 4 is a block diagram showing a configuration example of a contour correction circuit provided in a signal processing device to which the present invention is applied. 5 and 6 are diagrams showing examples of waveforms of signals generated in the respective units of the contour correction circuit shown in FIG. Note that A1 to S1 shown in FIG.
Are waveforms A1 to S1 shown in FIGS. 5 and 6.
Signal is detected at that position.

The contour correction circuit of FIG. 4 is different from the conventional contour correction circuit of FIG. 1 in that a level detection circuit 43 for detecting the level of the output signal of the adder circuit 40 is provided. ing. Details of the level detection circuit 43 will be described later.

The video signal (original signal) input to the input terminal 31 is supplied to the delay circuit 32A which delays its phase for a predetermined time (T), and the output signal of the delay circuit 32A similarly changes the phase. It is further supplied to the delay circuit 32B which delays by a predetermined time (T).

Therefore, when the video signal having the waveform A1 shown in FIG. 5 is input to the input terminal 31, the delay circuit 32A produces the signal having the waveform B1 shown in FIG. 5, and the delay circuit 32B produces the signal having the waveform C1. Is generated. In FIG. 5, the times t _{1 to} t ₂ and the times t _{2 to} t ₃ are the delay circuit 32A and the delay time 3 respectively.
It corresponds to the time T at which the signal is delayed by 2B.

The video signal input to the input terminal 31 is also input to the subtraction circuit 33 and subtracted from the output signal of the delay circuit 32A. Then, the subtractor circuit 33 generates the signal having the waveform D1 shown in FIG. In addition, the delay circuit 3
The output signal of 2A and the output signal of the delay circuit 32B are both input to the subtraction circuit 34, and the signal of the waveform E1 shown in FIG. 5 is generated.

The output signal of the subtraction circuit 33 is the minimum value circuit 3
5 and the maximum value circuit 36, and the output signal of the subtraction circuit 34 is supplied to the minimum value circuit 37 and the maximum value circuit 38. These minimum value circuit 35 to maximum value circuit 3
A 0 level potential is supplied to each 8.

Minimum value circuit 35 and minimum value circuit 37
Are circuits for extracting the negative-polarity portions of the input signals, respectively, the maximum value circuit 36 and the maximum value circuit 38.
Are circuits for extracting the positive-polarity portions of the input signals.

Therefore, in the minimum value circuit 35, the signal of the waveform F1 in FIG. 5 (the signal corresponding to the rising edge of the video signal), which is the negative polarity portion of the output signal of the subtraction circuit 33, is extracted, In the minimum value circuit 37,
The signal of the waveform H1 in FIG. 5 (the signal corresponding to the trailing edge of the video signal), which is the negative polarity portion of the output signal of the subtraction circuit 34, is extracted.

Further, in the maximum value circuit 36, the waveform G of FIG. 5 which is the positive polarity portion of the output signal of the subtraction circuit 33.
1 (a signal corresponding to the trailing edge of the video signal) is extracted. Similarly, in the maximum value circuit 38, the waveform I1 (the waveform I1 in FIG. 5), which is the positive polarity portion of the output signal of the subtraction circuit 34, is extracted. (Signal corresponding to the trailing edge of the video signal)
Signal is extracted.

The signals extracted by the minimum value circuit 35 and the maximum value circuit 38 are supplied to the multiplication circuit 39 and the addition circuit 40, respectively, and the signals extracted by the maximum value circuit 36 and the minimum value circuit 37 are It is supplied to the multiplication circuit 41 and the addition circuit 42, respectively.

In the multiplication circuit 39, the signal having the waveform J1 shown in FIG. 6 is generated and supplied to the multiplication circuit 47. Further, in the adding circuit 40, the signal of the waveform K1 shown in FIG. 6 is generated, and the level of the signal is detected by the level detecting circuit 43. Further, the output signal of the adder circuit 40 is supplied to the switch circuit 44 via the amplifier circuit 45 and the limiter circuit 46 having a predetermined gain (−k1).

The level detection circuit 43 includes a switch circuit 44.
When the absolute value of the level of the output signal of the adding circuit 40 is less than or equal to a predetermined threshold value, the switch 44A is set to the terminal 44.
It connects to B and supplies the 0 level signal to the multiplication circuit 47. On the other hand, when the absolute value of the level of the output signal of the adding circuit 40 is equal to or larger than the predetermined threshold value, the level detecting circuit 43
The switch 44A is connected to the terminal 44C, and the output from the limiter circuit 46 is supplied to the multiplication circuit 47 as a 1-level signal.

Therefore, for example, the waveform K1 shown in FIG.
The output signal of the adder circuit 40 outside the range of "-X to + X" is cut. In the example of FIG. 6, the amplification factor (k1) of the amplifier circuit 45 is 1.

Further, the level detection circuit 43 controls the switch circuit 44 and supplies the ternary signal of the waveform L1 shown in FIG. 6 to the multiplication circuit 47.

That is, in the period from time t _{1 to} t ₁₅ (the period in which the first waveform of the waveform K1 appears), the time t
During the period from _{11 to} t ₁₂ and the time from t _{13 to} t ₁₄ , the output signal (1 level signal) of the limiter circuit 46 is selected,
Time t ₁ to t _11, the time t ₁₂ to t ₁₃ and time t _14,
During the period from t ₁₅ to t ₁₅ , the 0 level signal is selected.

Similarly, in the period from the time t _{16 to} t ₂₁ (the period in which the second waveform of the waveform K1 appears), the limiter is provided from the time t _{17 to} t ₁₈ and the period from the time t _{19 to} t _20. The output signal of the circuit 46 is selected, and the 0 level signal is selected during the periods of time t _{16 to} t ₁₇ , time t _{18 to} t ₁₉ , and time t _{20 to} t ₂₁ .

In the multiplication circuit 47, the output signal of the multiplication circuit 39 and the output signal of the switch circuit 44 are multiplied,
The obtained output signal is amplified by the amplification circuit 48 having a gain (k2) and then output to the addition circuit 55. The multiplication circuit 47 outputs the signal having the waveform M1 shown in FIG.

On the other hand, in the multiplication circuit 41, the signal of the waveform N1 shown in FIG. 6 is generated, which is the multiplication circuit 53.
Is supplied to. Further, in the addition circuit 42, the signal of the waveform O1 shown in FIG. 6 is generated, and the level of the generated signal is detected by the level detection circuit 49. Also,
The output signal of the adder circuit 42 is sent to the switch circuit 5 via the amplifier circuit 51 and the limiter circuit 52 each having a predetermined gain (-k1).
Supplied to zero.

The level detection circuit 49 includes a switch circuit 50.
When the absolute value of the level of the output signal of the adding circuit 42 is less than or equal to a predetermined threshold value, the switch 50A is set to the terminal 50.
The signal is connected to C and a 0 level signal is supplied to the multiplication circuit 53. On the other hand, the level detection circuit 49, when the absolute value of the level of the output signal of the addition circuit 42 is equal to or more than the predetermined threshold value,
The switch 50A is connected to the terminal 50B, and the output signal from the limiter circuit 52 is supplied to the multiplication circuit 53.

Therefore, for example, the waveform O1 shown in FIG.
The output signal of the adding circuit 42 outside the range of "-Y to + Y" is cut.

Further, the level detection circuit 49 controls the switch circuit 50 and supplies the ternary signal of the waveform P1 shown in FIG. 6 to the multiplication circuit 53.

That is, time t₃₁To t₃₆Period (waveform
Time period during which the first waveform of O1 appears)
₃₂To t₃₃, Time t₃₄To t₃₅Limiter circuit
The output signal of 52 is selected and time t₃₁To t₃₂, Time t
₃₃To t₃₄, Time t₃₅To t ₃₆During the period,
No. is selected.

Similarly, the period from time t _{37 to} t ₄₂ (waveform O
(The period in which the second waveform of 1 appears), at time t ₃₈
The output signal of the limiter circuit 52 is selected during the period from t _{39 to} t ₃₉ and the period from t _{40 to} t ₄₁ , and the period from t _{37 to} t ₃₈ , the period from t _{39 to} t ₄₀ , and the period from t _{41 to} t ₄₂ is 0
The level signal is selected.

In the multiplication circuit 53, the output signal of the multiplication circuit 41 and the output signal of the switch circuit 50 are multiplied,
The obtained output signal is amplified by the gain (k2 ′) amplification circuit 54 and then output to the addition circuit 55. In addition,
The signal having the waveform Q1 shown in FIG. 6 is output from the multiplication circuit 53.

In the adder circuit 55, the supplied signals are added together to generate a correction signal of the waveform R1 shown in FIG. 6, which is supplied to the adder circuit 56.

In the adder circuit 56, the output signal of the adder circuit 55 and the output signal of the delay circuit 32A are added,
The generated signal is output to the output terminal 57.

By the operation of each circuit described above, for example, as shown in FIG.
Compared with the original signal of waveform A1 shown in
And the waveform S1 in which the falling edge portion is sharply corrected
The video signal of is taken out.

As described above, the signals near the 0 level of the input signals of the amplifier circuit 45 and the amplifier circuit 51, which are easily affected by noise, are forced to the 0 level signal by the switch 44 and the switch 50, respectively. Since the signal is output to the multiplying circuit 47 and the multiplying circuit 53, the jitter of the signal taken out by the output terminal 57 is reduced.

FIG. 7 is a block diagram showing another configuration example of the contour correction circuit provided in the signal processing device to which the present invention is applied.

The contour correction circuit shown in FIG. 7 corresponds to the amplification circuit 48 and the amplification circuit 5 of the contour correction circuit shown in FIG.
The number of elements constituting the circuit is reduced by making the gain of 4 the same.

When the video signal supplied to the input terminal 71 is the same as the signal of the waveform A1 shown in FIG. 5,
The waveforms of the output signals of the delay circuit 72A, the delay circuit 72B, the subtraction circuit 73, the subtraction circuit 74, the minimum value circuit 75, the maximum value circuit 76, the minimum value circuit 77, the maximum value circuit 78, and the multiplication circuit 79 are as shown in FIG. Waveforms A1 to I1, waveform J of FIG.
1 and the waveform N1 are the same.

The input terminal 71 to the multiplication circuit 79 are the same as the input terminal 31 to the multiplication circuit 39 shown in FIG.
In the multiplication circuit 79, extracted by the minimum value circuit 75,
A negative polarity signal of the output signal of the subtraction circuit 73 and a positive polarity signal of the output signal of the subtraction circuit 74 extracted by the maximum value circuit 78 are supplied.

On the other hand, the multiplication circuit 80 includes the maximum value circuit 76.
The positive polarity signal of the output signal of the subtraction circuit 73 extracted by and the negative polarity signal of the output signal of the subtraction circuit 74 extracted by the minimum value circuit 77 are supplied.

The signal obtained by multiplication by the multiplication circuit 79 and the signal obtained by multiplication by the multiplication circuit 80 are respectively supplied to the addition circuit 81, and are added in the addition circuit 81. The output of the addition circuit 81 is the multiplication circuit 8
2 is output.

Further, in the contour correction circuit shown in FIG. 7, the output of the subtraction circuit 73 and the output signal of the subtraction circuit 74 are supplied to the addition circuit 83, respectively.
A ternary signal is generated in the same manner as that generated by the contour correction circuit shown in FIG. 4 based on the signal obtained by adding 3 and the obtained signal. In the adder circuit 83, for example,
A signal having a waveform obtained by adding the waveform K1 and the waveform O1 shown in FIG. 2 (a signal having a waveform obtained by adding the waveform F1, the waveform G1, the waveform H1, and the waveform I1) is generated.

Specifically, the level of the output signal of the adder circuit 83 is detected by the level detection circuit 84, and the switch 85A of the switch circuit 85 is switched based on the detection result to output the output signal of the adder circuit 83. , A signal near the 0 level (a signal whose absolute value of the level is within a predetermined threshold range) is forcibly set to the 0 level signal.

Then, the terminals 85B and 85C of the switch circuit 85 are appropriately selected, and the output signal of the limiter circuit 87 and the ternary signal consisting of the 0 level signal are multiplied by the multiplication circuit 82.
Is supplied to.

In the multiplication circuit 82, the output signal of the addition circuit 81 and the output signal of the switch circuit 85 are multiplied,
The obtained signal is amplified by the amplifier circuit 88 having a gain k2 and then used as a correction signal. This correction signal and the delay circuit 72
The output signal of A is added in the addition circuit 89, and the obtained video signal is extracted by the output terminal 90.

As described above, even when the configuration of the contour correction circuit shown in FIG. 4 is changed, the contour correction of the video signal suitable for improving the image quality can be performed. Further, the number of elements constituting the circuit can be reduced as compared with the contour correction circuit shown in FIG.

The contour correction circuit shown in FIG. 8 is the same as the contour correction circuit shown in FIG. 7 except that an OR gate 111 is provided instead of the multiplication circuit 81. Figure 7
The detailed description of the portions overlapping with the contour correction circuit shown in FIG.

That is, a signal obtained by multiplying the output signal of the minimum value circuit 105 and the output signal of the maximum value circuit 108, and the output signal of the maximum value circuit 106 and the output signal of the minimum value circuit 107. Since the signals obtained by doing so do not show values other than 0 during the same period, by providing the OR gate 111 in this way, the multiplication circuit 112 is provided with the output signal of the multiplication circuit 109 and the multiplication circuit. Either the output signal of 110 or the signal of 0 level is input.

The contour correction circuit shown in FIG. 9 is a block diagram showing a configuration example of the contour correction circuit provided in the signal processing apparatus to which the present invention is applied.

The input terminal 131 to the maximum value circuit 138 and the addition circuit 149 to the level detection circuit 153 are the same as those shown in FIG. That is, the output signals of the subtraction circuit 133 and the subtraction circuit 134 are added in the addition circuit 149, and the switch circuit 152 generates a ternary signal based on the level of the obtained signal. The generated ternary signal is supplied to the multiplication circuit 148 and is multiplied by the signal supplied from the multiplication circuit 147.

The negative polarity signal of the output signal of the subtraction circuit 133 obtained by the minimum value circuit 135 is the switching circuit 13
9 and the AND gate 140, and the positive signal of the output signal of the subtraction circuit 133 obtained by the maximum value circuit 136 is supplied to the switch circuit 141 and the AND gate 142.

Further, the negative signal of the output signal of the subtraction circuit 134 obtained by the minimum value circuit 137 is supplied to the AND gate 142 and the switch circuit 143, and the maximum value circuit 1
The positive signal of the output signal of the subtraction circuit 134 obtained by 38 is supplied to the AND gate 140 and the switch circuit 144.

The AND gate 140 switches the switch 13 of the switch circuit 139 when the levels of both the output signal of the minimum value circuit 135 and the output signal of the maximum value circuit 138 are not 0.
9A is connected to the terminal 139C, and the switch 144A of the switch circuit 144 is connected to the terminal 144B. Therefore, when the switch 139A is connected to the terminal 139C, the OR gate 145 is supplied with the output signal of the minimum value circuit 135, and when the switch 144A is connected to the terminal 144B, the OR gate 146 has the maximum value. Value circuit 13
8 output signals are provided.

Similarly, the AND gate 142 connects the switch 141A of the switch circuit 141 to the terminal 141B when the levels of the output signal of the maximum value circuit 136 and the output signal of the minimum value circuit 137 are not both 0, and the switch circuit The switch 143A of 143 is connected to the terminal 143C. Therefore, when the switch 141A is connected to the terminal 141C, the maximum value circuit 135 is included in the OR gate 145.
Output signal is supplied to switch 143A
When connected to C, the output signal of the minimum value circuit 137 is supplied to the OR gate 146.

Since one of the output of the switch circuit 139 and the output of the switch circuit 141 is always 0, the output signal of the minimum value circuit 135 or the output signal of the maximum value circuit 136 is output from the OR gate 145. Is output.

Further, one of the output of the switch circuit 143 and the output of the switch circuit 144 is always 0.
Therefore, the minimum value circuit 137 is output from the OR gate 146.
Or the output signal of the maximum value circuit 138 is output.

In the multiplication circuit 147, the OR gate 14
5 is multiplied by the output signal of the OR gate 146, and the obtained signal is further multiplied by the ternary signal supplied from the switch 152 in the multiplication circuit 148.

The output signal of the multiplication circuit 148 is amplified by the amplifier circuit 153 and then added to the output signal of the delay circuit 132 by the adder circuit 154 in the same manner as in the above-described various contour correction circuits to correct the contour. Video signal output terminal 1
55.

In the contour correction circuit shown in FIG. 9,
Since the multiplication circuit 147 is used in a time-division manner, the number of elements forming the circuit can be reduced and power consumption can be suppressed.

As described above, the contour correction circuit to which the present invention is applied can be configured by various configurations, and when a ternary signal is obtained, a portion where the influence of noise greatly appears is set to a 0 level signal. More suitable contour correction can be performed.

[0092]

According to the first signal processing apparatus and method of the present invention, the original signal is delayed by a predetermined period to generate the first delayed signal, and the first delayed signal is further delayed for the predetermined period. And a second delayed signal is generated. Also, based on the original signal and the first delayed signal, the first signal corresponding to the contour of the original signal is generated.
Of the first delay signal and the second delay signal, a second contour signal corresponding to the contour of the original signal is generated, and the first contour signal and the second contour signal are generated. Multiply to generate a first multiplication signal. Furthermore, the first contour signal and the second contour signal are added to generate a first addition signal,
The addition signal of 3 is converted into a 0-value or a predetermined positive / negative value by ternarization to generate a first ternary signal, and the first ternary signal is multiplied by the first multiplication signal to obtain a second multiplication signal. To generate. Also,
The contour of the first delay signal is corrected based on the second multiplication signal, and the first ternary signal is generated as 0 when the level of the first addition signal is within a predetermined threshold value. Therefore, even if the video signal contains noise,
The contour correction can be more suitably performed.

According to the second signal processing apparatus and method of the present invention, the original signal is delayed by a predetermined period, the first delayed signal is generated, and the first delayed signal is further delayed by the predetermined period. , A second delayed signal is generated. Also, the original signal and the first
A first rising edge signal corresponding to the rising edge of the original signal and a first falling edge signal corresponding to the falling edge of the original signal, and the first delay signal and the second delay signal are generated. The second rising edge contour signal corresponding to the rising edge of the original signal and the second falling edge edge signal corresponding to the falling edge of the original signal are generated based on the delay signal of. Further, the first rising contour signal and the second rising contour signal, and the first falling contour signal and the second falling contour signal are respectively multiplied to obtain the first
And a second multiplication signal are generated, and the first multiplication signal and the second multiplication signal are added to generate a first addition signal. A second addition signal corresponding to a signal obtained by adding the first rising edge signal, the first falling edge signal, the second rising edge signal, and the second falling edge signal is generated. The second addition signal to 0
A value or a predetermined positive / negative value is ternarized to generate a ternary signal. When the first added signal and the ternary signal are multiplied, the contour of the first delayed signal is corrected based on the obtained signal, and the level of the second added signal is within a predetermined threshold value, the ternary signal Since 0 is generated, even if the video signal contains noise, the contour correction can be more suitably performed.

According to the third signal processing apparatus and method of the present invention, the original signal is delayed by a predetermined period, the first delayed signal is generated, and the first delayed signal is further delayed by the predetermined period. , A second delayed signal is generated. Also, the original signal and the first
A first rising edge signal corresponding to the rising edge of the original signal and a first falling edge signal corresponding to the falling edge of the original signal, and the first delay signal and the second delay signal are generated. The second rising edge contour signal corresponding to the rising edge of the original signal and the second falling edge edge signal corresponding to the falling edge of the original signal are generated based on the delay signal of. Further, the first rising contour signal and the second rising contour signal, and the first falling contour signal and the second falling contour signal are respectively multiplied to obtain the first
Of the first multiplication signal and the second multiplication signal are calculated, and the logical sum of the first multiplication signal and the second multiplication signal is calculated, and the first rising contour signal, the first falling contour signal, and the second An addition signal corresponding to the signal obtained by adding the rising edge signal and the second falling edge signal is generated. The added signal is ternarized into a zero value or a predetermined positive / negative value to generate a ternary signal, the result of the logical sum is multiplied by the ternary signal, and the first delay is performed based on the obtained signal. Correct the contour of the signal. Further, since the ternary signal is generated as 0 when the level of the added signal is within the predetermined threshold, even if the video signal contains noise,
The contour correction can be more suitably performed.

According to the fourth signal processing apparatus and method of the present invention, the original signal is delayed by a predetermined period, the first delayed signal is generated, and the first delayed signal is further delayed by the predetermined period. , A second delayed signal is generated. Also, the original signal and the first
A first rising edge signal corresponding to the rising edge of the original signal and a first falling edge signal corresponding to the falling edge of the original signal, and the first delay signal and the second delay signal are generated. The second rising edge contour signal corresponding to the rising edge of the original signal and the second falling edge edge signal corresponding to the falling edge of the original signal are generated based on the delay signal of. Further, when the logical product of the first rising contour signal and the second rising contour signal is not 0, the first rising contour signal and the second rising contour signal are output, and the first falling contour signal and the first falling contour signal are output. When the logical product of the two falling edge signals is not 0, the first falling edge signal and the second falling edge signal are output, and the output first rising edge signal and the output first rising edge signal are output. The logical sum of the falling edge signals and the logical sum of the second rising edge signal and the second falling edge signal are calculated. The calculation result of the logical sum of the first rising contour signal and the first falling contour signal is multiplied by the calculation result of the logical sum of the second rising contour signal and the second falling contour signal to generate a multiplication signal. Then, an addition signal corresponding to a signal obtained by adding the first rising edge signal, the first falling edge signal, the second rising edge signal, and the second falling edge signal is generated. Further, the addition signal is ternarized into a zero value or a predetermined positive / negative value, a ternary signal is generated, the generated multiplication signal is multiplied by the generated ternary signal, and based on the obtained signal, Since the contour of the delay signal of 1 is corrected and the ternary signal is generated as 0 when the level of the added signal is within the predetermined threshold value, even when the video signal includes noise. The contour correction can be performed more preferably.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional contour correction circuit.

FIG. 2 is a diagram showing an example of a waveform.

FIG. 3 is a diagram showing an example of a waveform when noise is included.

FIG. 4 is a block diagram showing a configuration example of a contour correction circuit to which the present invention is applied.

FIG. 5 is a diagram showing an example of a waveform.

FIG. 6 is another diagram showing an example of a waveform.

FIG. 7 is a block diagram showing another configuration example of the contour correction circuit to which the present invention is applied.

FIG. 8 is a block diagram showing still another configuration example of the contour correction circuit to which the present invention is applied.

FIG. 9 is a block diagram showing a configuration example of a contour correction circuit to which the present invention is applied.

[Explanation of symbols]

1 input terminal, 2A and 2B delay circuit, 3 and 4 subtraction circuit, 5 and 7 minimum value circuit, 6 and 8 maximum value circuit, 9 and 11 multiplication circuit, 10
And 12 adder circuit, 13 multiplier circuit, 15 limiter, 16 multiplier circuit, 18 limiter, 21 and 22 adder circuit, 23 output terminal

Claims (9)

[Claims] 1. A first delay means for delaying an original signal by a predetermined time to generate a first delay signal, further delaying the first delay signal by the time, and second
Second delay means for generating the delay signal of, and first generation means for generating a first contour signal corresponding to the contour of the original signal based on the original signal and the first delay signal. Based on the first delayed signal and the second delayed signal,
Second generation means for generating a second contour signal corresponding to the contour of the original signal, and first for multiplying the first contour signal and the second contour signal to generate a first multiplication signal. Multiplying means, adding means for adding the first contour signal and the second contour signal to generate a first addition signal, the first addition signal having a zero value or a predetermined positive or negative value. Arithmetic means for ternarizing a value to generate a first ternary signal, and second multiplying means for multiplying the first ternary signal by the first multiplication signal to generate a second multiplication signal. And a correction unit that corrects the contour of the first delay signal based on the second multiplication signal, and the calculation unit is such that when the level of the first addition signal is within a predetermined threshold value. A signal processing device, wherein the first ternary signal is generated as 0. 2. The first generation means generates a first rising edge signal corresponding to a rising edge of the original signal and a falling edge of the original signal, which form the first edge signal. A corresponding first falling edge signal is generated, and the second generation means forms a second edge signal, and a second rising edge signal corresponding to a rising edge of the original signal; A second falling edge signal corresponding to the falling edge of the original signal is generated, and the first multiplying means includes the first rising edge signal, the second rising edge signal, and the first rising edge signal. Each of the falling edge contour signal and the second falling edge signal are generated to generate a third multiplication signal and a fourth multiplication signal, which form the first multiplication signal, and the addition means , The first standing A rising contour signal and the second rising contour signal, and a first falling contour signal and the second falling contour signal are added together to form the first addition signal; Of the second addition signal and the third addition signal, and the arithmetic means generates the second addition signal and the third addition signal.
When the level of the addition signal is within the threshold,
And generating a second ternary signal and a third ternary signal that compose the third ternary signal as 0, and the second multiplying unit generates the third multiplying signal and the second ternary signal.
Ternary signal, and the fourth multiplication signal and the third
Each of the value signals is multiplied to generate a fifth multiplication signal and a sixth multiplication signal, which form the second multiplication signal, and the correction means includes the fifth multiplication signal and the sixth multiplication signal. The signal processing device according to claim 1, wherein the first delay signal is corrected based on a signal obtained by adding the multiplication signals. 3. A first delay step of delaying an original signal by a predetermined time to generate a first delayed signal, further delaying the first delayed signal by the time, and
A second delay step of generating a delay signal of, and a first generation step of generating a first contour signal corresponding to a contour of the original signal based on the original signal and the first delay signal, Based on the first delayed signal and the second delayed signal,
A second generation step of generating a second contour signal corresponding to the contour of the original signal, and a first step of multiplying the first contour signal and the second contour signal to generate a first multiplication signal. And a step of adding the first contour signal and the second contour signal to generate a first addition signal, and setting the first addition signal to a zero value or a predetermined positive or negative value. An operation step of ternarizing a value to generate a first ternary signal, and a second multiplication step of multiplying the first ternary signal by the first multiplication signal to generate a second multiplication signal And a correction step of correcting the contour of the first delay signal based on the second multiplication signal, and the level of the first addition signal falls within a predetermined threshold by the processing of the calculation step. In one case, the first ternary signal is generated as 0. Signal processing method to be. 4. A first delay means for delaying an original signal by a predetermined time to generate a first delay signal, further delaying the first delay signal by the time, and second
A second delay means for generating a delay signal, and a first rising contour signal corresponding to a rising contour of the original signal and a falling contour based on the original signal and the first delay signal. First generating means for generating a corresponding first falling edge signal, and based on the first delay signal and the second delay signal,
A second rising edge signal corresponding to the rising edge of the original signal and a second generating means for generating a second falling edge signal corresponding to the falling edge; and the first rising edge signal Multiplication means for respectively multiplying the second rising contour signal, the first falling contour signal and the second falling contour signal to generate a first multiplication signal and a second multiplication signal; A first addition means for adding the first multiplication signal and the second multiplication signal to generate a first addition signal, the first rising contour signal, the first falling contour signal, Second adding means for generating a second addition signal corresponding to a signal obtained by adding the second rising contour signal and the second falling contour signal; and the second addition signal, , 0 value, Alternatively, arithmetic means for ternaryizing a predetermined positive and negative value to generate a ternary signal, and multiplying the first addition signal and the ternary signal, and calculating the first delayed signal based on the obtained signal. A signal processing device comprising: a correction unit that corrects a contour, wherein the calculation unit generates the ternary signal as 0 when the level of the second addition signal is within a predetermined threshold value. 5. A first delay step of delaying an original signal by a predetermined time to generate a first delay signal, further delaying the first delay signal by the time, and
A second delay step for generating a delay signal of the first signal, and a first rising contour signal corresponding to a rising contour of the original signal and a falling contour based on the original signal and the first delay signal. A first generating step of generating a corresponding first falling edge signal, and based on the first delay signal and the second delay signal,
A second rising edge signal corresponding to the rising edge of the original signal and a second generation step of generating a second falling edge signal corresponding to the falling edge; and the first rising edge signal A multiplication step of multiplying each of the second rising contour signal, the first falling contour signal and the second falling contour signal to generate a first multiplication signal and a second multiplication signal; A first addition step of adding the first multiplication signal and the second multiplication signal to generate a first addition signal, the first rising contour signal, the first falling contour signal, A second addition step of generating a second addition signal corresponding to a signal obtained by adding the second rising contour signal and the second falling contour signal; and the second addition step. An arithmetic step of ternarizing the arithmetic signal into a zero value or a predetermined positive / negative value to generate a ternary signal; and multiplying the first addition signal by the ternary signal, and based on the obtained signal A correction step of correcting the contour of the first delay signal, and by the processing of the calculation step, the ternary signal is generated as 0 when the level of the second addition signal is within a predetermined threshold value. A signal processing method comprising: 6. A first delay means for delaying the original signal by a predetermined time to generate a first delay signal, further delaying the first delay signal by the time, and second
A second delay means for generating a delay signal, and a first rising contour signal corresponding to a rising contour of the original signal and a falling contour based on the original signal and the first delay signal. First generating means for generating a corresponding first falling edge signal, and based on the first delay signal and the second delay signal,
A second rising edge signal corresponding to the rising edge of the original signal and a second generating means for generating a second falling edge signal corresponding to the falling edge; and the first rising edge signal Multiplication means for respectively multiplying the second rising contour signal, the first falling contour signal and the second falling contour signal to generate a first multiplication signal and a second multiplication signal; Calculating means for calculating a logical sum of the first multiplication signal and the second multiplication signal, the first rising contour signal, the first falling contour signal, the second rising contour signal, Adder means for generating an addition signal corresponding to a signal obtained by adding the second falling contour signal; and a three-value signal in which the addition signal is ternarized into a zero value or a predetermined positive / negative value. And a correction unit that multiplies the calculation result of the logical sum by the calculation unit and the ternary signal, and corrects the contour of the first delay signal based on the obtained signal. The signal processing device, wherein the arithmetic means generates the ternary signal as 0 when the level of the addition signal is within a predetermined threshold value. 7. A first delay step of delaying an original signal by a predetermined time to generate a first delayed signal, further delaying the first delayed signal by the time, and
A second delay step for generating a delay signal of the first signal, and a first rising contour signal corresponding to a rising contour of the original signal and a falling contour based on the original signal and the first delay signal. A first generating step of generating a corresponding first falling edge signal, and based on the first delay signal and the second delay signal,
A second rising edge signal corresponding to the rising edge of the original signal and a second generation step of generating a second falling edge signal corresponding to the falling edge; and the first rising edge signal A multiplication step of multiplying each of the second rising contour signal, the first falling contour signal and the second falling contour signal to generate a first multiplication signal and a second multiplication signal; A calculating step of calculating a logical sum of the first multiplication signal and the second multiplication signal, the first rising contour signal, the first falling contour signal, the second rising contour signal, An addition step of generating an addition signal corresponding to a signal obtained by adding the second falling contour signal, and setting the addition signal to 0 or a predetermined positive or negative value. An operation step of digitizing and generating a ternary signal, a calculation result of the logical sum by the processing of the calculating step and the ternary signal are multiplied, and the contour of the first delay signal is corrected based on the obtained signal. The signal processing method according to claim 1, wherein the ternary signal is generated as 0 when the level of the addition signal is within a predetermined threshold by the processing of the calculation step. 8. A first delay means for delaying an original signal by a predetermined time to generate a first delay signal, further delaying the first delay signal by the time, and second
A second delay means for generating a delay signal, and a first rising contour signal corresponding to a rising contour of the original signal and a falling contour based on the original signal and the first delay signal. First generating means for generating a corresponding first falling edge signal, and based on the first delay signal and the second delay signal,
A second rising edge signal corresponding to the rising edge of the original signal and a second generating means for generating a second falling edge signal corresponding to the falling edge; and the first rising edge signal First output means for outputting the first rising contour signal and the second rising contour signal when the logical product of the second rising contour signals is not 0; the first falling contour signal; When the logical product of the second falling contour signals is not 0, second output means for outputting the first falling contour signal and the second falling contour signal, and output by the first output means A logical sum of the generated first rising contour signal and the first falling contour signal output by the second output means, and the second rising contour signal and the second Calculating means for respectively calculating the logical sum of the falling edge signals; calculation result of the logical sum of the first rising edge signal and the first falling edge signal by the calculating means; and the second rising edge signal And a multiplication means for generating a multiplication signal by multiplying the calculation result of the logical sum of the second falling edge signal, the first rising edge signal, the first falling edge signal, and the second rising edge. Adder means for generating an addition signal corresponding to a contour signal and a signal obtained by adding the second falling contour signal; and ternarizing the addition signal into a zero value or a predetermined positive / negative value. A calculator for generating a ternary signal; and a corrector for multiplying the multiplication signal by the ternary signal and correcting the contour of the first delay signal based on the obtained signal. The stage is configured to generate the ternary signal as 0 when the level of the addition signal is within a predetermined threshold value. 9. A first delay step of delaying an original signal by a predetermined time to generate a first delayed signal, further delaying the first delayed signal by the time, and
A second delay step for generating a delay signal of the first signal, and a first rising contour signal corresponding to a rising contour of the original signal and a falling contour based on the original signal and the first delay signal. A first generating step of generating a corresponding first falling edge signal, and based on the first delay signal and the second delay signal,
A second rising edge signal corresponding to the rising edge of the original signal and a second generation step of generating a second falling edge signal corresponding to the falling edge; and the first rising edge signal A first output step of outputting the first rising contour signal and the second rising contour signal when the logical product of the second rising contour signals is not 0; the first falling contour signal; A second output step of outputting the first falling edge signal and the second falling edge signal when the logical product of the second falling edge signals is not 0, and processing of the first output step And a logical sum of the first rising edge signal output by the second output step and the first falling edge signal output by the process of the second output step, and Calculation step for calculating the logical sum of the rising contour signal and the second falling contour signal, respectively, and the logical sum of the first rising contour signal and the first falling contour signal by the processing of the calculating step. A multiplication step of multiplying a calculation result and a calculation result of a logical sum of the second rising contour signal and the second falling contour signal to generate a multiplication signal; the first rising contour signal, the first A falling edge contour signal, the second rising edge contour signal, and a signal obtained by adding the second falling edge contour signal, and an addition step of generating an addition signal; , Or a step of ternaryizing a predetermined positive and negative value to generate a ternary signal; multiplying the multiplication signal by the ternary signal, and based on the obtained signal, A correction step for correcting the contour of the delay signal of 1, and the ternary signal is generated as 0 when the level of the addition signal is within a predetermined threshold by the processing of the calculation step. Signal processing method.