JPH0513640A - Lead pin plating jig for integrated circuit package - Google Patents

Lead pin plating jig for integrated circuit package

Info

Publication number
JPH0513640A
JPH0513640A JP18932991A JP18932991A JPH0513640A JP H0513640 A JPH0513640 A JP H0513640A JP 18932991 A JP18932991 A JP 18932991A JP 18932991 A JP18932991 A JP 18932991A JP H0513640 A JPH0513640 A JP H0513640A
Authority
JP
Japan
Prior art keywords
lead pin
integrated circuit
plating
circuit package
jig
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18932991A
Other languages
Japanese (ja)
Inventor
Katsuyuki Takarasawa
勝幸 宝沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Kikinzoku Kogyo KK
Original Assignee
Tanaka Kikinzoku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Kikinzoku Kogyo KK filed Critical Tanaka Kikinzoku Kogyo KK
Priority to JP18932991A priority Critical patent/JPH0513640A/en
Publication of JPH0513640A publication Critical patent/JPH0513640A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To surely perform uniform electric plating by constituting a jig of a thin plate which has openings for inserting the tips of many integrated circuit package lead pins which are arranged and fixed at the fixed intervals longitudinally and latitudinally and composing the thin plate of shape memory alloy. CONSTITUTION:A lead pin plating jig 8 is composed of Ti-Ni monidirectional shape memory alloy which completely inverts the shape at a low temperature and a high temperature. Namely, the lead pin plating jig 8 is composed of a thin plate which has openings 7 for inserting the many tips of the lead pins 3 of an integrated circuit package 2, which are arranged and fixed at the fixed intervals longitudinally and latitudinally. The thin plate is composed of the shape memory alloy. Therefore, since the openings 7 are opened and closed by changing the temperature, the many pins 3 can be inserted and pulled out without load and the operation is facilitated. Thus, uniform current flows to the all lead pins 3 and uniform electric plating is performed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、集積回路パッケージの
リードピンに、Ni、Auその他の電気メッキを施す際
に用いる通電電極としてのリードピンメッキ用治具に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead pin plating jig as a current-carrying electrode used for electroplating Ni, Au or the like on a lead pin of an integrated circuit package.

【0002】[0002]

【従来の技術】集積回路パッケージのリードピンは、耐
食性を向上させる為に、Ni、Auその他の電気メッキ
を施している。従来、集積回路パッケージ、特に数10〜
数 100本のリードピンを有するPGA(ピングリッドア
レー)型パッケージのリードピンに、Ni、Auその他
の電気メッキを施す際には、図6に示すようにメッキ用
通電電極をとる為の端子1をパッケージ2の側面にろう
付け又は半田付けしてコモン電極としたり、図7に示す
ようにパッケージ2のリードピン3の先端に、Niやス
テンレス鋼等の薄板4をろう付け又は半田付けしてコモ
ン電極としたり、図8に示すように半導体チップから信
号を取り出すAu線やAl線をボンディングするパッケ
ージ2の端子部5にコモン電極を押し付けている。
2. Description of the Related Art Lead pins of integrated circuit packages are electroplated with Ni, Au or the like in order to improve corrosion resistance. Conventionally, integrated circuit packages, especially several tens to
When electroplating Ni, Au, etc., on the lead pins of a PGA (pin grid array) type package having several hundreds of lead pins, as shown in FIG. 2 is brazed or soldered to the side surface to form a common electrode, or a thin plate 4 made of Ni, stainless steel, or the like is brazed or soldered to the tip of the lead pin 3 of the package 2 to form a common electrode as shown in FIG. Alternatively, as shown in FIG. 8, the common electrode is pressed against the terminal portion 5 of the package 2 for bonding the Au wire or the Al wire for taking out a signal from the semiconductor chip.

【0003】ところで、図6、7の方法ではメッキ前後
の電極の取り付け、取り外しに手間がかかる。また取り
外した後その部分を修正する必要がある。図8の方法で
は後工程でAu線やAl線をボンディングする最も信頼
性の必要なパッケージ2の端子部5を疵付けたり、汚し
たりする恐れがあり、また全てのリードピン3に確実に
電流を流すような接続をとることは困難であって、メッ
キ不良のリードピンが発生する恐れがある。
By the way, in the method shown in FIGS. 6 and 7, it takes time and effort to attach and detach the electrodes before and after plating. Moreover, it is necessary to modify the part after removing. In the method of FIG. 8, there is a possibility that the terminal portion 5 of the package 2 that requires the most reliability for bonding the Au wire and the Al wire in the subsequent step may be scratched or soiled, and all the lead pins 3 should be surely supplied with current. It is difficult to make a flowable connection, and lead pins with defective plating may occur.

【0004】[0004]

【発明が解決しようとする課題】そこで本発明は、全て
のリードピンに確実に接触して電流を流すことができ、
しかも挿抜が容易でリードピンを疵付けたり、汚したり
することのない通電電極としてのリードピンメッキ用治
具を提供しようとするものである。
Therefore, according to the present invention, it is possible to surely contact all the lead pins to pass an electric current,
Moreover, it is an object of the present invention to provide a lead pin plating jig as a current-carrying electrode that is easy to insert and remove and does not scratch or stain the lead pin.

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
の本発明の集積回路パッケージのリードピンメッキ用治
具は、一定間隔に多数縦横に配列固定された集積回路パ
ッケージのリードピンの先端を差し込む開口部を有する
薄板からなり、該薄板が形状記憶合金からなるものであ
る。
To solve the above problems, a jig for plating lead pins of an integrated circuit package according to the present invention is an opening for inserting the tips of lead pins of an integrated circuit package in which a large number of fixed and arranged vertical and horizontal arrays are fixed. A thin plate having a portion, and the thin plate is made of a shape memory alloy.

【0006】このリードピンメッキ用治具は、全面又は
リードピンとの接触部に、貴金属又は貴金属を主とする
合金がコーティングされているものもある。
This lead pin plating jig may have a noble metal or an alloy mainly composed of a noble metal coated on the entire surface or a contact portion with the lead pin.

【0007】またこれらのリードピンメッキ用治具は、
形状記憶合金の薄板の開口部のリードピン接触部が下面
側に折り曲げられ、この折り曲げ部がリードピンメッキ
時の雰囲気温度が低温から高温へ又は高温から低温へ変
化することにより折り曲げ角度が変化するようになされ
ているものもある。
These lead pin plating jigs are
The lead pin contact part of the opening of the shape memory alloy thin plate is bent to the lower surface side, and the bending angle is changed by changing the ambient temperature at the time of lead pin plating from low temperature to high temperature or from high temperature to low temperature. Some are done.

【0008】[0008]

【作用】上記のように本発明のリードピンメッキ用治具
は、多数のリードピンの先端を差し込む開口部を有する
薄板からなり、該薄板が形状記憶合金からなるので、温
度を変えることにより、開口部が開いたり閉じたりする
為、多数のリードピンを無負荷で挿抜できて作業し易
く、且つリードピンが疵付いたり汚れたりすることがな
い。しかも多数のリードピンに同時に一定の力でもって
接触させ、全てのリードピンに均等に電流を流すことが
でき、均一な電気メッキを行うことができる。また上記
本発明のリードピンメッキ用治具において、全面又はリ
ードピンとの接触部に、貴金属又は貴金属を主とする合
金がコーティングされたものにあっては、リードピンと
の接触抵抗が小さく、電気メッキ時通電が良好に行わ
れ、品質の良い電気メッキが行われる。なお、コーティ
ングは乾式メッキ、湿式メッキ等の他、クラッドによる
複合等でも良い。さらに上記本発明のリードピンメッキ
用治具において、形状記憶合金の薄板の開口部のリード
ピン接触部が下面側に折り曲げられ、この折り曲げ部が
リードピンメッキ時の雰囲気温度が低温から高温ヘ、又
は高温から低温へ変化することにより、折り曲げ角度が
変化するようになされたものにあっては、多数のリード
ピンの挿抜及び接触保持が確実に行われ、リードピンが
傷付いたり、メッキ用治具が損傷したりすることなく、
電気メッキが良好に行われる。
As described above, the jig for plating lead pins according to the present invention is made of a thin plate having an opening into which the tips of a large number of lead pins are inserted. Since the thin plate is made of a shape memory alloy, the opening can be changed by changing the temperature. Since it opens and closes, many lead pins can be inserted and removed without load, making it easy to work, and the lead pins do not get scratched or dirty. In addition, a large number of lead pins can be simultaneously brought into contact with each other with a constant force, an electric current can be evenly applied to all the lead pins, and uniform electroplating can be performed. Further, in the above-mentioned jig for lead pin plating of the present invention, in the case where the entire surface or the contact portion with the lead pin is coated with a noble metal or an alloy mainly containing a noble metal, the contact resistance with the lead pin is small, and at the time of electroplating. Electricity is well supplied and high quality electroplating is performed. The coating may be dry plating, wet plating or the like, or may be a composite with a clad or the like. Further, in the lead pin plating jig of the present invention, the lead pin contact portion of the opening of the shape memory alloy thin plate is bent to the lower surface side, and this bent portion changes the ambient temperature at the time of lead pin plating from low temperature to high temperature or from high temperature. In the case where the bending angle is changed by changing to a low temperature, many lead pins are securely inserted and removed and held in contact with each other, which may damage the lead pins or damage the plating jig. Without doing
Good electroplating.

【0009】[0009]

【実施例】本発明の集積回路パッケージのリードピンメ
ッキ用治具の一実施例を図によって説明する。低温と高
温で形状が完全に反転するTi−Ni系全方向型形状記
憶合金よりなる図1に示す厚さ0.25mm、一辺の長さ 100
mmの正方形の薄板6を用い、平坦な状態で高温記憶処理
を 250℃、1時間行った後、全面にCu、Niのストラ
イクメッキを施し、更に1μmのPtメッキを施した。
その後図2及び図3に示すように中間両側を下面側に折
り曲げたH型形状の開口部7をリードピンのピッチに合
わせて一定間隔に縦20個、横20個、合計 400個設けた
後、−40℃、12時間の低温記憶処理を行った。こうして
作成したリードピンメッキ用治具8を予め用意した0℃
の食塩水に浸漬し、開口部7が全開したことを確かめて
から図4、図5に示すようにPGA型パッケージ2のリ
ードピン3を挿入し、60℃の温浴に浸漬した処、全開口
部7の折り曲げ部7aが閉じられ、全リードピン3が折
り曲げ部7aに完全に保持固定されていた。その後メッ
キ前処理液及びメッキ浴は50〜60℃でもって、リードピ
ンメッキ用治具8から全リードピン3に通電し、Niメ
ッキ、Auメッキを施した結果、全リードピン3の先端
のメッキ用治具の接触部つまり折り曲げ部7a以外の部
分には全面均一なメッキが施された。尚、上記実施例の
リードピンメッキ用治具は、全方向性の形状記憶合金よ
りなるが、一方向性、二方向性の形状記憶合金よりなる
ものでも良い。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a jig for plating lead pins of an integrated circuit package of the present invention will be described with reference to the drawings. It consists of a Ti-Ni omnidirectional shape memory alloy whose shape is completely reversed at low and high temperatures, with a thickness of 0.25 mm and a side length of 100 as shown in Fig. 1.
Using a square thin plate 6 of mm, a high temperature storage treatment was carried out at 250 ° C. for 1 hour in a flat state, and then Cu and Ni strike plating was applied to the entire surface, and further Pt plating of 1 μm was applied.
After that, as shown in FIG. 2 and FIG. 3, after forming the H-shaped opening 7 with the middle both sides bent to the lower surface side at a constant interval of 20 in length and 20 in width according to the pitch of the lead pin, 400 in total, A low temperature memory treatment was performed at -40 ° C for 12 hours. The lead pin plating jig 8 thus prepared was prepared in advance at 0 ° C.
After confirming that the opening 7 is fully opened, the lead pin 3 of the PGA type package 2 is inserted and immersed in a 60 ° C warm bath as shown in Figs. The bent portion 7a of 7 was closed, and all the lead pins 3 were completely held and fixed to the bent portion 7a. After that, the plating pretreatment liquid and the plating bath are at 50 to 60 ° C., the lead pin plating jig 8 is energized to all the lead pins 3 to perform Ni plating and Au plating. The contact portion, that is, the portion other than the bent portion 7a was uniformly plated over the entire surface. The lead pin plating jig of the above embodiment is made of an omnidirectional shape memory alloy, but may be made of a unidirectional or bidirectional shape memory alloy.

【0010】[0010]

【発明の効果】以上の説明で判るように本発明の集積回
路パッケージのリードピンメッキ用治具は、全てのリー
ドピンに開口部が夫々独立して対応する為他のリードピ
ンに影響されることなく、全てのリードピンが確実に接
触保持固定できるので、均等に電流を流すことができ、
均一な電気メッキを行うことができる。しかもメッキ用
治具の温度を変えることにより多数のリードピンを無負
荷で挿抜できて作業し易く、且つリードピンが疵付いた
り汚れたりすることなく、また確実にリードピンを保持
固定することができる。また、PGA型パッケージのリ
ードピンのピッチに合わされた開口部を一定間隔に多数
設けているので、リードピンの数の多少にかかわらず、
1つのメッキ用治具で種々の集積回路パッケージのリー
ドピンの電気メッキを行うことができる。また全面又は
リードピンとの接触部に貴金属又は貴金属を主とする合
金がコーティングされているメッキ用治具は、リードピ
ンとの接触抵抗が小さく、通電が良好に行われるので、
品質の良い電気メッキが行われる。このメッキ用治具に
あっては、毎回メッキ物が電着するが、これは剥離液で
溶解することにより何度でも再利用でき、半永久的に使
用できる。
As can be seen from the above description, in the lead pin plating jig of the integrated circuit package of the present invention, since the openings correspond to all the lead pins independently of each other, the lead pins are not affected by other lead pins. Since all the lead pins can be securely held by contact, it is possible to flow current evenly,
Uniform electroplating can be performed. Moreover, by changing the temperature of the plating jig, a large number of lead pins can be inserted / removed without load, making it easy to work, and the lead pins can be securely held and fixed without being scratched or soiled. In addition, since a large number of openings matching the pitch of the lead pins of the PGA type package are provided at regular intervals, regardless of the number of lead pins,
It is possible to electroplate lead pins of various integrated circuit packages with one plating jig. Further, since the plating jig in which the noble metal or an alloy mainly containing noble metal is coated on the entire surface or the contact portion with the lead pin, the contact resistance with the lead pin is small, and the electricity is satisfactorily conducted.
Good quality electroplating. In this plating jig, the plated product is electrodeposited every time, but it can be reused any number of times by dissolving it in the stripping solution, and can be used semipermanently.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の集積回路パッケージのリードピンメッ
キ用治具の素材を示す図である。
FIG. 1 is a view showing a material of a jig for lead pin plating of an integrated circuit package of the present invention.

【図2】本発明の集積回路パッケージのリードピンメッ
キ用治具の一部底面拡大図である。
FIG. 2 is an enlarged partial bottom view of a jig for lead pin plating of the integrated circuit package of the present invention.

【図3】図2のA−A線断面図である。3 is a cross-sectional view taken along the line AA of FIG.

【図4】図2のリードピンメッキ用治具にリードピンを
挿入し、接触保持固定した状態を示す一部底面拡大図で
ある。
FIG. 4 is a partially enlarged bottom view showing a state in which a lead pin is inserted into the jig for lead pin plating in FIG.

【図5】図4のB−B線断面図である。5 is a sectional view taken along line BB of FIG.

【図6】夫々従来の集積回路パッケージのリードピンに
対する電気メッキ時のコモン電極の取り付け方法を示す
図である。
FIG. 6 is a diagram showing a method of attaching a common electrode to a lead pin of a conventional integrated circuit package during electroplating.

【図7】夫々従来の集積回路パッケージのリードピンに
対する電気メッキ時のコモン電極の取り付け方法を示す
図である。
FIG. 7 is a diagram showing a method of attaching a common electrode to a lead pin of a conventional integrated circuit package during electroplating.

【図8】夫々従来の集積回路パッケージのリードピンに
対する電気メッキ時のコモン電極の取り付け方法を示す
図である。
FIG. 8 is a diagram showing a method of attaching a common electrode to a lead pin of a conventional integrated circuit package during electroplating.

【符号の説明】[Explanation of symbols]

2 集積回路パッケージ 3 リードピン 6 薄板 7 開口部 7a 折り曲げ部(リードピン接触部) 8 リードピンメッキ用治具 2 Integrated circuit package 3 lead pin 6 thin plates 7 openings 7a Bent part (lead pin contact part) 8 Lead pin plating jig

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 一定間隔に多数縦横に配列固定された集
積回路パッケージのリードピンの先端を差し込む開口部
を有する薄板からなり、該薄板が形状記憶合金からなる
集積回路パッケージのリードピンメッキ用治具。
1. A jig for plating a lead pin of an integrated circuit package, comprising a thin plate having an opening into which a tip of a lead pin of the integrated circuit package is fixed and arranged in a matrix at fixed intervals, and the thin plate is made of a shape memory alloy.
【請求項2】 請求項1記載の集積回路パッケージのリ
ードピンメッキ用治具に於いて、全面又はリードピンと
の接触部に、貴金属又は貴金属を主とする合金がコーテ
ィングされていることを特徴とする集積回路パッケージ
のリードピンメッキ用治具。
2. The jig for lead pin plating of an integrated circuit package according to claim 1, wherein the entire surface or a contact portion with the lead pin is coated with a noble metal or an alloy mainly containing a noble metal. Jig for lead pin plating of integrated circuit package.
【請求項3】 請求項1又は2記載の集積回路パッケー
ジのリードピンメッキ用治具に於いて、形状記憶合金の
薄板の開口部のリードピン接触部が下面側に折り曲げら
れ、この折り曲げ部がリードピンメッキ時の雰囲気温度
が低温から高温へ又は高温から低温へ変化することによ
り折り曲げ角度が変化するようになされていることを特
徴とする集積回路パッケージのリードピンメッキ用治
具。
3. The lead pin plating jig for an integrated circuit package according to claim 1, wherein the lead pin contact portion of the opening of the shape memory alloy thin plate is bent to the lower surface side, and this bent portion is lead pin plated. A jig for lead pin plating of an integrated circuit package, wherein the bending angle is changed by changing the ambient temperature from low temperature to high temperature or from high temperature to low temperature.
JP18932991A 1991-07-03 1991-07-03 Lead pin plating jig for integrated circuit package Pending JPH0513640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18932991A JPH0513640A (en) 1991-07-03 1991-07-03 Lead pin plating jig for integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18932991A JPH0513640A (en) 1991-07-03 1991-07-03 Lead pin plating jig for integrated circuit package

Publications (1)

Publication Number Publication Date
JPH0513640A true JPH0513640A (en) 1993-01-22

Family

ID=16239529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18932991A Pending JPH0513640A (en) 1991-07-03 1991-07-03 Lead pin plating jig for integrated circuit package

Country Status (1)

Country Link
JP (1) JPH0513640A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459102A (en) * 1993-02-19 1995-10-17 Ngk Spark Plug Co., Ltd. Method of electroplating lead pins of integrated circuit package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459102A (en) * 1993-02-19 1995-10-17 Ngk Spark Plug Co., Ltd. Method of electroplating lead pins of integrated circuit package
US5580432A (en) * 1993-02-19 1996-12-03 Ngk Spark Plug Co., Ltd. Jig for electroplating lead pins of an integrated circuit package

Similar Documents

Publication Publication Date Title
KR960001352B1 (en) Solder-coated printed circuit board and the method of
US4944850A (en) Tape automated bonded (tab) circuit and method for making the same
US6887113B1 (en) Contact element for use in electroplating
JP3693300B2 (en) External connection terminal of semiconductor package and manufacturing method thereof
EP0335291A3 (en) Method and device of plating pin grid arrays
US3429786A (en) Controlled electroplating process
US3948736A (en) Method of selective electroplating and products produced thereby
JPH0513640A (en) Lead pin plating jig for integrated circuit package
JPS5985886A (en) Selective plating method
CA2341218A1 (en) Contact element
JP3620531B2 (en) Electronic component, plating jig, and plating method using the same
JP2002168879A (en) Insulation coated probe pin
EP3835461A1 (en) Substrate carrier for metallic electroplating of substrates
JP2902728B2 (en) Single side plating method
JPH056908A (en) Method of plating ceramic package
CN217895785U (en) Clamp, lead hanging plating device, lead electroplating system and gold-plated lead
JP3000084B2 (en) Conducting jig for plating and method of manufacturing wiring board using the same
JPH05129498A (en) Plating method for ceramic package
JP3501934B2 (en) Conducting jig for plating
JPH07207497A (en) Method for plating electronic parts and plating jig
JPH02182886A (en) Method for removing silver plating
JPH07115163A (en) Manufacture of ic package
JPH03232994A (en) Plating device
JP2902543B2 (en) Jig for plating
JPH0883662A (en) Manufacture of super-micro connector