JPH05135217A - Reset method for data transfer system to semiconductor memory medium and semiconductor memory medium suited to execution of the same method - Google Patents

Abstract

PURPOSE:To reset an IC card without interrupting supply of a power source, in a system which transfers data while a physical non-contact state between an IC card and a reader/writer device is held. CONSTITUTION:Trigger pulses P1 and P2 are arranged on a signal wave to be transmitted from the reader/writer device in each prescribed cycle T. Bit information to be transferred is expressed by the presence or absence of a bit pulse arranged after each trigger pulse. At the time of a normal data transfer, the state in which there is not any pulse is impossible in a period beyond the cycle T on the signal wave. At the time of operating a reset, a trigger pulse P3 to be arranged at a time t3 is intentionally pulled out. There is not any pulse from a time t2 to a prescribed set time D (D>T), so that the state can be recognized as a reset command, and the reset is operated at a time t4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset method in a data transfer system to a semiconductor storage medium, and more particularly to I
The present invention relates to a reset method suitable for a contactless system for data transfer to a C card.

[0002]

2. Description of the Related Art In recent years, IC has been used as a new information storage medium.
Cards are attracting attention. Although the IC card is a card-shaped storage medium that is convenient in its form, it has a semiconductor memory element built-in, and can record extremely large amount of information as compared with a magnetic card or the like. Further, in the IC card with a built-in CPU, since the IC card itself has an arithmetic processing function, it is highly useful in applications requiring a high degree of security.

A reader / writer device is used to write data in and read data from a semiconductor storage medium such as the IC card described above. By electrically contacting the input / output terminal on the reader / writer device side with the input / output terminal on the IC card side, power and clock can be supplied from the reader / writer device to the IC card.
In addition, it becomes possible to transfer data between them. As a new method of transferring data between the two, a method of transferring data while the two are physically kept in a non-contact state has recently been proposed. That is, the first coil provided on the reader / writer device side and the second coil provided on the IC card side are magnetically coupled to each other so that power and clock are supplied and data transfer is performed. It is something to do. If such non-contact type data transfer is performed, an external input / output terminal becomes unnecessary and the IC card becomes more portable.

[0004]

When resetting the IC card from the reader / writer device side, some external reset command must be transmitted to the IC card side. In the contact-type data transfer system, a dedicated reset line may be provided between the two, and an external reset command signal may be transmitted via this reset line. However, in the non-contact type data transfer system, it is necessary to form an information transmission route between the two coils by magnetically coupling the two coils. Therefore, in order to provide a dedicated reset line between the two, it is necessary to provide a new coil to form a new magnetic coupling. However, it is not preferable to provide a new coil because it hinders the miniaturization of the IC card.

Therefore, in the conventional non-contact type data transfer system, resetting is performed by temporarily interrupting the power supply to the IC card. That is, the IC card is reset by restarting the data transfer system. However, this reset method in which the power supply is once stopped and then restarted has a problem that it takes time until the system becomes stable.

Therefore, the present invention provides a data transfer system to a semiconductor storage medium without providing a dedicated reset line and without interrupting power supply.
An object of the present invention is to provide a reset method capable of resetting a semiconductor storage medium.

[0007]

(1) A first invention of the present application is a bit indicating a data to be transferred by arranging a trigger pulse at a predetermined cycle T in a signal wave transmitted from a reader / writer device to a semiconductor storage medium. A pulse is arranged subsequent to this trigger pulse, and a data transfer system for transferring data using this signal wave as a medium is constructed, and an external reset command given from the reader / writer device to the semiconductor storage medium is
The signal wave is transmitted by not arranging a pulse for a predetermined period.

(2) A second invention of the present application is a pulse detection for detecting a pulse from a transmitted signal wave in order to realize a semiconductor storage medium suitable for carrying out the reset method according to the first invention. Means and the pulse detecting means starts timing from the time when the pulse is detected, and generates a reset signal when a predetermined set time D (D> T) has elapsed without detecting a new pulse. And means are provided in the semiconductor storage medium.

(3) In the third invention of the present application, the reset signal is released when a new pulse is detected after the reset signal is generated in the semiconductor storage medium according to the second invention. A reset release means for performing the reset is further provided.

[0010]

[Operation] The reset method according to the present invention is premised on the adoption of a new data transfer method. In this novel data transfer method (disclosed in the application <Reference No. A03112> of the same applicant as the present application on the same date), the signal wave transmitted from the reader / writer device to the semiconductor storage medium has a trigger pulse at a predetermined cycle T. Are arranged, and the bit pulse is arranged following this trigger pulse. Therefore, if the signal wave is in a normal data transfer state,
There will always be some pulse at least every period T. The reset method of the present application utilizes this property of the new data transfer method. That is, if the pulse is not arranged in the signal wave for the predetermined period T,
It can be recognized that the data transfer state is not normal. The present invention utilizes such a state as an external reset command.

When issuing an external reset command from the reader / writer device side, for example, the trigger pulse may be extracted from the signal wave for one cycle so that the state in which no pulse exists continues for a period longer than the cycle T. When the semiconductor storage medium detects such a state, it recognizes this as an external reset command. When the reset is released, the trigger pulse may be sent again. The semiconductor storage medium in the reset state performs the reset release operation when a new trigger pulse is detected.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on illustrated embodiments. FIG. 1 is a reader / writer device 1 to which a reset method in a data transfer system according to the present invention is applied.
00 and IC card 200 are block diagrams.
In the reader / writer device 100, the first coil 110 is
Each C card 200 is provided with a second coil 210. By electromagnetically coupling these coils, data transfer between them is performed. More specifically, power and clock are supplied from the reader / writer device 100 to the IC card 200, and data signals are transmitted and received between the two.

The reader / writer device 100 superimposes a signal wave containing information about data to be transferred and a carrier wave of a predetermined frequency to generate a modulated wave, and sends the modulated wave to the first coil 110. I do. On the other hand, the IC card 20
0 receives the transmitted modulated wave by the second coil 210, generates power source power by rectifying the received modulated wave, and generates a clock signal by extracting a predetermined frequency component from the received modulated wave. Then, the signal wave is detected by demodulating the received modulated wave.

FIG. 2 shows an example of the above-mentioned carrier wave, signal wave and modulated wave. As the carrier wave shown in FIG. 2A, an example of a triangular wave is shown for convenience, but a sine wave or a rectangular wave carrier may of course be used. The signal wave shown in Fig. 2 (b) is
It is binary data that takes either level L or H.
The essence of the present invention lies in the method of expressing information by this binary data, which will be described in detail later. The modulated wave shown in FIG. 2 (c) is a waveform obtained by modulating the signal wave shown in FIG. 2 (b) with the carrier wave shown in FIG. 2 (a), and is obtained by superimposing the carrier wave and the signal wave. A modulated wave as shown in FIG. 2C is given to the first coil 110, and this modulated wave is received by the second coil 210 on the IC card 200 side.

FIG. 3 is a block diagram showing the internal structure of the input stage of the IC card 200. This input stage is composed of four main constituent elements of a power input section 10, a clock input section 20, a signal input section 30, and a reset section 40. The received signal received by the second coil 210, that is, the modulated wave, is Is directly or indirectly given to each component of. The modulated wave provided to the power input unit 10 is rectified by the rectifier bridge
Is rectified by the ripple filter 12, smoothed by the ripple filter 12, and stabilized by the regulator 13.
Converted to C. Instead of passing the ripple filter, a capacitor may be used for smoothing. Further, in order to further stabilize the power supply voltage VCC, it is preferable to provide a capacitor between the power supply line and the ground line. In this way, the power input unit 10 extracts the power source power required for the operation of the IC card from the received signal. On the other hand, the modulated wave given to the clock input section 20 is inputted to the carrier clock level shifter 21. Here, the frequency component of the carrier wave is extracted and further divided by the frequency dividing circuit 22 to a predetermined frequency division ratio to generate a clock signal CLK having a predetermined frequency. In this way, the clock input unit 20 extracts the clock signal necessary for the operation of the IC card from the received signal. Further, the modulated wave given to the signal input unit 30 is A
It is demodulated in the M demodulation circuit 31. That is, FIG.
From the modulated wave shown in (c), the signal wave shown in FIG. 2 (b) is extracted. This signal wave is given to the trigger pulse detection circuit 32 and the reception data demodulation circuit 33. The trigger pulse detection circuit 32 detects the trigger pulse necessary for demodulating the received data and informs the received data demodulation circuit 33 of the detection timing. The reception data demodulation circuit 33 demodulates the reception data based on this detection timing and extracts the transfer data DATA from the reader / writer device 100. The demodulation method will be described later.

The reset section 40 for carrying out the reset method according to the present invention comprises an internal reset circuit 41, a pulse detection circuit 42, a counter circuit 43, and an RS flip-flop 44. The internal reset circuit 41 is
When the power supply voltage VCC output from the regulator 13 decreases, an internal reset signal RES (a bar indicating logic inversion is omitted in the specification due to restrictions in electronic application) is output. The internal reset signal RES is a signal for resetting each constituent circuit of the input stage of the IC card 200 shown in FIG. On the other hand, the pulse detection circuit 42
A pulse is detected from the signal wave demodulated by the demodulation circuit 31. The detected pulse is the counter circuit 43.
And the set terminal S of the RS flip-flop 44. At this time, if the external reset signal RST is output, the reset release is performed as described later. The counter circuit 43 has a function of counting the clock signal CLK supplied from the frequency dividing circuit 22 from the time when the pulse detecting circuit 42 detects a pulse. Then, when the count value reaches a predetermined set value, a reset input is given to the reset terminal R of the RS flip-flop 44. In this way, the RS flip-flop 44 outputs the external reset signal RST. The reset operation will be described later in detail.

With the above configuration, it is possible to transfer power, clock and data from the reader / writer device 100 to the IC card 200 while maintaining a physically non-contact state, and also to transfer an external reset command. become. Now, let us consider the representation format of the data to be transferred. The information to be transferred is transferred as a signal wave represented by binary data as shown in FIG. 2 (b). As shown in FIG. 4, the conventional general representation of binary data is performed by defining one of the bit states of level L and level H. For example, if the bit "0" is defined for the level L and the bit "1" is defined for the level H, the binary data shown in FIG. 4 indicates the information "01110100101". However, when binary data as shown in FIG. 4 is used as a signal wave and is transmitted on a carrier wave, accurate information transmission may be impaired. The waveforms of the respective waves shown in FIG. 2 are theoretical waveforms, and distortion and rounding occur in the actual waveforms. Especially, IC card 2
The modulated wave received by 00 is considerably blunt.
Therefore, even if the signal wave as shown in FIG. 4 is transmitted, since the signal wave demodulated on the IC card 200 side does not have such a clean waveform, accurate bit information may not be restored.

The reset method according to the present invention is premised on the adoption of a novel data transfer method capable of more reliable and accurate data transfer even in such an environment. Therefore, first, the new data transfer method will be described. Now, as shown in FIG. 5, trigger pulses P1, P2, P are generated at a predetermined cycle T.
Place 3, ... Then, each trigger pulse P1, P
2, a predetermined time t (t <T) from the arrangement positions of P3, ...
The bit information B1, B2 ... Are arranged at a position delayed by only.
In this embodiment, information regarding the presence or absence of a bit pulse is arranged as the bit information. More specifically, a bit is represented by information indicating whether or not a bit pulse exists at a predetermined position. For example, in FIG. 5, the bit information B1 represents a bit “1” because the bit pulse exists at a position delayed by a predetermined time t from the trigger pulse P1, and the bit information B2 represents the bit information B2 for a predetermined time from the trigger pulse P2. Since there is no bit pulse at a position delayed by t, bit "0" is represented. In this way, the trigger pulses P1, P
2, P3, ... Are pulses that always appear every period T, but bit pulses B1, B2, B3, ... Are pulses that appear or do not appear with a delay of time t from the trigger pulse. However, the trigger pulse and the bit pulse are exactly the same pulse when viewed as one pulse waveform, and are distinguished only by their existing positions.

In this way, in this transfer method, one bit of information to be transferred is expressed every cycle T. If the period T of the trigger pulse and the bit information arrangement delay time t are set in advance, information can be extracted bit by bit from the signal wave as shown in FIG. That is, on the receiving side, first, the trigger pulse P
1, P2, P3, ... May be detected, and the bit pulse may be detected based on this. Specifically, it is sufficient to detect whether or not the bit pulse rises when a time t has elapsed from the time when the trigger pulses P1, P2, P3 ,. In reality, a predetermined margin δ at time t (for example, a value of 1/2 of the width of the bit pulse is the margin δ).
Is set as the time t + δ, which is the trigger pulse P
1, when the set time t + δ has elapsed from the rise of P1, P2, P3, ...
It is preferable to perform a process for detecting whether it is at or at level L. If the signal wave is at level H, bit "1" is detected, and if it is at level L, bit "0" is detected.

FIG. 6 is a waveform diagram showing a more specific embodiment of the present invention. Now, as shown in FIG. 6 (a), "00
Consider the case of transferring 5-bit information "110".
In this case, a signal wave as shown in FIG. 6 (b) may be prepared. Trigger pulses are arranged in this signal wave at every predetermined cycle T, and depending on the presence or absence of a bit pulse at a time point when a predetermined set time t + δ has elapsed from the rising time point of each trigger pulse, as shown in FIG. Bit information is expressed. That is, there is no bit pulse in the first period and the second period, bit information "00" is expressed, and bit pulse is present in the third period and fourth period, and bit information "11" is given. That is, there is no bit pulse in the fifth period, and the bit information of “0” is expressed. Based on such a signal wave, a modulated wave as shown in FIG. 6C is obtained, and the transfer information is transmitted to the IC card 200 in such a modulated wave format.

In the input stage of the IC card 200 shown in FIG. 3, first, the AM demodulation circuit 31 extracts the signal wave shown in FIG. 6B from the modulated wave shown in FIG. 6C. Then, the trigger pulse detection circuit 32 detects from this signal wave
A trigger pulse that appears every predetermined period T is detected, and a trigger signal is given to the reception data demodulation circuit 33 when a predetermined time t + δ has elapsed from this detection timing. The reception data demodulation circuit 33 detects the level of the signal wave at the time when this trigger signal is given, and outputs a bit “1” if the level is H and a bit “0” if the level is L. The transfer data DATA is formed by the bit string thus output. If such a bit detection method is used, even if the signal wave is blunted,
Accurate bit detection is possible.

Next, the reset method, which is the gist of the present invention, will be described. The IC card 200 of this embodiment is provided with two types of reset signals. That is, the internal reset signal RE generated inside the IC card
S and an external reset signal RST generated based on a reset command from the outside. As shown in FIG. 3, the internal reset signal RES is generated by the internal reset circuit 41. The internal reset circuit 41 is the regulator 1
When the power supply voltage VCC output from 3 decreases, the internal reset signal RES is output. This output operation is shown in FIG.
As shown in the graph, there is hysteresis. That is, the power supply voltage VCC gradually rises and the first threshold value V
When it reaches TH, the internal reset signal RES rises. On the other hand, when the power supply voltage VCC drops, the internal reset signal RES is reached when the second threshold value VTL is reached.
Falls down. After all, the internal reset circuit 41 monitors the power supply voltage VCC supplied to the inside of the IC card, keeps the internal reset signal RES in the “H” state when the voltage is normal, and when the voltage drops, the internal reset signal RES is kept internal. Reset signal RE
Performs the function of keeping S at "L".

From the side of the reader / writer device 100, the IC
Conventionally, when the card is reset (when the external reset is applied), the internal reset signal RES is used. That is, the reader / writer device 10
If 0 temporarily suspends the transmission of the modulated wave, the power supply unit 10 cannot supply the normal power supply voltage VCC,
The internal reset signal RES can be automatically generated. However, as described above, this reset method in which the power supply is once stopped and then restarted has a problem that it takes time until the system becomes stable. The reset method according to the present invention is
Utilizing the properties of the new data transfer system described above,
The external reset signal RST is generated by a completely different method.

FIG. 8 is a time chart for explaining the external reset method according to the present invention. Now, it is assumed that the internal reset signal RES has risen at time t0 by activating this data transfer system. Figure 3
As shown in FIG.
Since 1 has a function of detecting the pulse of the demodulated signal wave, the trigger pulse P1 included in the signal wave is detected at time t1. Then, the pulse detection circuit 4
The trigger pulse P1 detected by 2 is the counter circuit 43.
And RS flip-flop 44. The counter circuit 43 uses the clock signal CLK to start counting from the rising time t1 of the trigger pulse P1. On the other hand, the RS flip-flop 44, to which the pulse signal is applied to the set input terminal S, operates to raise the logic output Q. Thus, the external reset signal RST rises at time t1. This external reset signal RST
Always maintains the "H" state during data transfer, but changes to the "L" state when an external reset command is given from the reader / writer device 100.

When the count value reaches a predetermined set value D (D> T), the counter circuit 43 receives the RS flip-flop 4
4 has a function of giving a pulse signal to the reset input terminal R. When the reader / writer device 100 is transferring data, a trigger pulse always appears in the signal wave every period T. That is, at the time t2, the next trigger pulse P
2 will appear. Therefore, the counter circuit 43
Will receive a new pulse input before counting up to the predetermined set value D. The counter circuit 43 is
At time t2, the count value so far is returned to the initial value 0, and the counting operation is started again. On the other hand, at the time t2, the set input terminal S of the RS flip-flop 44 is
Since the trigger pulse P2 is given, the logic output Q, that is, the external reset signal RST is still "H".
Keep the state of.

As described above, while the data transfer is performed through the signal wave, the trigger pulse always appears in the signal wave every period T. Therefore, when a signal wave in which no pulse exists is transmitted over a period exceeding the period T, it can be arranged to mean a reset command from the outside. For example, in FIG. 8, consider the operation in the case where the trigger pulse P3, which should have been placed apart from the trigger pulse P2 by the period T, does not exist at time t3. In this case, since a new pulse is not input to the counter circuit 43 even at time t3, the counter circuit 43 continues counting as it is. Thus, at time t4,
When the count value of the counter circuit 43 reaches a predetermined set value D, the counter circuit 43 outputs a reset pulse to the reset input terminal R of the RS flip-flop 44. As a result, the logical output Q of the RS flip-flop 44, that is, the external reset signal RST is inverted to the “L” state, and this inverted state continues until a new pulse appears in the signal wave. When a new pulse appears, the reset is released at that point, and the external reset signal RST is again "H".
Return to the state of.

After all, from the reader / writer device 100 side, I
In order to apply an external reset to the C card 200, the signal wave is processed such that no pulse is placed for a predetermined set period D, and in order to release the reset, a new pulse is placed after that. It will be good. Since the transmission of the modulated wave is not interrupted, the IC card 200
On the side, the supply of the power supply voltage VCC and the clock signal CLK is not interrupted. Although the above embodiment does not mention the relationship between the internal reset signal RES and the external reset signal RST, it is preferable that the external reset signal is also applied when the internal reset signal is applied. ..

The present invention has been described above based on the illustrated embodiment, but the present invention is not limited to this embodiment and can be implemented in various modes other than this. For example, the configuration of the reset unit 40 in FIG. 3 is shown as an example, and the same function may be realized by other circuit configurations. In addition, although the present invention is applied to the data transfer system related to the IC card in the above-described embodiments, the present invention can be widely applied not only to the IC card but also to the data transfer system using the semiconductor storage medium. is there.

[0029]

As described above, according to the reset method of the semiconductor storage medium according to the present invention, the reset command from the outside is recognized based on the presence or absence of the pulse in the signal wave, so that the dedicated reset is performed. It becomes possible to reset the semiconductor storage medium without providing a line and without interrupting the power supply.

[Brief description of drawings]

FIG. 1 is a block diagram showing a reader / writer device 100 and an IC card 200 to which a reset method in a data transfer system according to the present invention is applied.

FIG. 2 is a waveform diagram showing an example of carrier waves, signal waves, and modulated waves used in the data transfer system related to the present invention.

3 is a block diagram showing a configuration of an input stage of the IC card 200 shown in FIG.

FIG. 4 is a waveform diagram showing the expression contents of a signal wave in the conventional transfer method.

FIG. 5 is a waveform diagram showing an expression content of a signal wave in the data transfer system related to the present invention.

FIG. 6 is a diagram showing a relationship among transfer information, signal waves, and modulated waves in the data transfer system related to the present invention.

FIG. 7 is a waveform diagram illustrating a method of generating an internal reset signal RES according to the present invention.

FIG. 8 is a waveform diagram illustrating a method of generating an external reset signal RST in the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Electric power input part 11 ... Rectifier bridge 12 ... Ripple filter 13 ... Regulator 20 ... Clock input part 21 ... Carrier clock level shifter 22 ... Dividing circuit 30 ... Signal input part 31 ... AM demodulation circuit 32 ... Trigger pulse detection circuit 33 ... Received data demodulation circuit 40 ... Reset section 41 ... Internal reset circuit 42 ... Pulse detection circuit 43 ... Counter circuit 44 ... RS flip-flop 100 ... Reader / writer device 110 ... First coil 200 ... IC card 210 ... Second coil P1, P2, P3 ... Trigger pulse B1, B2 ... Bit pulse (bit information) RES ... Internal reset signal RST ... External reset signal

Claims (3)

[Claims] 1. A signal pulse transmitted from a reader / writer device to a semiconductor storage medium is provided with a trigger pulse at a predetermined period T, and a bit pulse indicating data to be transferred is provided subsequent to the trigger pulse, and this signal is provided. A reset method used in a data transfer system for transferring data using waves as a medium, wherein an external reset command given from a reader / writer device to a semiconductor storage medium is transmitted by arranging no pulse in the signal wave for a predetermined period. A reset method in a data transfer system to a semiconductor storage medium, comprising: 2. A semiconductor storage medium suitable for carrying out the reset method according to claim 1, wherein the pulse detection means detects a pulse from a transmitted signal wave, and the pulse detection means detects a pulse. Resetting means for generating a reset signal when time measurement is started from a time point and a predetermined set time D (D> T) has elapsed without detection of a new pulse, and a semiconductor device comprising: Storage medium. 3. The semiconductor storage medium according to claim 2, further comprising reset release means for releasing the reset signal when a new pulse is detected after the reset signal is generated. And semiconductor storage medium.