JPH05134940A - Static memory device and its memory back-up system - Google Patents

Static memory device and its memory back-up system

Info

Publication number
JPH05134940A
JPH05134940A JP3299437A JP29943791A JPH05134940A JP H05134940 A JPH05134940 A JP H05134940A JP 3299437 A JP3299437 A JP 3299437A JP 29943791 A JP29943791 A JP 29943791A JP H05134940 A JPH05134940 A JP H05134940A
Authority
JP
Japan
Prior art keywords
power supply
memory device
battery
static
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3299437A
Other languages
Japanese (ja)
Inventor
Koji Okada
耕児 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP3299437A priority Critical patent/JPH05134940A/en
Publication of JPH05134940A publication Critical patent/JPH05134940A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To lose neither a file nor a data even though a main power supply is cut off. CONSTITUTION:When a main power supply 1 is cut off, a power supply control circuit 3 switches the supply 1 to an auxiliary power supply 2. Therefore the register contents of a CPU 4 are immediately written into a static memory device 6 which contains a back-up battery. Then the resettable information is backed up when the power is supplied again from the supply 1. When the power is supplied from the supply 1 while the memory is kept in the device 6 and a static memory 5 containing a battery, these memory devices are not checked.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はコンピュータ,ワードプ
ロセッサ等の情報処理機器に用いられるスタティック型
メモリ装置とそのメモリバックアップ方式に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static type memory device used in information processing equipment such as a computer and a word processor, and a memory backup system thereof.

【0002】[0002]

【従来の技術】従来のスタティック型メモリ装置は電源
供給がストップすると直ちにそれまで保持していた内容
を失ってしまう。
2. Description of the Related Art In a conventional static memory device, the contents held until then are lost immediately when the power supply is stopped.

【0003】[0003]

【発明が解決しようとする課題】上述した従来のスタテ
ィック型メモリ装置では、情報処理機器の操作中に誤っ
て電源スイッチを押した場合、もしくは停電した場合に
は、直ちに電源供給が切断されて作成中のファイルやデ
ータのセーブ動作を行なうことができないので、必要と
するファイル,データが失われてしまう問題点がある。
In the conventional static memory device described above, the power supply is immediately cut off when the power switch is erroneously pressed during the operation of the information processing device or a power failure occurs. Since the save operation of the files and data inside cannot be performed, there is a problem that necessary files and data are lost.

【0004】[0004]

【課題を解決するための手段】第1の発明のスタティッ
ク型メモリ装置は、充電可能なバックアップ用バッテリ
を内蔵したことを特徴とする。
The static type memory device of the first invention is characterized by having a built-in rechargeable backup battery.

【0005】第2の発明のメモリバックアップ方式は、
内部に充電可能なバックアップ用バッテリを有するスタ
ティック型メモリ装置と、電源切断時に電源供給を主電
源から補助電源に切り替えると共に中央処理装置の内容
を前記スタティック型メモリ装置に記憶させる電源制御
回路とを備え、前記スタティック型メモリ装置に記憶が
保持されている場合には電源投入時にメモリのチェック
を行なわないことを特徴とする。
The memory backup system of the second invention is
A static memory device having a rechargeable backup battery therein, and a power supply control circuit for switching the power supply from the main power supply to the auxiliary power supply when the power is turned off and for storing the contents of the central processing unit in the static memory device are provided. The memory is not checked when the memory is held in the static memory device when the power is turned on.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図1は第1の発明のスタティック型メモリ装置の一
実施例を示すブロック図、図2は第2の発明のメモリバ
ックアップ方式の一実施例を示すブロック図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a static type memory device of the first invention, and FIG. 2 is a block diagram showing an embodiment of a memory backup system of the second invention.

【0007】図1において、バックアップ用バッテリ内
蔵スタティック型メモリ装置6はスタティックメモリI
C61と、充電源,接地源をスタティックメモリIC6
1と共有する充電可能なバックアップ用バッテリ62を
1チップに納めたものである。
In FIG. 1, a static type memory device 6 with a built-in backup battery is a static memory I.
Static memory IC6 for C61, charging source and ground source
The rechargeable backup battery 62 shared with the No. 1 is contained in one chip.

【0008】次に図2において、主電源部1から主電源
信号01が供給されているときには、電源制御回路3は
中央処理装置4,バッテリ内蔵スタティック型メモリ
5,バックアップ用バッテリ内蔵スタティック型メモリ
装置6にそれぞれ電源信号03,04,05を供給して
いる。また、中央処理装置4とバッテリ内蔵スタティッ
ク型メモリ5間のアクセス信号06,データ信号07の
みでデータのやり取りを行なっている。
In FIG. 2, when the main power supply signal 01 is supplied from the main power supply unit 1, the power supply control circuit 3 includes a central processing unit 4, a static type memory with built-in battery 5, a static type memory device with built-in backup battery. Power supply signals 03, 04, 05 are supplied to each of the terminals 6. Further, data is exchanged between the central processing unit 4 and the static type memory 5 with a built-in battery only by the access signals 06 and data signals 07.

【0009】主電源1から主電源信号01の供給が切断
されると、電源制御回路3は直ちに補助電源2より補助
電源信号02を受けて中央処理装置4,バッテリ内蔵ス
タティック型メモリ5,バックアップ用バッテリ内蔵ス
タティック型メモリ装置6へ電源信号03,04,05
を供給し続ける。そして、中央処理装置4はバッテリ内
蔵スタティック型メモリ5へのアクセス信号06を中止
し、バックアップ用バッテリ内蔵スタティック型メモリ
装置6にデータ信号08を送信し、主電源1が復帰した
時に必要なレジスタの内容を書き込む。これにより、バ
ッテリ内蔵スタティック型メモリ5,バックアップ用バ
ッテリ内蔵スタティック型メモリ装置6はメモリの1チ
ップ中にバッテリを内蔵しているので、そのバッテリが
充電されている間、主電源1,補助電源2から主電源信
号01,補助電源信号02がストップして電源制御回路
3からの電源信号03,04,05の供給が切断されて
も復帰可能な情報をセーブしている。
When the supply of the main power supply signal 01 from the main power supply 1 is cut off, the power supply control circuit 3 immediately receives the auxiliary power supply signal 02 from the auxiliary power supply 2 and the central processing unit 4, the static memory with a built-in battery 5, and the backup. Power supply signals 03, 04, 05 to the static memory device 6 with built-in battery
Continue to supply. Then, the central processing unit 4 cancels the access signal 06 to the static type memory 5 with built-in battery, transmits the data signal 08 to the static type memory device 6 with built-in battery for backup, and registers the registers necessary when the main power supply 1 is restored. Write the content. As a result, since the static memory 5 with built-in battery and the static memory device 6 with built-in backup battery have a built-in battery in one chip of the memory, while the battery is being charged, the main power supply 1, the auxiliary power supply 2 Therefore, even if the main power supply signal 01 and the auxiliary power supply signal 02 are stopped and the supply of the power supply signals 03, 04, 05 from the power supply control circuit 3 is cut off, the information that can be restored is saved.

【0010】主電源1から再度電源信号01が供給され
ると、中央処理装置4はバッテリ内蔵スタティック型メ
モリ5,バックアップ用バッテリ内蔵スタティック型メ
モリ装置6のメモリチェックを行なわずにバックアップ
用バッテリ内蔵スタティック型メモリ装置6の内容をデ
ータ信号09によりレジスタ部に書き込む。
When the power source signal 01 is supplied again from the main power source 1, the central processing unit 4 does not perform the memory check of the static type memory 5 with built-in battery and the static type memory device 6 with built-in battery for backup, and the static type built-in battery for backup is used. The contents of the memory device 6 are written in the register section by the data signal 09.

【0011】[0011]

【発明の効果】以上説明したように本発明は、使用者が
誤って電源スイッチを押した場合もしくは停電した場合
でも、スタティック型メモリに接続されているバッテリ
が電源を供給している間は再度主電源を投入すればファ
イルやデータを失うことがなく、電源切断時の状態で作
業が続行できるという効果を有する。
As described above, according to the present invention, even when the user mistakenly presses the power switch or a power failure occurs, the battery connected to the static type memory is supplied again while the power is being supplied. When the main power is turned on, files and data are not lost, and the work can be continued in the state when the power is turned off.

【図面の簡単な説明】[Brief description of drawings]

【図1】第1の発明のスタティック型メモリ装置の一実
施例を示すブロック図である。
FIG. 1 is a block diagram showing an embodiment of a static memory device of the first invention.

【図2】第2の発明のメモリバックアップ方式の一実施
例を示すブロック図である。
FIG. 2 is a block diagram showing an embodiment of a memory backup system of the second invention.

【符号の説明】[Explanation of symbols]

1 主電源 2 補助電源 3 電源制御回路 4 中央処理装置 5 バッテリ内蔵スタティック型メモリ 6 バックアップ用バッテリ内蔵スタティック型メモ
リ装置 01 主電源信号 02 補助電源信号 03,04,05 電源信号 06 アクセス信号 07,08,09 データ信号 61 スタティックメモリIC 62 バックアップ用バッテリ
1 Main Power Supply 2 Auxiliary Power Supply 3 Power Control Circuit 4 Central Processing Unit 5 Static Memory with Built-in Battery 6 Static Memory Device with Built-in Battery for Backup 01 Main Power Signal 02 Auxiliary Power Signal 03, 04, 05 Power Signal 06 Access Signal 07, 08 , 09 Data signal 61 Static memory IC 62 Battery for backup

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 充電可能なバックアップ用バッテリを内
蔵したことを特徴とするスタティック型メモリ装置。
1. A static memory device having a built-in rechargeable backup battery.
【請求項2】 内部に充電可能なバックアップ用バッテ
リを有するスタティック型メモリ装置と、電源切断時に
電源供給を主電源から補助電源に切り替えると共に中央
処理装置の内容を前記スタティック型メモリ装置に記憶
させる電源制御回路とを備え、前記スタティック型メモ
リ装置に記憶が保持されている場合には電源投入時にメ
モリのチェックを行なわないことを特徴とするメモリバ
ックアップ方式。
2. A static memory device having a rechargeable backup battery therein, and a power supply for switching the power supply from a main power supply to an auxiliary power supply when the power is turned off and for storing the contents of the central processing unit in the static memory device. A memory backup system comprising a control circuit, wherein the memory is not checked when the power is turned on when the memory is held in the static memory device.
JP3299437A 1991-11-15 1991-11-15 Static memory device and its memory back-up system Withdrawn JPH05134940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3299437A JPH05134940A (en) 1991-11-15 1991-11-15 Static memory device and its memory back-up system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3299437A JPH05134940A (en) 1991-11-15 1991-11-15 Static memory device and its memory back-up system

Publications (1)

Publication Number Publication Date
JPH05134940A true JPH05134940A (en) 1993-06-01

Family

ID=17872567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3299437A Withdrawn JPH05134940A (en) 1991-11-15 1991-11-15 Static memory device and its memory back-up system

Country Status (1)

Country Link
JP (1) JPH05134940A (en)

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990204