JPH05134656A - Image display size varying circuit - Google Patents

Abstract

PURPOSE:To expand or contract digital image data by not only integer multiple and reciprocal of an integer multiple but also arbitrary magnification. CONSTITUTION:By thinning out a 294 picture element portion from lateral 736 picture elements, an enlarged image in the transverse direction is obtained. An arithmetic circuit 1 combines 294/736 with a fractional expression (1/2)-(1/9)+(1/94) and obtains denominators '2', '9' and '94'. A thinning-out signal generating circuit 19 generates a thinning-out signal consisting of one piece of pulse per '2' times, the pulse of the thinning-out signal is subjected to thinning-out release by one piece per '9' times, and the thinning-out release is inhibited by one piece per '94' times. A thinning-out circuit 17 thins out a timing signal by its thinning-out signal and outputs it to an image storage circuit 21. When the image storage circuit 21 reads out image data by the timing signal, enlarged image data is obtained. When the timing signal is used as the writing signal of the image data to the image storage circuit 21, contracted image data is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display size varying circuit, and more particularly to improvement of an image display size varying circuit for enlarging or reducing a digitally converted image signal of, for example, NTSC system according to control data.

[0002]

2. Description of the Related Art Conventionally, an image display size variable circuit of this kind has an image not showing image data in display pixels a, b, c, d, e ... Shown in FIG. 10 when enlarging digital image data. A configuration is known in which a read clock signal stored in a memory circuit and thinned out based on enlargement control data output from a microcomputer (not shown) or the like is read from the image memory circuit and reproduced and displayed. For example, if every other read clock signal is thinned out, the display pixel a,
The image data in b, c, d, e ... Is retained for one clock and read out, and the display pixels a, a, b, b ... Enlarged twice as shown in FIG. 11 are reproduced. ..

On the other hand, when the digital image data is reduced, the write clock signal is thinned out based on the reduction control data to write the image data in the display pixels a, b, c, d, ... It suffices to read the pixel data with a read clock signal which is not changed and reproduce and display it. For example, when the write clock signal is thinned out every other pixel, the contents of the display pixels a, b, c, d, e ... Are drawn for one clock and stored in the image storage circuit. , The display pixels a, c, e ... Reduced to 1/2 as shown in FIG. 12 are reproduced.

[0004]

However, in the conventional image display size varying circuit, various enlarging or reducing screens can be obtained by appropriately varying the enlarging or reducing control data from the microcomputer. Integer multiples of 2, 4, 8 times, etc., 1/2, 1 / for reduction
There is a drawback that the enlargement or reduction ratio is limited to an integral multiple or an integral fraction, such as 4 or 1/8. The present invention has been made to solve such a conventional drawback, and an image can be enlarged or reduced not only by an integral multiple or an integral fraction of the number of displayable pixels on the display screen but also by an arbitrary magnification. An object is to provide a circuit for varying the image display size.

[0005]

In order to solve such a problem, the present invention sets the number of display pixels in the vertical and / or horizontal directions to be displayed on the image reproduction screen as A, and is thinned from this display pixel number A. Let B be the number of thinned pixels and 1 / C be the most approximate value that is greater than B / A.
The value closest to the difference between and is 1 / D, and its B / A and 1 / C
When the value closest to the difference between and with 1 / D is 1 / E, an arithmetic circuit for obtaining C, D, and E with integer values is formed, and one pulse is provided every C times. A thinning-out signal generation circuit that generates a thinning-out signal by canceling the thinning-out signal by one pulse every D times and canceling one pulse every D times at E-time, and a thinning-out signal generation circuit A thinning circuit for thinning a predetermined timing signal by a thinning signal and an image storage circuit for reading or writing image data by the thinned timing signal are included.

[0006]

In the present invention equipped with such means, 1 in C times
If the thinning signal generator circuit outputs a thinning signal consisting of individual pulses and the thinning circuit thins out the timing signals, it will be in an excessively thinned state. However, by thinning out the thinning signal pulse by one pulse every D times. When it is output, it will be in a state of insufficient thinning, and E
When one pulse thinning of D times is canceled at a rate of once, the timing signals are thinned almost evenly. Then, when the stored image data is read by adding the timing signals, which are thinned out substantially evenly, to the image storage circuit as a read signal, enlarged image data is obtained, and the image data is written in addition to the image storage circuit as a write signal. Then, the image data is stored in the image storage circuit in the reduced state, and the reduced image is obtained from the read image data.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an image display size varying circuit according to the present invention. Since the enlargement function configuration and the reduction function in the present invention are substantially the same, for convenience, the enlargement function and the enlargement function configuration in the lateral direction will be described. In FIG. 1, an arithmetic circuit 1 is composed of, for example, a CPU and a microcomputer having a built-in operation program for the CPU, and a personal computer having the microcomputer, and calculates an integer value for obtaining a desired magnification. is there. That is, the number of display pixels in the horizontal direction in a CRT (cathode ray tube) as a reproduction image device is A, and the number of thinned pixels thinned from this display pixel number A is B to obtain an enlarged image of A / B times. The value of B / A is expressed by a combination of fractions where the numerator is 1.

In this simple combination of fractions, the most approximate value larger than the value of B / A is set to 1 / C, and those B / A and 1 / C are set.
The value closest to the difference between and is 1 / D, and its B / A and 1 / C
When the value closest to the difference between 1 / D and 1 / D is 1 / E, B / A≈ (1 / C) − (1 / D) + (1 / E) Of course, depending on the value, B / A = (1 /
C) and B / A = (1 / C)-(1 / D) in some cases. The arithmetic circuit 1 obtains integer values C, D and E, which are denominators of these fractions, by setting the number of pixels A and the number of pixels B from outside or by a program, and a programmable counter (PC and PC in FIG. 1). Abbreviated) 3, 5,
7 is connected to the bus.

For example, when a read pulse signal (described later) for 294 pixels is thinned out in a CRT having 736 pixels in the horizontal direction to obtain a magnified image of 1.399 times, 294 / 736≈ (1/2)-(1 / 9) + (1/94), and the arithmetic circuit 1 sets the number of display pixels 736 and the number of thinned pixels 294 in the horizontal direction to obtain integer values "2", "9" and " 94 "to the programmable counters 3, 5, and 7. The programmable counter 3 is, for example, a programmable 1/2 counter that synchronizes with a timing signal (see FIG. 2) described later and counts down the set number “2” that is input, and is connected to the decoder 9. Programmable counter 5
Is a 1/9 counter and is connected to the decoder 11, and the programmable counter 7 is a 1/94 counter and is connected to the decoder 13.

The decoder 9 outputs one pulse and outputs a first count signal to the gate circuit 15 when the programmable counter 3 counts "2" as shown in FIG. The decoder 11 outputs one pulse to the gate circuit 15 when the programmable counter 5 subtracts and counts “9” as shown in FIG. 2, and the decoder 13 outputs the second count signal. When 7 counts down "94", it outputs one pulse and outputs the third count signal to the gate circuit 15. The gate circuit 15 uses the first count signal from the decoder 9 as a thinning signal,
The thinning circuit 1 thins out one pulse by the count signal, cancels the thinning by the second count signal by the third count signal, and thins out the thinning signal as shown in FIG.
7 is output.

These programmable counters 3, 5,
7, the decoders 9, 11, 13 and the gate circuit 15 form a thinning signal generation circuit 19. The thinning circuit 17 is a CRT for reading, which will be described later, based on the thinning signal.
The pulse is thinned out from the timing signal serving as the synchronization signal, and the thinned timing signal as shown in FIG. 3A is used as the read pulse signal (readout signal) in the image storage circuit 2.
It is output to 1. The image storage circuit 21 is a conventionally known readable and writable image memory (VRAM) in which image data is read at a predetermined timing, and the timing is set to, for example, the rising edge of the pulse of the timing signal thinned out as shown in FIG. 3B. In addition, the image data is read out.
In the portion of the timing signal corresponding to the thinned pulse, the image data read by the immediately preceding pulse is held and output.

Next, the operation of the thus-configured image display size varying circuit of the present invention for obtaining a magnified image of 1.399 times on a CRT having 736 horizontal display pixels will be described. As shown in FIG. 4, when the digital image data 1 to 48 are written in the image storage circuit 21 at the same timing, if the number of display pixels 736 and the number of enlarged pixels 294 are set in the arithmetic circuit 1 of FIG. A fractional mathematical expression of 294 / 736≈ (1/2)-(1/9) + (1/94) is created in the circuit 1, and integer values “2”, “9” and “94” which are denominators of the above fractions are created. Is output to the programmable counters 3, 5, and 7.

As shown in FIG. 2, the programmable counter 3 counts down "2", the decoder 9 outputs the first count signal to the gate circuit 15, and the programmable counter 5 counts down "9". The decoder 11 outputs the second count signal to the gate circuit 15, the programmable counter 7 counts down “94”, and the decoder 13 outputs the third count signal to the gate circuit 15. The gate circuit 15 thins out the first count signal from the decoder 9 with the second count signal, but if the first count signal is always thinned out with the second count signal, the third count signal is thinned out. Is input, the thinning-out by the second count signal is released, and the thinning-out signal generating circuit 19 outputs the thinned-out thinning-out signal to the thinning-out circuit 17.

The decimation circuit 17 decimates the timing signal set as the CRT synchronization signal by the decimation signal and outputs it to the image storage circuit 21. The image storage circuit 21 produces the decimation timing as shown in FIGS. 3A and 3B. The image data is read at the same timing as the rising edge of the signal pulse. 3C and 3D show a conventional timing signal which is not thinned out and image data which is read out at the same timing. At this time, a portion of the timing signal corresponding to the rising edge of the thinned pulse is thinned, and as shown in the horizontal direction (X direction) of FIG. 5, when the read pulse signal is thinned, new image data is generated. The image data immediately before is not read out and held in an extended manner.

In other words, in the present invention, the first count signal from the decoder 9 decimates the read pulse of the image data, and the second count signal from the decoder 11 decimates the decimation once every nine times. At the same time, the third count signal from the decoder 13 releases the thinning stop by the second count signal once every 94 times,
The enlarged image data of 1.399 times is output. Although the above description is for the horizontal enlargement function configuration, the vertical displayable pixel number A and the thinned pixel number B are set in the arithmetic circuit 1 in FIG. 1, and the horizontal synchronizing signal is used as the timing signal for thinning. In addition to the circuit 17, if the thinning signal from the thinning signal generating circuit 19 is thinned and added to the image storage circuit 21, the image storage circuit 21 is driven by the vertical timing signal as shown in the vertical direction (Y direction) of FIG. A certain line is thinned out and output, and the thinned out image data line is extended and output.

In the image display size variable circuit having the circuit configuration as shown in FIG. 1 corresponding to the horizontal and vertical directions, as shown in FIG. 6, the original reproduced image in the narrow window area in the display area is displayed in the display area. It can be fully expanded and played. By appropriately selecting the pixel numbers A and B that determine the setting ratio and inputting them to the arithmetic circuit 1, an arbitrary enlarged size image can be obtained.
Moreover, it is possible to set the horizontal and vertical directions at different enlargement ratios, or to set only one of the horizontal and vertical directions at the enlargement ratio, which is determined by the number of pixels A and B set in the arithmetic circuit 1. The configuration described above is suitable for actually obtaining an enlarged image that does not differ from the enlargement ratio set in the arithmetic circuit 1 of FIG. 1, but if a slight difference is allowed, the programmable counter 7 and the decoder 13 are omitted. It is also possible to always thin out the first count signal from the decoder 9 by the second count signal from the decoder 11 to create a thinning signal.

On the other hand, for an image having a high resolution and a large number of pixels, it is possible to additionally connect another programmable counter to the arithmetic circuit 1 and perform thinning with a small error. That is, the difference between B / A and 1 / C is obtained by the above formula B / A≈ (1 / C) − (1 / D) + (1 / E), and this difference and 1 / D
Then, the difference between this difference and 1 / E is calculated,
The closest approximation to the final difference is 1 / F, and B / A≈ (1 / C)-(1 / D) + (1 / E)-(1 / F) It can be configured such that the thinning processing can be performed by prohibiting the thinning cancellation once every E times.

As described above, in the present invention, fractional terms are sequentially increased to form an infinite term fractional expression, and not only an integer-enlarged size but also an arbitrary-enlarged size can be formed. Although the present invention described above has the enlargement function configuration, it is possible to configure the reduction function. That is, in FIG. 1, the vertical display pixel number A and the thinned pixel number B are set in the arithmetic circuit 1,
The decimating circuit 17 decimates a timing signal as a clock signal or a horizontal synchronizing signal with the decimating signal from the gate circuit 15 and adds it to the image storage circuit 21, and the image storage circuit 21 decimates the timing signal (write pulse signal ) To control the horizontal and vertical writing of image data. With this configuration, as shown in FIG. 7, the image data is horizontally and vertically written in the image storage circuit 21 by the thinned timing signal, and the image data corresponding to the thinned portion in the timing signal is generated. The image data immediately before is extended and written.

Therefore, if the reading is performed by a constant read timing signal that is not thinned out, reduced image data can be obtained as shown in FIG. The reduction ratio at this time is indicated by B / A. With such reduced image data, the original reproduced image is reduced as shown in FIG. That is, in the image display size varying circuit of the present invention, it is possible to perform the enlargement or reduction operation depending on whether the thinned-out timing signal is used as the read signal or the write signal of the image storage circuit 21. Moreover, if the display pixel number A and the thinning-out pixel number B to be thinned from this display pixel number A are arbitrarily set within the displayable pixel number of the image display device, an arbitrary enlargement ratio A / B,
A reduction ratio B / A is obtained. Further, according to the present invention,
Even when an image is displayed on a CRT or the like having a higher resolution than the general number of display pixels with respect to the number of input pixels, it is possible to perform uniform enlarged display on the entire display area.

[0020]

As described above, according to the present invention, the number of display pixels in the horizontal and / or vertical direction in the displayable image area is A.
, The thinning pixel number is B, and the numerator is 1 to approximate the value of B / A by a combination of fractions, and as a combination of such fractions, the closest approximation value 1 / C larger than the value of B / A, and The value 1 / D that is the closest to the difference between B / A and 1 / C, and the value 1 / E that is the closest to the difference between B / A and 1 / C and the difference between 1 / D are calculated. The decimating signal consisting of one pulse is decimated by one pulse every D times, and one decimating signal is canceled every D times at the rate of E times, and the decimating signal is output. The timing signal is thinned out and added to the image storage circuit. Therefore, if the thinned-out timing signal is added as a read signal to the image storage circuit, the read stored image data becomes enlarged image data, and if it is added as a write signal to the image storage circuit, the image data is displayed in a reduced state. The data can be stored in the memory circuit, and the read image data becomes reduced image data. Moreover, by arbitrarily setting the integer values A and B, it is possible to obtain not only an integral multiple or an integer fraction but also an arbitrary enlargement ratio and reduction ratio.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image display size varying circuit according to the present invention.

FIG. 2 is a timing waveform chart for explaining the operation of the image display size varying circuit of FIG.

FIG. 3 is a timing waveform diagram showing the timing of writing or reading image data in the image display size variable circuit of the present invention in comparison with a conventional example.

FIG. 4 is a diagram showing a state of writing image data to an image storage circuit during an enlarging operation in the present invention.

FIG. 5 is a diagram showing the timing of reading image data from the image storage circuit during the enlarging operation according to the present invention.

FIG. 6 is a diagram comparing a 1 × reproduction image and an enlarged reproduction image according to the present invention.

FIG. 7 is a diagram showing a state of writing image data to an image storage circuit during a reduction operation according to the present invention.

FIG. 8 is a diagram showing the timing of reading image data from the image storage circuit during the reduction operation according to the present invention.

FIG. 9 is a diagram comparing a 1 × reproduction image and a reduced reproduction image according to the present invention.

FIG. 10 is a schematic diagram showing a state in which image data is reproduced and displayed at the same size.

FIG. 11 is a schematic diagram showing a conventional state in which image data is enlarged and reproduced and displayed.

FIG. 12 is a schematic diagram showing a conventional state in which image data is reduced and reproduced and displayed.

[Explanation of symbols]

 1 arithmetic circuit 3, 5, 7 programmable counter (PC) 9, 11, 13 decoder 15 gate circuit 17 thinning circuit 19 thinning signal generating circuit 21 image storage circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location // H04N 1/387 8839-5C

Claims (1)

[Claims] 1. The number of vertical and / or horizontal display pixels displayed on the image reproduction screen is A, the number of thinned pixels thinned from this display pixel number A is B, and the most approximate value larger than B / A is set. Is 1 / C, the value closest to the difference between B / A and 1 / C is 1 / D, and the value closest to the difference between B / A and 1 / C and the difference between 1 / D is Is set to 1 / E, an arithmetic circuit for obtaining C, D and E by integer values, and a thinning signal having one pulse at C times based on the integer values C, D and E at D times. A thinning-out signal generating circuit for thinning out with one pulse and releasing one pulse every D times at the rate of E times to generate the thinning-out signal, and a predetermined thinning-out signal according to the thinning-out signal. Image data is read by the thinning circuit for thinning the timing signal and the thinned timing signal. An image display size variable circuit, comprising: