JPH05130089A - Data transmitter - Google Patents

Abstract

PURPOSE:To attain data transmission in multi-stage by absorbing a frequency deviation without making circuit configuration complicated, making the circuit large in its scale and too large delay for data transmission. CONSTITUTION:This transmitter is provided with an edge detection section 5 detecting the edge of input data, a data fetch timing signal generating section 7 outputting a data fetch timing signal based on an edge detected by the edge detection section 5, a data storage section 9 fetching data synchronously with the data fetch timing signal outputted from the data fetch timing signal generating section 7 and latching the data, an output delay section 11 outputting a signal delayed by a prescribed time with respect to the data fetch of the data storage section 9, a reference clock signal generating section 13 generating a reference clock signal synchronously with the signal outputted by the output delay section 11, and a reference clock synchronization section 17 outputting the data of the data storage section 9 synchronously with the reference clock signal generated by the reference clock signal generating section 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device, and more particularly to a data transmission device connected in cascade to perform digital data transmission.

[0002]

2. Description of the Related Art In digital data transmission, bit synchronization of data is necessary in order for another data transmission apparatus to correctly receive the data sent by one data transmission apparatus.

Except in special cases, data transmission equipment
The data output is performed in synchronization with a single reference clock signal generated by a reference clock signal generator individually provided in each data transmission device, instead of a reference clock signal generated by a common reference clock signal generator. If
A frequency deviation occurs due to the difference between the reference clock frequencies on the data transmitting side and the data receiving side. The occurrence of this frequency deviation is actually due to the tolerance of the reference clock signal generator of each data transmission device, as long as each data transmission device uses the reference clock signal of its own reference clock signal generator. ,Inevitable. In particular, when a relatively large amount of data is transmitted by cascaded data transmission devices, this frequency deviation causes a problem for each data transmission device.

For this reason, conventionally, each data transmission device has a PP
An L (Phase Lock Loop) circuit is provided so that the received data is fetched in synchronization with its own reference clock signal, or a FIFO (First in First Out) memory is provided for buffer storage of data, and each data transmission device is provided. Absorbing the frequency deviation between the two is performed.

[0005]

However, in the above-mentioned method, there is a drawback that the circuit structure is complicated and the scale becomes large, and the delay of data transmission becomes large. This is a particular problem in data transmission by a large number of cascaded data transmission devices that occur in the device.

The present invention has been made by paying attention to the above-mentioned problems in the conventional data transmission device, and does not increase the delay of data transmission without complicating and increasing the scale of the circuit configuration. It is an object of the present invention to provide a data transmission device that absorbs a frequency deviation and transmits data in multiple stages without increasing the size.

[0007]

SUMMARY OF THE INVENTION According to the present invention, the above-described object is to detect an edge of input data, and a data fetch timing signal based on the edge detected by the edge detector. A data fetching timing signal generating section, a data fetching section that fetches data in synchronization with the data fetching timing signal output from the data fetching timing signal generating section, and latches the data, and fetching data to the data storing section An output delay unit that outputs a signal delayed by a predetermined time, a reference clock signal generation unit that generates a reference clock signal synchronized with the signal output by the output delay unit,
And a reference clock synchronization unit that outputs the data of the data storage unit in synchronization with a reference clock signal generated by the reference clock signal generation unit.

[0008]

According to the above-mentioned structure, the input data is temporarily fetched in the data storage unit, and after a predetermined time has elapsed from the start of the fetching, this data is output in synchronization with the reference clock signal of the user. During this time, the frequency deviation between the data transmission device of the transmission source and the data transmission device of the data reception is absorbed.

[0009]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of a data transmission device according to the present invention. The data transmission device includes a noise removal circuit 1 that removes noise from input data, and a no-signal state detection circuit 3 that detects a no-signal state and clears an internal circuit of the device.
An edge detection circuit 5 for detecting an edge of a rectangular wave of the input data after noise removal, a data capture timing signal generation circuit 7 for outputting a data capture timing signal based on the edge of the rectangular wave of the input data, and an input data A data storage circuit 9 for temporarily storing the data, an output delay circuit 11 for outputting a signal delayed for a predetermined time with respect to the data storage circuit 9, and an output delay circuit 1.
1 and a reference clock generation circuit 13 for generating a reference clock signal synchronized with the signal output by 1 and an output data selection circuit 1 for selecting the output of the data stored in the data storage circuit 9.
5 and a reference clock synchronization circuit 17 that outputs data from the data storage circuit 9 in synchronization with the reference clock signal generated by the reference clock signal generation circuit 13.

Next, with reference to FIG. 2, the above-mentioned respective circuit examples will be described in detail.

The noise removing circuit 1 includes a 5-bit synchronous shift register 19 including five D-type flip-flops and two multiplexers, and a synchronous shift register 19
The input signals of the respective bits are input to the multiplexer based on the combination of the output signals of the selection signals SEL1 and SEL2.
And a rectangular wave data signal from another data transmission device, that is, input data DATA IN is sampled and input in synchronization with the system clock signal CLK32, and a predetermined bit of the synchronous shift register 19 is output. The input signal of is selectively inverted by the operation of the multiplexer to remove the noise component from the input data DATA IN, eliminate unnecessary edges of this, and output the data FILOUT after noise removal. There is. In this case, the frequency of the system clock signal CLK32 is that the input data DATA IN is based on the Manchester encoding method,
If the baud rate is a value equivalent to about 2 MHz, 32
It is set to about MHz.

If a more detailed description of the noise elimination circuit 1 is required, refer to the specification and drawings of Japanese Patent Application No. 3-286169 filed by the same applicant as the present applicant.

The no-signal state detection circuit 3 is composed of a 32-bit shift register 23 and a 32-input OR gate circuit 25, and synchronizes the noise-removed data FILOUT from the noise removal circuit 1 with the system clock signal CLK32. The shift register 23
The output of the OR gate circuit 25 becomes "L" when all of the outputs of the
Clear signal CLR to clear the circuit from the R gate circuit 25
A data fetch timing signal generation circuit 7, a data storage circuit 9, an output delay circuit 11, and a reference clock generation circuit 1.
3 to the data selection circuit 15 and the reference clock synchronization circuit 17 respectively.

The edge detection circuit 5 is composed of an EX-OR gate circuit 27 and an inverter 29. The data FILOUT after noise removal by the noise removal circuit 1 and the Q1 output of the shift register 23 of the no-signal state detection circuit 3 are output. Input and to detect the rising edge and falling edge of data FILOUT, and from this, only 2 system clocks "L"
The edge detection signal EDGE is output to the data fetch timing signal generation circuit 7.

Data acquisition timing signal generation circuit 7
Is composed of a 4-bit shift register 31, an AND gate circuit 33, and an inverter 35. After the clear signal CLR is changed from "L" to "H", two system clocks are output from the rising edge of the edge detection signal EDGE. The data fetch timing signal TCLK which rises every 8 system clocks with a delay is set to Q1 of the shift register 31.
The output is output as a clock signal to the data storage circuit 9.

The data storage circuit 9 is composed of a 4-bit shift register 37, four individual D-type flip-flops 39, 41, 43 and 45, and a multiplexer 47 having four inputs and one output, and takes in data. The timing signal TCLK is fetched as a clock signal of the shift register 37, the shift register 37 is operated by the data fetch timing signal TCLK, and the output Q0, Q1, Q2 of each bit of the shift register 37 is synchronized with the data fetch timing signal TCLK. , Q3 are starting up in order. D-type flip-flops 39, 41, 4
3 and 45 respectively take in the data FILOUT after noise elimination from the noise elimination circuit 1 in synchronization with the rising edges of the outputs Q0, Q1, Q2 and Q3 of the corresponding bits of the shift register 37, and latch it. It has become. The multiplexer 47 includes D-type flip-flops 39, 4
1, 43, 45 connected to each latch data MD0
, MD1, MD2, MD3 read is selectively set.

The output delay circuit 11 is composed of one D-type flip-flop 49, receives the output Q0 of the shift register 37 of the data storage circuit 9 as a clock signal, and an output signal for setting a delay time in synchronization therewith. Is output to the reference clock signal generation circuit 13. In this case, the output Q0 of the shift register 37 of the storage circuit 9 becomes "H" after counting one data fetch timing signal TCLK, so the D-type flip-flop 4
9 does not operate until the data fetch timing signal TCLK counts by one. This delay time, which is the delay time, is set to an optimum value for the data transmission system according to the frequency deviation and the data length transmitted in one frame.
This delay time may be determined according to the following equation. Delay time (number of system clocks) = maximum transmission data length x
Frequency deviation x number of sampling clocks for 1 data The reference clock generation circuit 13 is composed of a 4-bit shift register 51, an AND gate circuit 53, and two inverters 55 and 57, and outputs an output signal from the output delay circuit 11. Synchronous 32MHz system clock signal CL
The frequency of K32 is divided and a 4 MHz transmission clock signal CLK4 is generated as a reference clock signal of the own device.

The output data selection circuit 15 is composed of a quaternary binary counter 59, receives the transmission clock signal CLK4 from the reference clock generation circuit 13, and receives the D-type flip-flops 39, 41, 43 of the data storage circuit 9. Four
In order to select the output of the data stored in 5, the select signal MQ synchronized with the transmission clock signal CLK4 is output to the multiplexer 47.

The reference clock synchronization circuit 17 is composed of a D-type flip-flop 61 and has a transmission clock signal CLK4.
Is supplied via the inverter 57 to the multiplexer 4
7 outputs selected D-type flip-flops 39, 41,
The data MUXOUT read from 43 and 45 is output in synchronization with the transmission clock signal CLK4.

Next, the operation of the data transmitting apparatus according to the present invention having the above-mentioned configuration will be described with reference to the time chart of FIG.

The data transmitting apparatus samples and inputs the input data DATAIN from another data transmitting apparatus to the noise removing circuit 1 in synchronization with the system clock signal CLK32. The noise component of the input data DATAIN input to the noise removal circuit 1 is removed and the data FILOUT is output from the noise removal circuit 1. Due to the operation of the noise removing circuit 1, single-shot noise and noise having a frequency slower than the transfer rate are removed.

The data FILOUT is input to the no-signal state detection circuit 3, the edge detection circuit 5, and the data storage circuit 9, respectively.

At the rising edge of the data FILOUT, the clear command by the no-signal state detection circuit 3 is released, and each circuit transitions to the active state.

Further, the edge of the data FILOUT is detected by the edge detection circuit 5, and the edge detection signal EDGE which becomes "L" for only 2 system clocks from this is detected by the edge detection circuit 5.
The data is input to the data fetch timing signal generation circuit 7.

After that, when the edge detection signal EDGE becomes "H", the data fetch timing signal generation circuit 7 operates and the data fetch timing signal rises every 8 system clocks with a delay of 2 system clocks from the rising edge of the edge detection signal EDGE. TCLK is input from the Q1 output of the shift register 31 to the shift register 37 of the data storage circuit 9 as a clock signal.

When one data acquisition timing signal TCLK is given to the shift register 37, the shift register 3
The output Q0 of 7 becomes "H" and this output enables the data storage circuit 9, whereby the reference clock generation circuit 13 generates the transmission clock signal CLK4 and this transmission clock signal CLK4 is output.

The outputs Q0, Q of the shift register 37
1, Q2, Q3 sequentially rise in synchronization with the data fetch timing signal TCLK, and at this rising timing, each of the D-type flip-flops 39, 41, 43, 45 sequentially and cyclically receives data from the noise elimination circuit 1. FILO
Take in UT and latch it.

On the other hand, the output data selection circuit 15 operates in response to the rising of the transmission clock signal CLK4, and the select signal MQ is input to the multiplexer 47 in synchronization with the transmission clock signal CLK4. As a result, each D of the data storage circuit 9
The data MD0, MD1, MD2, MD3 stored in the type flip-flops 39, 41, 43, 45 are sequentially taken out and input to the reference clock synchronization circuit 17 as data MUXOUT.

This data MUXOUT is output data DATA according to the frequency of the transmission clock signal CLK4 by the reference clock synchronization circuit 17 in synchronization with the fall of the transmission clock signal CLK4.
It is output as OUT. In this case, there is a delay time T between the data writing to the data storage circuit 9 and the data output from the reference clock synchronization circuit 17, and this delay time T depends on the frequency deviation and the data length transmitted by one frame. Is set to the optimum value for the data transmission system.

In the above-described embodiment, in the no-signal state, each circuit is cleared by the clear signal CLR of the no-signal state detection circuit 3, and each circuit becomes the static state in the data waiting state. This stabilizes the circuit operation.

[0032]

As can be understood from the above description, according to the data transmission device of the present invention, the input data is temporarily stored in the data storage unit, and after a predetermined time has elapsed from the start of the storage, The data is output in synchronization with its own reference clock signal, and during this time, the frequency deviation between the source data transmission device and the data reception data transmission device is absorbed, and the data is multistaged while eliminating the effect of the frequency deviation. Can be transmitted to.

This data transmission device is composed of a D-type flip-flop, a multiplexer, a shift register, and a logic gate, and does not require a PLL circuit, a FIFO memory, etc., so that the circuit structure does not become complicated and large-scaled. , This is especially true for the ASI
This is effective when realized by C.

If the maximum transmission data amount and the frequency deviation of the data transmission system are determined, the data transmission delay time for absorbing the frequency deviation can be set to the minimum required value in the system, and the processing by the MPU, etc. The data transmission can be processed at a higher speed than the above.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data transmission device according to the present invention.

FIG. 2 is a block diagram showing in detail each circuit example of the data transmission device according to the present invention.

FIG. 3 is a time chart of each signal showing the operation of the data transmission device according to the present invention.

[Explanation of symbols]

 1 Noise Removal Circuit 3 No-Signal State Detection Circuit 5 Edge Detection Circuit 7 Data Acquisition Timing Signal Generation Circuit 9 Data Storage Circuit 11 Output Delay Circuit 13 Reference Clock Generation Circuit 15 Output Data Selection Circuit 17 Reference Clock Synchronization Circuit

Claims (1)

[Claims] 1. An edge detector for detecting an edge of a rectangular wave of input data, and a data capture timing signal for outputting a data capture timing signal based on the edge of the rectangular wave of the input data detected by the edge detector. A generator, a data storage unit that captures input data in synchronization with a data capture timing signal output by the data capture timing signal generator, and latches the data, and a predetermined time for capturing the input data to the data storage unit. An output delay unit that outputs a delayed signal, a reference clock signal generation unit that generates a reference clock signal that is synchronized with the signal that the output delay unit outputs, and a reference clock signal that is generated by the reference clock signal generation unit. And a reference clock synchronization unit that outputs the input data of the data storage unit. A data transmission device characterized in that