JPH05129909A - Variable delay circuit with very small delay - Google Patents

Abstract

PURPOSE:To provide a variable delay quantity with high resolution. CONSTITUTION:One input of 1st and 2nd exclusive OR (EXOR) gates 17, 18 is connected to a delay input terminal 15, and both outputs are connected together through a capacitor 21. Moreover, the other input terminal of the 1st EXOR gate 17 connects to ground, the other input terminal of the 2nd EXOR gate 18 is connected to a selection signal input terminal 19 and an output of the 1st EXOR gate 17 is connected to a delay output terminal 16 through a logic buffer 22. When a level of a selection signal is '0', potentials across the capacitor 21 are always at an equi-potential and no current flows to the capacitor 21, and when the level of the selection signal is '1', a current flows to the capacitor 21 and the current is delayed by a prescribed quantity with respect to an output of the output terminal 16 when the level of the selection signal is '0'.

Description

Detailed Description of the Invention

[0001]

This invention has a delay resolution of, for example, 1
The present invention relates to a minute variable delay circuit that enables minute delay on the order of 0 pS.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional minute variable delay circuit.
The delay stages 11 ₁ , 11 ₂ , and 11 ₃ are cascade-connected, and the delay stage 11 ₁ has a path of the buffer 12 with a delay amount A and a delay amount of B.
(B = 2A) or the passage of the buffer 13 is selected by the multiplexer 14 is the selected channel to signal passes, the delay stage 11 ₂ of the delay B and passage without delay One of the paths of the buffer 13 is selected by the multiplexer 14, and the delay stage 11 ₃ is selected by the multiplexer 14 of either the path with no delay amount or the path in which two buffers 13 with the delay amount B are connected in series. It By controlling the selection signal applied to the selection input side S of each multiplexer 14, the delay input terminal 15 and the delay output terminal 16 are controlled.
The path through which the signal between and is passed is switched, and a delay of the delay amount corresponding to the path is generated in the output signal of the delay output terminal 16. Depending on the route selection, the difference in delay amount is (B−A), 2 (B
-A), 3 (BA), 4 (BA) ... That is, a variable delay circuit having a resolution of (BA) can be obtained.

[0003]

The delay amounts A and B are obtained from the propagation delay amounts T _pd in the buffers 12 and 13, respectively. If the buffers 12 and 13 are to be realized by a gate array or the like, it is necessary to consider the delay amount due to the wiring because the arrangement of the gates cannot be freely selected.
It becomes difficult to design so as to satisfy the relationship of B, and the minute resolution is poor. That is, it is difficult to reduce (B-A), and the difference (B-A) in the amount of adjacent delay varies widely.

[0004]

According to the present invention, first and second exclusive OR gates are used.
One input side of the second exclusive OR gate is connected to a common delay input terminal, the other input side of the first exclusive OR gate is grounded, and its output side and the second exclusive OR gate are connected. Of the second exclusive OR gate, the other input side of which is connected to the selection signal input terminal and which outputs a logic level to the output side of the first exclusive OR gate. Is connected to the output side of the buffer and the output side of the buffer is connected to the delay output terminal.

[0005]

1A shows an embodiment of the present invention. First and second exclusive OR gates (hereinafter referred to as EXOR gates)
17, 18 are provided, and the first and second EXOR gates 1 are provided.
One input side of each of 7 and 18 is commonly connected to the delay input terminal 15, the other input side of the first EXOR gate 17 is grounded, and the other input side of the second EXOR gate 18 is connected to the selection signal input terminal 19. To be done. First EXOR gate 1
A capacitor 21 is connected between the output side of 7 and the output side of the second EXOR gate 18, and the output side of the first EXOR gate 17 is connected to the delay output terminal 16 through a buffer 22 that outputs a logic level. The buffer 22 has a threshold value and outputs one or the other of binary logic levels according to whether the input is above or below the threshold value.

In this configuration, when the selection signal at the selection signal input terminal 19 is "0", the second EXOR gate 18 becomes a non-inverting gate, and the circuit shown in FIG. 1A becomes the circuit shown in FIG. 1B. When the signals of the waveforms shown are input, the signals of the same waveform appear simultaneously on the output sides of the first and second EXOR gates 17 and 18, respectively, as shown by b and c in FIG. 1C. Therefore, the potentials on both sides of the capacitor 21 are always the same, no current flows through the capacitor 21, and the impedance of the capacitor 21 can be regarded as infinite. Therefore, it can be considered that there is no second EXOR gate 18, and the equivalent circuit of FIG. 1A can be written as shown in FIG. 1D.

On the other hand, when the selection signal at the selection signal input terminal 19 is "1", the second EXOR gate 18 acts as an inverting gate, and the circuit of FIG. 1A can be written as shown in FIG. 2A. When the signal having the waveform shown in FIG. 2Ba is input to the input terminal 15, the output of the first EXOR gate 17 assuming that the second EXOR gate 18 is not present has the same polarity as the input waveform as shown in FIG. 2Bb. As shown in FIG. 2Bc, the output of the 2EXOR gate 18 has a waveform having a polarity opposite to that of FIG. 2Bb. The first and second EXOR gates 17 and 18 are connected to the voltage sources 23 and 24 and the output resistor (gate on-resistance) 2 respectively.
5 and 26, the circuit of FIG. 2A becomes the equivalent circuit shown in FIG. 2C. The voltage sources 23 and 24 output the following reverse-phase voltages.

V ₁ (t) = v ₀ f (t), v ₂ (t) = v ₀ (1-f (t)) f (t) is 0 when t ≦ 0, and 1 when t ← ∞. ≤f (t) ≤1 Connection point 2 of the first EXOR gate 17 and the capacitor 21
The voltage V _out (s) of 7 is given by the following equation. V _out (s) = V ₀ · F (s) − [V ₀ F (s) − {V ₀ (1 / s−F (s)) −V ₀ / s} · R] / (2R + 1 / sC) = V ₀ · F (s) (1 / 2CR) / (s + 1 / (2CR)) R is the resistance value of each of the output resistors 25 and 26, and C is the capacitance of the capacitor 21 f (t) = u (t) ( Unit step pulse)

[0009]

[Equation 1] Becomes v time _{t out} (t) is the V _0/2 is 2CR l
It will be og2. The waveform of the output signal of this connection point 27 is shown in FIG. 2B.
The waveform has a blunt rising, as shown in d. Therefore, when the signal of the waveform shown in FIG. 2Da is input to the delay input terminal 15 of FIG. 1A, when the selection signal is “0”, the signal of the connection point 27 has the same waveform as the input signal as shown by the solid line 28 of FIG. 2Db. However, when the selection signal is "1", the signal at the connection point 27 has rising and falling edges as shown by a dotted line 29 in FIG. 2Db. Threshold level V of buffer 22
_{When t} is at the center between the low level and the high level as shown in FIG. 2Db, the output of the buffer 22 becomes the solid line output 31 when the selection signal is “0” as shown in FIG. In the case of the signal “1”, it is delayed by Δt = 2CR log2 like the dotted line output 32.

It is easy to make the entire circuit shown in FIG. 1A into an IC and reduce the influence of the wiring at that time, and it is possible to easily make a target delay difference Δt. It is easy to set the delay amount difference Δt to be, for example, about 20 pS to 40 pS. By connecting a plurality of the variable delay circuits shown in FIG. 1A in cascade and changing the combination of the selection signals for each variable delay circuit to take various paths for the input signal, the delay time differences Δt, 2Δt, 3Δt, Four
It is possible to selectively set any of a plurality of delay amounts with Δt.

As shown in FIG. 3A, a plurality of second EXOR1s are provided.
8 ₁ , 18 ₂ , 18 ₃ ... Are provided, one input side of each of which is commonly connected to the delay input terminal 15, and the other input side of each selection signal input terminal 19 ₁ , 19 ₂ , 19 respectively. ₃
... and connect each output side to a separate capacitor 21
_It may be connected to the output side of the first EXOR 17 through ₁ , 21 ₂ , 21 ₃ ... Capacitors 21 ₁ , 21 ₂ , 21
₃ has the same value C, when the n selection signals in the selection signal input terminals 19 ₁ , 19 ₂ , 19 ₃ are “1”, the circuit of FIG. Similar to Figure 3
This can be represented by the equivalent circuit shown in B. At this time, the voltage V _out (s) at the connection point 27 is given by the following equation.

V _out (s) = V ₀ · F (s) − [V ₀ F (s) − {V ₀ (1 / s−F (s)) −V ₀ / s} · R] / (R + R / N + 1 / (nsC)) V ₁ (s) = V ₀ · F (s), V ₂ (s) = V ₀ (1 / SF)
(s)), V ₂ ( ₀ ) = V ₀ F (s) = 1 / S (unit step pulse)

[0013]

[Equation 2] Becomes The time when it becomes V _0/2 is t =-(n + 1) CR l
It becomes og (n + 1) / 4n, and the delay amount can be monotonously changed according to the value of n. If the number of the second EXOR gates 18 is four in FIG. 3A, the conventional circuit shown in FIG. 4 has the same function as two delay stages. In the above, the first and second E
The XOR gates 17 and 18 and the buffer 22 are, for example, CMOs.
It is composed of S.

[0014]

As described above, according to the present invention, the first
At least one second EXOR gate is connected in parallel to the output side of the EXOR gate via a capacitor,
The selection signal is applied to the other input side of the second EXOR gate,
Depending on whether the selection signal is "0" or "1",
The delay amount of the input signal can be changed. It is possible to easily make a difference in the change in the delay amount of, for example, about 20 to 40 pS, and to obtain a minute and high resolution variable delay circuit.

[Brief description of drawings]

FIG. 1A is a logic circuit diagram showing an embodiment of the present invention, B,
D is an equivalent circuit diagram when the selection signal is "0", and C is an operation explanatory diagram thereof.

2A and 2B are equivalent circuit diagrams of FIG. 1A when a selection signal is "1", B is an operation waveform diagram thereof, and D is an operation waveform diagram of FIG. 1A.

FIG. 3A is a logic circuit diagram showing another embodiment of the present invention,
B is an equivalent circuit diagram thereof.

FIG. 4 is a block diagram showing a conventional minute variable delay circuit.

Claims (1)

[Claims] 1. A first exclusive OR gate in which one input side is grounded and the other input side is connected to a delay input terminal, and one input side is connected to a selection signal input terminal, and the other input side is connected. A second exclusive OR gate connected to the delay input terminal, and a capacitor connected between the output side of the first exclusive OR gate and the output side of the second exclusive OR gate. A minute variable delay circuit comprising: a capacitor, the input side of which is connected to a connection point of the output side of the first exclusive OR gate, the output side of which is connected to a delay output terminal, and a buffer which outputs a logic level.