JPH05129649A - Solid-state image sensing element - Google Patents
Solid-state image sensing elementInfo
- Publication number
- JPH05129649A JPH05129649A JP3290157A JP29015791A JPH05129649A JP H05129649 A JPH05129649 A JP H05129649A JP 3290157 A JP3290157 A JP 3290157A JP 29015791 A JP29015791 A JP 29015791A JP H05129649 A JPH05129649 A JP H05129649A
- Authority
- JP
- Japan
- Prior art keywords
- guard ring
- pixel electrodes
- layer
- electrode
- blocking layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000000903 blocking effect Effects 0.000 claims description 23
- 238000003384 imaging method Methods 0.000 claims description 4
- 239000007787 solid Substances 0.000 claims description 2
- 238000002347 injection Methods 0.000 abstract description 15
- 239000007924 injection Substances 0.000 abstract description 15
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 239000004642 Polyimide Substances 0.000 abstract description 3
- 230000003321 amplification Effects 0.000 abstract description 3
- 239000011159 matrix material Substances 0.000 abstract description 3
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 239000011810 insulating material Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 43
- 239000002184 metal Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910017875 a-SiN Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14665—Imagers using a photoconductor layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は増幅型の固体撮像素子に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification type solid state image pickup device.
【０００２】[0002]
【従来の技術】増幅型の固体撮像素子として、積層型Ａ
ＭＩ（Ａｍｐｌｉｆｉｅｄ ＭＯＳＩｍａｇｅｒ）が知
られ、その一例がテレビジョン学会技術報告Ｖｏｌ．１
４，Ｎｏ．７４，ＰＰ．７〜１１（１９９０．１２．１
８）や、昭和６３年電子情報通信学会秋季全国大会報告
集に開示されている。2. Description of the Related Art As an amplification type solid-state image pickup device, a laminated type A
MI (Amplified MOS Imager) is known, and an example thereof is the Technical Report of the Institute of Television Engineers of Japan, Vol. 1
4, No. 74, PP. 7-11 (1990.12.1
8) and the 1988 IEICE Autumn National Convention report collection.
【０００３】図３は、その構造を模式的に示し、同図
（ａ）は断面図、同図（ｂ）は上面図である。図示の通
り、増幅回路、走査回路などが形成された基板１上に
は、マトリクスに複数の画素電極２が配設され、この上
面には、電子注入阻止層３、アバランシェ増倍作用を有
するａ−Ｓｅの受光層４、ホール注入阻止層５およびＩ
ＴＯなどの透明電極６が設けられている。このような固
体撮像素子おいて、光入力があると受光層４でキャリア
が生成され、アバランシェ増倍作用が生じる。この増倍
キャリアは画素電極２に注入され、検出されて走査回路
によって転送されていく。FIG. 3 schematically shows the structure. FIG. 3A is a sectional view and FIG. 3B is a top view. As shown in the figure, a plurality of pixel electrodes 2 are arranged in a matrix on a substrate 1 on which an amplifier circuit, a scanning circuit, etc. are formed, and an electron injection blocking layer 3 and an avalanche multiplication function a are provided on the upper surface of the pixel electrode 2. -Se light receiving layer 4, hole injection blocking layer 5 and I
A transparent electrode 6 such as TO is provided. In such a solid-state imaging device, when light is input, carriers are generated in the light-receiving layer 4 and an avalanche multiplication action occurs. This multiplication carrier is injected into the pixel electrode 2, detected, and transferred by the scanning circuit.
【０００４】[0004]
【発明が解決しようとする課題】ところで、受光層４は
一般的には２μｍ程度の厚さを必要とし、したがってア
バランシェ増倍作用のためには画素電極２と透明電極６
の間に１００〜２００Ｖ以上の印加電圧を必要とする。
このため、基板１と受光層４の間で絶縁破壊が生じない
ようにするため、基板１表面の厳しい平坦化が必要にな
る。この平坦化の程度は、一般には２５０オングストロ
ーム程度であり、前述の先行技術では基板１表面の凹部
にＯＣＤを埋め込む技術が提案されている。By the way, the light-receiving layer 4 generally needs to have a thickness of about 2 μm, and therefore the pixel electrode 2 and the transparent electrode 6 are required for the avalanche multiplication function.
An applied voltage of 100 to 200 V or more is required between the two.
Therefore, in order to prevent dielectric breakdown between the substrate 1 and the light-receiving layer 4, the surface of the substrate 1 needs to be severely flattened. The degree of flattening is generally about 250 angstroms, and the above-mentioned prior art proposes a technique of burying an OCD in a recess on the surface of the substrate 1.
【０００５】しかし、上記のような平坦化を実現できた
としても、画素電極２の間の段差は解決されない。この
ため、電子注入阻止層３の膜厚が画素電極２のエッジで
薄くなりやすく、図３（ａ）で矢印で示す部分の耐圧低
下は避けられなかった。本発明は、このような従来技術
の欠点を解決した固体撮像素子を提供することを目的と
する。However, even if the above flattening can be realized, the step difference between the pixel electrodes 2 cannot be solved. For this reason, the film thickness of the electron injection blocking layer 3 is likely to be thin at the edge of the pixel electrode 2, and a decrease in breakdown voltage at the portion shown by the arrow in FIG. 3A cannot be avoided. It is an object of the present invention to provide a solid-state image sensor that solves the above-mentioned drawbacks of the conventional technology.
【０００６】[0006]
【課題を解決するための手段】本発明は、上面に複数の
画素電極が配設された信号読み出し用の基板上に、第１
導電型キャリア阻止層、受光層、第２導電型キャリア阻
止層および透光性の導電膜が順次に積層された固体撮像
素子において、基板上には、複数の画素電極間に埋め込
まれて当該画素電極のエッジを覆う絶縁性のガードリン
グが形成され、第１導電型キャリア阻止層は複数の画素
電極およびガードリングを覆うように形成されているこ
とを特徴とする。ここで、受光層はアバランシェ増倍作
用を有し、複数の画素電極と導電膜には受光層でアバラ
ンシェ増倍作用を生じ得るバイアスが印加される。According to the present invention, a first substrate is provided on a signal reading substrate having a plurality of pixel electrodes arranged on an upper surface thereof.
In a solid-state imaging device in which a conductive type carrier blocking layer, a light receiving layer, a second conductive type carrier blocking layer, and a translucent conductive film are sequentially stacked, a pixel is embedded on a substrate between a plurality of pixel electrodes. An insulating guard ring that covers the edge of the electrode is formed, and the first conductivity type carrier blocking layer is formed so as to cover the plurality of pixel electrodes and the guard ring. Here, the light receiving layer has an avalanche multiplication function, and a bias that can cause the avalanche multiplication function in the light receiving layer is applied to the plurality of pixel electrodes and the conductive film.
【０００７】[0007]
【作用】本発明の構成によれば、画素電極２のエッジ部
には絶縁性のガードリングが設けられるので、その上の
キャリア阻止層がこの部分で薄層化せず、また薄層化し
ても下側にガードリングが介在しているので、絶縁耐圧
の大幅な向上が可能になる。According to the structure of the present invention, since the insulating guard ring is provided at the edge portion of the pixel electrode 2, the carrier blocking layer thereabove does not become thin at this portion, and is made thin. Also, since the guard ring is provided on the lower side, the withstand voltage can be significantly improved.
【０００８】[0008]
【実施例】以下、添付図面により本発明の実施例を説明
する。Embodiments of the present invention will be described below with reference to the accompanying drawings.
【０００９】図１は本発明に係る固体撮像素子の基本構
造を示し、同図（ａ）は断面図、同図（ｂ）は上面図で
ある。ＭＯＳ形、ＣＣＤ形などのイメージャー基板１上
には複数の画素電極２がマトリクス状に配設され、この
画素電極２の間隙部分には、画素電極２のエッジ部を覆
うガードリング７が設けられている。そして、全面に電
子注入阻止層３、受光層４、ホール注入阻止層５および
透明電極６が順次に形成されている。ここで、ガードリ
ング７は例えばポリイミドなどの絶縁材料で構成され、
画素電極２のコーナーにおけるブレークダウンを防止し
ている。このため、アバランシェ増倍作用を生じ得る程
度の高バイアスを印加したときにも、絶縁破壊が生じる
ことはない。FIG. 1 shows a basic structure of a solid-state image pickup device according to the present invention. FIG. 1 (a) is a sectional view and FIG. 1 (b) is a top view. A plurality of pixel electrodes 2 are arranged in a matrix on an imager substrate 1 of MOS type, CCD type or the like, and a guard ring 7 for covering an edge portion of the pixel electrode 2 is provided in a gap between the pixel electrodes 2. Has been. Then, an electron injection blocking layer 3, a light receiving layer 4, a hole injection blocking layer 5, and a transparent electrode 6 are sequentially formed on the entire surface. Here, the guard ring 7 is made of an insulating material such as polyimide,
Breakdown at the corner of the pixel electrode 2 is prevented. Therefore, dielectric breakdown does not occur even when a high bias to the extent that an avalanche multiplication effect is generated is applied.
【００１０】図２は実施例に係る固体撮像素子の詳細な
構成を示す断面図である。ｐ型シリコン基板１１にはｎ
+ 型層１２が形成され、熱酸化によるゲート絶縁膜１３
を介してｐ型シリコン基板１１上にポリシリコンのゲー
ト電極１４が形成され、更にｎ+ 型層１２にオーミック
接触するＡｌなどの第１層金属電極１５が形成されるこ
とで、ＭＯＳ構造のスイッチが構成されている。なお、
ゲート電極１４はポリシリコンの熱酸化膜１６でカバー
されている。さらに、これらの全面を覆うように、ポリ
イミド等からなる層間絶縁膜１７が形成されている。FIG. 2 is a sectional view showing the detailed structure of the solid-state image pickup device according to the embodiment. The p-type silicon substrate 11 has n
The + type layer 12 is formed, and the gate insulating film 13 by thermal oxidation is formed.
A gate electrode 14 made of polysilicon is formed on the p-type silicon substrate 11 via the via, and a first-layer metal electrode 15 such as Al that is in ohmic contact with the n + -type layer 12 is formed, thereby forming a switch having a MOS structure. Is configured. In addition,
The gate electrode 14 is covered with a thermal oxide film 16 of polysilicon. Further, an interlayer insulating film 17 made of polyimide or the like is formed so as to cover these entire surfaces.
【００１１】層間絶縁膜１７の上面には、複数の画素ご
とに第２層金属電極１８が形成されるが、これらは、層
間絶縁膜１７に形成されたスルーホールを介して第１層
金属電極１５に接続されている。さらに、全面にＯＣＤ
あるいはＰＳＧなどからなる絶縁膜１９が形成され、Ｍ
ＯＳ形イメージャー基板１０が構成されている。A second layer metal electrode 18 is formed on the upper surface of the interlayer insulating film 17 for each of a plurality of pixels, and these are formed through the through holes formed in the interlayer insulating film 17 to form the first layer metal electrode. It is connected to 15. Furthermore, OCD on the whole surface
Alternatively, an insulating film 19 made of PSG or the like is formed, and M
An OS type imager substrate 10 is configured.
【００１２】画素電極２は絶縁膜１９上に形成され、ス
ルーホールを介して対応する第２層金属電極１８に接続
されている。そして、画素電極２の各々の間隙部分には
ガードリング７が設けられ、これらの上面には、電子注
入阻止層３、受光層４、ホール注入阻止層５および透明
電極６が順次に堆積されている。なお、電子注入阻止層
３としては、受光層４がａ−ＳｅのときにＡｓ2 Ｓｅ3
が用いられ、ホール注入阻止層５としては、受光層４が
ａ−ＳｅのときにＣｅＯが用いられる。但し、受光層４
がａ−Ｓｉのときには、下側のキャリア阻止層３はホー
ル注入阻止層となってａ−ＳｉＣ：Ｈが用いられ、上側
のキャリア阻止層５は電子注入阻止層はａ−ＳｉＮ又は
ａ−ＳｉＣ：Ｈが用いられる。The pixel electrode 2 is formed on the insulating film 19 and is connected to the corresponding second layer metal electrode 18 via a through hole. A guard ring 7 is provided in each gap between the pixel electrodes 2, and an electron injection blocking layer 3, a light receiving layer 4, a hole injection blocking layer 5 and a transparent electrode 6 are sequentially deposited on the upper surfaces of the guard rings 7. There is. The electron injection blocking layer 3 is As 2 Se 3 when the light receiving layer 4 is a-Se.
As the hole injection blocking layer 5, CeO is used when the light receiving layer 4 is a-Se. However, the light receiving layer 4
Is a-Si, the lower carrier blocking layer 3 serves as a hole injection blocking layer and a-SiC: H is used, and the upper carrier blocking layer 5 has an electron injection blocking layer of a-SiN or a-SiC. : H is used.
【００１３】この実施例によれば、画素電極２のエッジ
部を完全に保護できるのでブレークダウンを効果的に防
止できる。また、製造プロセスが容易であって、画素電
極２の膜厚に対する制約も少なくできる。According to this embodiment, since the edge portion of the pixel electrode 2 can be completely protected, breakdown can be effectively prevented. Further, the manufacturing process is easy, and restrictions on the film thickness of the pixel electrode 2 can be reduced.
【００１４】[0014]
【発明の効果】以上の通り、本発明の固体撮像素子によ
れば、画素電極２のエッジ部は絶縁性のガードリングが
設けられるので、その上のキャリア阻止層がこの部分で
薄層化せず、また薄層化しても下側にガードリングが介
在しているので、絶縁耐圧の大幅な向上が可能になる。
このため、アバランシェ増倍型の固体撮像素子におい
て、平坦化に格別の配慮をすることなく、効果的なブレ
ークダウン防止を図ることができる。As described above, according to the solid-state image pickup device of the present invention, since the insulating guard ring is provided at the edge portion of the pixel electrode 2, the carrier blocking layer on it is thinned at this portion. In addition, since the guard ring is provided on the lower side even if the layer is thinned, the withstand voltage can be significantly improved.
Therefore, in the avalanche multiplication type solid-state imaging device, effective breakdown prevention can be achieved without special consideration for flattening.
【図１】本発明に係る固体撮像素子の基本構造を示す図
である。FIG. 1 is a diagram showing a basic structure of a solid-state image sensor according to the present invention.
【図２】実施例に係る固体撮像素子の詳細な断面図であ
る。FIG. 2 is a detailed cross-sectional view of a solid-state image sensor according to an example.
【図３】従来の固体撮像素子を示す図である。FIG. 3 is a diagram showing a conventional solid-state image sensor.
１…基板、１０…ＭＯＳ形イメージャー基板、１１…ｐ
型シリコン基板、１２…ｎ+ 型層、１３…ゲート絶縁
膜、１４…ゲート電極、１５…第１層金属電極、１６…
絶縁膜、１７…層間絶縁膜、１８…第２層金属電極、１
９…絶縁膜、２…画素電極、３…電子注入阻止層、４…
受光層、５…ホール注入阻止層、６…透明電極、７…ガ
ードリング1 ... substrate, 10 ... MOS type imager substrate, 11 ... p
Type silicon substrate, 12 ... N + type layer, 13 ... Gate insulating film, 14 ... Gate electrode, 15 ... First layer metal electrode, 16 ...
Insulating film, 17 ... Interlayer insulating film, 18 ... Second layer metal electrode, 1
9 ... Insulating film, 2 ... Pixel electrode, 3 ... Electron injection blocking layer, 4 ...
Light-receiving layer, 5 ... Hole injection blocking layer, 6 ... Transparent electrode, 7 ... Guard ring
Claims (2)
読み出し用の基板上に、第１導電型キャリア阻止層、受
光層、第２導電型キャリア阻止層および透光性の導電膜
が順次に積層された固体撮像素子において、 前記基板上には、前記複数の画素電極間に埋め込まれて
当該画素電極のエッジを覆う絶縁性のガードリングが形
成され、前記第１導電型キャリア阻止層は前記複数の画
素電極および前記ガードリングを覆うように形成されて
いることを特徴とする固体撮像素子。1. A first conductivity type carrier blocking layer, a light receiving layer, a second conductivity type carrier blocking layer and a translucent conductive film are provided on a signal reading substrate having a plurality of pixel electrodes disposed on an upper surface thereof. In the sequentially stacked solid-state imaging device, an insulating guard ring embedded between the plurality of pixel electrodes and covering edges of the pixel electrodes is formed on the substrate, and the first conductivity type carrier blocking layer is formed. Is formed so as to cover the plurality of pixel electrodes and the guard ring.
し、前記複数の画素電極と前記導電膜には前記受光層で
アバランシェ増倍作用を生じ得るバイアスが印加される
請求項１記載の固体撮像素子。2. The solid according to claim 1, wherein the light receiving layer has an avalanche multiplication function, and a bias that can cause an avalanche multiplication function in the light receiving layer is applied to the plurality of pixel electrodes and the conductive film. Image sensor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3290157A JPH05129649A (en) | 1991-11-06 | 1991-11-06 | Solid-state image sensing element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3290157A JPH05129649A (en) | 1991-11-06 | 1991-11-06 | Solid-state image sensing element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05129649A true JPH05129649A (en) | 1993-05-25 |
Family
ID=17752508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3290157A Pending JPH05129649A (en) | 1991-11-06 | 1991-11-06 | Solid-state image sensing element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05129649A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6307239B1 (en) * | 2000-04-19 | 2001-10-23 | United Microelectronics Corp. | CMOS sense structure having silicon dioxide outer ring around sense region |
| JP2005019543A (en) * | 2003-06-24 | 2005-01-20 | Shimadzu Corp | Two-dimensional semiconductor detector and two-dimensional imaging apparatus |
| JP2007142283A (en) * | 2005-11-21 | 2007-06-07 | Fujifilm Corp | Radiation image detector, and method for manufacturing radiation image detector |
| JP2007273555A (en) * | 2006-03-30 | 2007-10-18 | Fujifilm Corp | Photoelectric conversion device and solid state imaging device |
| JP2011159781A (en) * | 2010-02-01 | 2011-08-18 | Epson Imaging Devices Corp | Photoelectric conversion device, x-ray imaging device, and method of manufacturing photoelectric conversion device |
| JP2016033972A (en) * | 2014-07-31 | 2016-03-10 | キヤノン株式会社 | Imaging apparatus and imaging system |
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|---|---|---|---|---|
| JPS61268077A (en) * | 1985-05-23 | 1986-11-27 | Mitsubishi Electric Corp | Photoelectric conversion element |
| JPH0366178A (en) * | 1989-08-04 | 1991-03-20 | Canon Inc | Optoelectric transducer |
-
1991
- 1991-11-06 JP JP3290157A patent/JPH05129649A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61268077A (en) * | 1985-05-23 | 1986-11-27 | Mitsubishi Electric Corp | Photoelectric conversion element |
| JPH0366178A (en) * | 1989-08-04 | 1991-03-20 | Canon Inc | Optoelectric transducer |
Cited By (8)
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| JP2005019543A (en) * | 2003-06-24 | 2005-01-20 | Shimadzu Corp | Two-dimensional semiconductor detector and two-dimensional imaging apparatus |
| JP2007142283A (en) * | 2005-11-21 | 2007-06-07 | Fujifilm Corp | Radiation image detector, and method for manufacturing radiation image detector |
| JP4762692B2 (en) * | 2005-11-21 | 2011-08-31 | 富士フイルム株式会社 | Radiation image detector and method for manufacturing radiation image detector |
| JP2007273555A (en) * | 2006-03-30 | 2007-10-18 | Fujifilm Corp | Photoelectric conversion device and solid state imaging device |
| JP2011159781A (en) * | 2010-02-01 | 2011-08-18 | Epson Imaging Devices Corp | Photoelectric conversion device, x-ray imaging device, and method of manufacturing photoelectric conversion device |
| JP2016033972A (en) * | 2014-07-31 | 2016-03-10 | キヤノン株式会社 | Imaging apparatus and imaging system |
| US9991305B2 (en) | 2014-07-31 | 2018-06-05 | Canon Kabushiki Kaisha | Stacked type solid state imaging apparatus and imaging system |
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