JPH0366178A - Optoelectric transducer - Google Patents

Optoelectric transducer

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Publication number
JPH0366178A
JPH0366178A JP1201452A JP20145289A JPH0366178A JP H0366178 A JPH0366178 A JP H0366178A JP 1201452 A JP1201452 A JP 1201452A JP 20145289 A JP20145289 A JP 20145289A JP H0366178 A JPH0366178 A JP H0366178A
Authority
JP
Japan
Prior art keywords
amorphous
layer
photoelectric conversion
conversion element
nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1201452A
Other languages
Japanese (ja)
Inventor
Masashi Yoshimi
雅士 吉見
Yasutaka Domoto
道本 康隆
Toshihiko Toyama
利彦 外山
Hiroaki Okamoto
博明 岡本
Yoshihiro Hamakawa
圭弘 浜川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP1201452A priority Critical patent/JPH0366178A/en
Publication of JPH0366178A publication Critical patent/JPH0366178A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、光を電気信号に変換する光電変換素子に係り
、特に非晶質半導体において電荷増倍作用を用いて高感
度を実現する光電変換素子に関する。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a photoelectric conversion element that converts light into an electrical signal, and in particular to a photoelectric conversion element that achieves high sensitivity by using charge multiplication in an amorphous semiconductor. It relates to a conversion element.

[従来の技術] 光を情報信号の媒体とする映像情報システム、光通信、
その他の産業、民生分野において、光信号を電気信号に
変換する光電変換素子は、最も重要で基本的な構成要素
の一つであり、既に数多くのものが実用化されている。
[Prior art] Video information systems, optical communications, and optical communications that use light as a medium for information signals.
In other industrial and consumer fields, photoelectric conversion elements that convert optical signals into electrical signals are one of the most important and fundamental components, and many of them have already been put into practical use.

一般に、光電変換素子の特性としては、高感度であるこ
とが要求される。
In general, photoelectric conversion elements are required to have high sensitivity.

このうち、光生成されたキャリアを衝突電離により増幅
するアバランシェフォトダイオード(以下APDと称す
る)は、利得が高く、かつ応答速度が速いので、こうし
た要求を満たす光電変換素子の有力な候補である。この
APDは、現在では、特に光通信システムにおける受光
素子として、既に多数実用化されており、他の分野、例
えば、−次元イメージセンサ、受光素子を積層した二次
元イメージセンサ、光導電型撮像管、電子写真感光体な
どへの応用も強く望まれている。
Among these, avalanche photodiodes (hereinafter referred to as APDs), which amplify photogenerated carriers by impact ionization, have high gain and fast response speed, and are therefore promising candidates for photoelectric conversion elements that meet these requirements. Many APDs have already been put into practical use, especially as photodetectors in optical communication systems, and are also used in other fields, such as -dimensional image sensors, two-dimensional image sensors with stacked photodetectors, and photoconductive image pickup tubes. Application to electrophotographic photoreceptors, etc., is also strongly desired.

こうしたAPDを作成するために用いられている材料は
、結晶半導体、特に第rv族のSL、第1II −V族
のGaAs5InPを主体とした材料がほとんどである
。結晶半導体材料を用いてAPDを作成するには、一般
に、高温、超高真空の製造工程を必要とするので、既存
の回路素子上への積層、大面積化には不向きである。加
えて、GaやAsなどは毒性も強く工業的に取り扱うに
は問題の多い材料である。
Most of the materials used to create such APDs are crystalline semiconductors, particularly materials mainly composed of SL of the RV group and GaAs5InP of the II-V group. Creating an APD using a crystalline semiconductor material generally requires a high-temperature, ultra-high vacuum manufacturing process, so it is not suitable for stacking on existing circuit elements or for increasing the area. In addition, Ga, As, and the like are highly toxic materials and are problematic to handle industrially.

そこで、工業的に安価で、低温で作成でき、既存回路上
への積層や大面積化にも向いている、非晶質半導体材料
を用いたAPDの実現が望まれる。
Therefore, it is desired to realize an APD using an amorphous semiconductor material, which is industrially inexpensive, can be produced at low temperatures, and is suitable for stacking on existing circuits and increasing the area.

非晶質半導体を用いたAPDを実現する方式として、従
来、Seを主体とする非晶質半導体で電荷注入阻止型構
造を形成し、非晶質半導体内でアバランシェ増倍を起こ
して信号増幅を行なう方式(テレビジョン学会技術報告
1987年第10巻1−6ページ)、水素やハロゲン(
例えばフッ素、塩素)を含むSLを主体とする非晶質半
導体で、p+πpnn”接合を形成してpn接合部空乏
層でアバランシェ増倍を起こして信号増倍を行なう方式
(特開昭55−95953号公報)、あるいは、水素お
よびハロゲン元素の少なくとも一方を含むSiとCの化
合物を主体とする非晶質半導体で、SLとCの組成比を
膜厚方向に連続的に変化させた層を多数積層して電子の
増倍率を高めたアバランシェ増倍を起こして信号増倍を
行なう方式(特開昭63−233574号公報)が提案
されている。
Conventionally, as a method for realizing APD using an amorphous semiconductor, a charge injection blocking structure is formed using an amorphous semiconductor mainly composed of Se, and avalanche multiplication occurs within the amorphous semiconductor to amplify the signal. method (Television Society Technical Report 1987 Vol. 10, pages 1-6), hydrogen and halogen (
For example, a method of signal multiplication by forming a p+πpnn" junction in an amorphous semiconductor mainly composed of SL containing fluorine, chlorine) and causing avalanche multiplication in the pn junction depletion layer (Japanese Unexamined Patent Publication No. 55-95953 (No. Publication), or an amorphous semiconductor mainly composed of a compound of Si and C containing at least one of hydrogen and halogen elements, with many layers in which the composition ratio of SL and C is continuously varied in the film thickness direction. A method has been proposed (Japanese Patent Application Laid-Open No. 63-233574) in which signal multiplication is carried out by stacking layers to increase the electron multiplication factor to cause avalanche multiplication.

[発明が解決しようとする課題] 上記従来技術である非晶質Se中でのアバランシェ増倍
、あるいは、非晶質SLのpn接合部でのアバランシェ
増倍を用いる方法においては、動作の熱的安定性に問題
があった。
[Problems to be Solved by the Invention] In the prior art method using avalanche multiplication in amorphous Se or avalanche multiplication at the pn junction of amorphous SL, the thermal There were stability issues.

すなわち、前者の場合には、非晶質材料自身の耐熱性が
乏しく、長時間の動作、高温環境に長時間放置した場合
の特性の劣化が顕著であった。また後者においては、室
温程度以上における暗電流の増加が著しく、十分な増倍
率を得るほどに高電界を印加することができなかった。
That is, in the former case, the amorphous material itself has poor heat resistance, and the characteristics deteriorate significantly when operated for a long time or left in a high-temperature environment for a long time. Furthermore, in the latter case, the dark current increases significantly at temperatures above about room temperature, making it impossible to apply a high enough electric field to obtain a sufficient multiplication factor.

また、後者の場合には、pn接合界面に再結合中心が多
数存在するために、空乏層があまり広がらず、十分な増
倍率が得られないという欠点も有していた。
In addition, in the latter case, since there are many recombination centers at the pn junction interface, the depletion layer does not expand much and a sufficient multiplication factor cannot be obtained.

上記従来技術であるSiとCの組成比を変化させた層の
多層構造でのアバランシェ増倍を用いる方法では、熱的
安定性についての考慮はなされているものの、SLとC
の組成比を連続的に変化させるための製法上の困難があ
るとともに、SLとCの化合物に再結合中心が多数存在
することによる暗電流の増加が著しく、この場合も、十
分な増倍率を得るほどに高電界を印加することができな
かった。
In the conventional technique described above, which uses avalanche multiplication in a multilayer structure of layers with varying composition ratios of Si and C, although consideration is given to thermal stability, SL and C
In addition to the difficulty in the manufacturing method of continuously changing the composition ratio of SL and C, the dark current increases significantly due to the presence of many recombination centers in the compound of SL and C. It was not possible to apply a high enough electric field.

すなわち、元来、半導体中で衝突電離のごとき電荷の増
倍を行なわせるためには、自由キャリアがその平均自由
行程内に衝突電離を起こすのに必要なエネルギを獲得で
きるように、十分な高電界を印加しなければらないわけ
であるが、非晶質Siの単なるpin構造では、ダング
リングボンドなどの再結合中心が多数存在するために、
衝突電離のような電荷増倍を起こす目的で、大きな逆バ
イアス電圧を印加する都、暗電流の増加が顕著になって
しまい、現実的な素子性能を得ることができなかった。
In other words, in order to carry out charge multiplication such as impact ionization in a semiconductor, a sufficiently high level of energy must be required so that free carriers can acquire the energy necessary to cause impact ionization within their mean free path. An electric field must be applied, but in a simple pin structure of amorphous Si, there are many recombination centers such as dangling bonds, so
When a large reverse bias voltage is applied to cause charge multiplication such as impact ionization, the dark current increases significantly, making it impossible to obtain realistic device performance.

本発明の目的は、上記従来の技術の問題点を除去し、高
感度で、光応答特性も良好で、耐熱性にも優れ、作成が
容易で、既存回路上への積層が可能で、大面積化も可能
な非晶質半導体光電変換素子を提供することにある。
The purpose of the present invention is to eliminate the problems of the above-mentioned conventional techniques, and to provide high sensitivity, good photoresponse characteristics, excellent heat resistance, easy fabrication, and the ability to stack on existing circuits. An object of the present invention is to provide an amorphous semiconductor photoelectric conversion element that can be expanded in area.

[課題を解決するための手段及び作用]最近、a−3e
 (非晶質Se)において、10’V/cm以上の高電
界下でアバランシェ増倍が生じることが報告されている
(Y、Takasaki et al、 :1988 
MR3Spring Meeting Symposi
um) oこのことは、新機能アモルファス半導体デバ
イスの開発という実用的見地からのみならず、高電界下
のキャリア輸送現象に関する情報が得られる点において
も興味深い。このような観点から我々は、a−3L (
非晶質Si)においても同様の現象が生じる可能性を探
るために、a−3L系フオトダイオードの逆方向パイア
スー光電流特性の検討を行っている。本発明はこのよう
な検討に基づいてなされたものである。
[Means and actions for solving the problem] Recently, a-3e
It has been reported that avalanche multiplication occurs in (amorphous Se) under a high electric field of 10'V/cm or more (Y, Takasaki et al.: 1988
MR3Spring Meeting Symposia
um) oThis is interesting not only from the practical standpoint of developing amorphous semiconductor devices with new functions, but also because it provides information on carrier transport phenomena under high electric fields. From this perspective, we have a-3L (
In order to explore the possibility that a similar phenomenon may occur in amorphous Si (amorphous Si), we are investigating the reverse polarity photocurrent characteristics of a-3L photodiodes. The present invention has been made based on such considerations.

本発明の光電変換素子は、i層が非晶質SLで構成され
ているpin型光電変換素子において、p型半導体層と
n型半導体層との間に非晶質窒化Si層を設け、前記光
電変換素子に逆バイアス電圧を印加したときに、前記非
晶質窒化Si層又は/及び前記非晶質窒化Si層近傍に
電界を集中させて電荷増幅を行なうことを特徴とする。
The photoelectric conversion element of the present invention is a pin type photoelectric conversion element in which the i-layer is composed of an amorphous SL, in which an amorphous Si nitride layer is provided between a p-type semiconductor layer and an n-type semiconductor layer, and the The present invention is characterized in that when a reverse bias voltage is applied to the photoelectric conversion element, an electric field is concentrated on the amorphous Si nitride layer and/or the vicinity of the amorphous Si nitride layer to perform charge amplification.

本発明の光電変換素子は、素子を構成する非晶質Si層
の内部またはそれに隣接して、より絶縁的性質を有する
非晶質窒化Siを設け、この非晶質窒化Si近傍に電界
を集中させて、効率的に電荷の増倍を行なうので、素子
全体にわたって高電界を印加する必要がなく、大きな逆
バイアス電圧印加に伴う暗電流の顕著な増加を回避する
ことができる。
In the photoelectric conversion device of the present invention, amorphous Si nitride having more insulating properties is provided inside or adjacent to the amorphous Si layer constituting the device, and an electric field is concentrated near the amorphous Si nitride. Since charge is multiplied efficiently, there is no need to apply a high electric field to the entire device, and a significant increase in dark current due to application of a large reverse bias voltage can be avoided.

本発明の光電変換素子の動作について、図面を用いて以
下に詳しく説明する。
The operation of the photoelectric conversion element of the present invention will be explained in detail below using the drawings.

第1図(a)に示すように、p型半導体層であるp型非
晶質炭化Si層1と、非晶質窒化SL層2と、i型半導
体層である非晶質Sii層と、n型半導体層であるn型
微結晶5il14とを順次積層してなる光電変換素子の
一端に透明電極を形成し、他の端には金属電極を形成し
て作成される光電変換素子に光を入射し、かつ上記両端
の電極に逆バイアス電圧を印加すると、非晶質窒化5i
Jllおよび非晶質窒化Si層近傍の非晶質SL層に高
電界が集中する。
As shown in FIG. 1(a), a p-type amorphous Si carbide layer 1 which is a p-type semiconductor layer, an amorphous nitride SL layer 2, an amorphous Sii layer which is an i-type semiconductor layer, A transparent electrode is formed at one end of a photoelectric conversion element formed by sequentially laminating n-type microcrystals 5il14, which are n-type semiconductor layers, and a metal electrode is formed at the other end. When a reverse bias voltage is applied to the electrodes at both ends, amorphous nitride 5i
A high electric field is concentrated in the amorphous SL layer near Jll and the amorphous Si nitride layer.

光照射により非晶質炭化Si層で生成された電子・正孔
のうちの電子は、上記高電界によりトンネル効果もしく
は拡散により、非晶質窒化SL層の伝導帯に注入される
。つづいて、この非晶質窒化Si層の伝導帯に注入され
た電子は、上記の高電界により加速され、衝突電離によ
る電荷の増倍を生じるに至る。すなわち、光照射によっ
て発生した電荷を素子内部で増倍する高感度な光電変換
素子が実現できる。
Among the electrons and holes generated in the amorphous Si carbide layer by light irradiation, electrons are injected into the conduction band of the amorphous nitride SL layer by tunneling or diffusion due to the high electric field. Subsequently, the electrons injected into the conduction band of the amorphous Si nitride layer are accelerated by the above-mentioned high electric field, resulting in charge multiplication due to impact ionization. That is, it is possible to realize a highly sensitive photoelectric conversion element that multiplies charges generated by light irradiation inside the element.

本発明においては、非晶質窒化SL層を非晶質Si層の
内部またはそれに隣接して設けることにより、光電変換
素子の一部にのみ電界を集中させ、効率的に衝突電離に
よる電荷の増倍作用を生起させることが重要であり、上
記の光増倍作用は、上記非晶質窒化SL層中でも非晶質
窒化Si層近傍の非晶質Si層中でもよく、また同時に
両方で生じてもよい。
In the present invention, by providing the amorphous nitride SL layer inside or adjacent to the amorphous Si layer, the electric field can be concentrated only in a part of the photoelectric conversion element, and the charge can be efficiently increased by impact ionization. It is important to produce double effect, and the above-mentioned photomultiplying effect may occur in the amorphous nitride SL layer, the amorphous Si layer near the amorphous nitride Si layer, or both at the same time. good.

さらに、非晶質窒化Si層を設ける位置は、p型非晶質
Si層と非晶質SL層の間でも、非晶質SL層の内部で
も、またn型機結晶SL層と非晶質Si層との間でもよ
いが、好ましくは、上に示したp型非晶質SL層と非晶
質Si層の間か、あるいは第1図(b)に示した非晶質
Si層の内部であることが望ましい。
Furthermore, the position where the amorphous Si nitride layer is provided is between the p-type amorphous Si layer and the amorphous SL layer, inside the amorphous SL layer, or between the n-type mechanical crystal SL layer and the amorphous SL layer. It may be between the p-type amorphous SL layer and the amorphous Si layer shown above, or inside the amorphous Si layer shown in FIG. 1(b). It is desirable that

第1図に示した本発明の光電変換素子では、ある程度長
い時間逆バイアス電圧を印加し続けると、非晶質窒化S
L層の両端に電子および/もしくは正孔が蓄積して、異
種層である非晶質窒化SL層および非晶質窒化Si層近
傍の非晶質SL層に集中する電界をさらに高くし、した
がって、電荷増倍作用はさらに増大する。
In the photoelectric conversion element of the present invention shown in FIG.
Electrons and/or holes accumulate at both ends of the L layer, further increasing the electric field concentrated in the amorphous nitride SL layer and the amorphous SL layer near the amorphous nitride Si layer, which are dissimilar layers, and thus , the charge multiplication effect further increases.

上記のように非晶質Siに挿入する非晶質窒化Siのご
とき異種層としては、原理的には様々な材料を使用する
ことが可能であるが、非晶質SL層と比較的良好な界面
を形成でき、かつエネルギ・ギャップ、伝導帯のバンド
端の位置(電子親和力)を比較的制御しやすい非晶質窒
化Si層が望ましく、さらに、電界が集中し効率的な増
倍作用を得、かつ低印加電圧において十分な電流を流す
ためには、エネルギ・ギャップが2.4eV程度となる
組成の非晶質窒化Si層がより望ましい。
As mentioned above, various materials can be used in principle for the heterogeneous layer such as amorphous Si nitride inserted into the amorphous Si, but there are some materials that are relatively good with the amorphous SL layer. It is desirable to use an amorphous Si nitride layer that can form an interface and relatively easily control the energy gap and the position of the band edge of the conduction band (electron affinity), as well as concentrate the electric field and obtain an efficient multiplication effect. , and in order to flow a sufficient current at a low applied voltage, it is more desirable to use an amorphous Si nitride layer having a composition such that the energy gap is about 2.4 eV.

さらに、上記の非晶質Si層の層厚は、非晶質窒化SL
層を設ける位置、要求する光電変換素子としての機能を
実現するのに必要な印加電圧および必要な増倍率、非晶
質Si層の層厚などによって決定されるが、通常の用途
の素子に印加される電圧としては高々数十ボルトである
ことが好ましく、この印加電圧において増倍した電荷を
効率よく非晶質Si中を走行させ、応答性よく信号電荷
として取り出すためには、非晶質SL層の層厚としては
lum程度が好ましいため、このような場合には、上記
の非晶質窒化SL層の層厚としては、100人よりも大
きければよく、好ましくは200人−500Åがよい。
Furthermore, the layer thickness of the above amorphous Si layer is amorphous nitride SL
It is determined by the position where the layer is provided, the applied voltage and multiplication factor necessary to realize the required function as a photoelectric conversion element, the layer thickness of the amorphous Si layer, etc. It is preferable that the applied voltage is several tens of volts at most, and in order to make the charge multiplied at this applied voltage travel efficiently through the amorphous Si and take it out as a signal charge with good response, it is necessary to Since the thickness of the layer is preferably approximately lum, in such a case, the thickness of the amorphous nitrided SL layer may be greater than 100 Å, preferably 200 Å to 500 Å.

また、本発明の光電変換素子のp型半導体層としては、
電極からの電荷の注入を阻止する機能を有し、かつ上記
の異種層がp型半導体層に接して設けられる場合には、
光電変換機能を有するものであれば、上記の非晶質炭化
Si層以外の材料も適宜使用できることは本発明の光電
変換素子の動作原理から明らかである。
Moreover, as the p-type semiconductor layer of the photoelectric conversion element of the present invention,
When the above-mentioned heterogeneous layer has the function of blocking charge injection from the electrode and is provided in contact with the p-type semiconductor layer,
It is clear from the operating principle of the photoelectric conversion element of the present invention that materials other than the above-mentioned amorphous Si carbide layer can be appropriately used as long as they have a photoelectric conversion function.

これと同様に、n型半導体層も上記の微結晶Si層以外
の材料も適宜使用できることは明らかである。
Similarly, it is clear that materials other than the above-mentioned microcrystalline Si layer can also be used for the n-type semiconductor layer as appropriate.

また、本素子を作成するための製法としては、一般には
、堆積法が有効であり、蒸着法、化学的気相析出(CV
D)法、気相エピタキシ法、スパッタ法、分子線エピタ
キシ法などが利用できる。このうち特に、、非晶質半導
体層は、容量結合型堆積膜形成装置によるグロー放電法
で作成されるのが好ましい。この方法は、作成温度が3
00℃前後と低温なために既に集積回路などが形成され
ている半導体装置上にも容易に積層して作成できること
、原料ガスの成分を変えることだけで異種の半導体層を
容易に作成できること、無公害の工業的にも安価な材料
が利用できること、大面積の成膜も容易に行なえること
などの特徴を有しており、したがって、これを利用して
本発明の光電変換素子を作成すれば、従来の問題点を全
て解決できる。
In addition, as a manufacturing method for creating this device, deposition methods are generally effective, and vapor deposition methods, chemical vapor deposition (CVD), etc.
D) method, vapor phase epitaxy method, sputtering method, molecular beam epitaxy method, etc. can be used. Among these, it is particularly preferable that the amorphous semiconductor layer be formed by a glow discharge method using a capacitively coupled deposited film forming apparatus. This method requires a creation temperature of 3
Because the temperature is around 00°C, it can be easily stacked on semiconductor devices on which integrated circuits and the like have already been formed, and different types of semiconductor layers can be easily created by simply changing the ingredients of the raw material gas. It has characteristics such as being able to use materials that are low in pollution and industrially, and being able to easily form a film over a large area. , can solve all the conventional problems.

[実施例] 以下、本発明の実施例を図面にしたがって説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.

(実施例1) 作製した試料は、p−1−n a−3L太陽電池構造の
p/i界面に光学ギャップが2.4eVのa−3iN 
(非晶質窒化SL)層を挿入したものである。また、u
ndoped a−Si層の膜厚は1μmである。
(Example 1) The prepared sample was a-3iN with an optical gap of 2.4 eV at the p/i interface of a p-1-n a-3L solar cell structure.
(Amorphous nitride SL) layer is inserted. Also, u
The thickness of the ndoped a-Si layer is 1 μm.

本発明の第1の実施例の素子の断面図を第2図(a)に
示す。
A sectional view of a device according to a first embodiment of the present invention is shown in FIG. 2(a).

本素子は次の操作により作成した。This device was created by the following operations.

まず、コーニング社製の7059ガラス基板1011 上に、蒸着装置により、ITO/5no2からなる透明
電極102を作成し、電極の形状が所定の形状になるよ
うにエツチングした。
First, a transparent electrode 102 made of ITO/5no2 was formed using a vapor deposition apparatus on a 7059 glass substrate 1011 manufactured by Corning, and etched so that the electrode had a predetermined shape.

次に、容量結合型の堆積膜形成装置のアノード電極に基
板を設置し、堆積室内を、約10−’Torrに排気し
、ヒーターにより基板を約300℃に加熱した。基板が
所定の温度になった後に、水素ガス中2で10%に希釈
したシランガスSiSiH4100se、およびメタン
ガスCH410secmを堆積室に導入する。堆積室の
内圧が所定の圧力約0.3Torrになったことを確認
してから、高周波電力(13,56MHz)0.5W/
cm”を堆積室内に投入した。所定の時間グロー放電を
行なって、非晶質p型膜化Siからなるブロッキング層
および受光層103を200人堆積した。
Next, the substrate was placed on the anode electrode of a capacitively coupled deposited film forming apparatus, the inside of the deposition chamber was evacuated to about 10-' Torr, and the substrate was heated to about 300° C. with a heater. After the substrate reaches a predetermined temperature, silane gas SiSiH4100se diluted to 10% with 2 in hydrogen gas and methane gas CH410 sec are introduced into the deposition chamber. After confirming that the internal pressure of the deposition chamber reached the predetermined pressure of approximately 0.3 Torr, high-frequency power (13,56 MHz) 0.5 W/
cm'' was put into the deposition chamber.Glow discharge was performed for a predetermined period of time, and 200 layers of blocking layer and light-receiving layer 103 made of amorphous p-type Si film were deposited.

その後、ブロッキング層および受光層103と同様の手
順で、水素ガス中2で10%に希釈したシランガスSi
H< 100 sccmとアンモニアガスNH35se
cmとから非晶質窒化SL[104を200人と、水素
ガス中2で10%に希釈したシランガスSiH42 100secmから非晶質Si層105を10000人
と、水素ガス中2で10%に希釈したシランガス5iH
4100secmとフォスフインガスPHa 10sc
cmから微結晶n型Si層106を500人を順次堆積
した。
After that, in the same procedure as for the blocking layer and the light-receiving layer 103, silane gas Si diluted to 10% with 2 in hydrogen gas was added.
H<100 sccm and ammonia gas NH35se
cm and amorphous nitride SL[104 diluted to 10% with 2 in hydrogen gas SiH42 with 100 sec of amorphous Si layer 105 diluted with 2 in hydrogen gas to 10% Silane gas 5iH
4100sec and phosphine gas PHa 10sc
500 microcrystalline n-type Si layers 106 were sequentially deposited from 50 cm to 10 cm.

最後に、電極として、AI層107を蒸着し、A1層1
07、微結晶n型Si層106、非晶質Si層105、
非晶質窒化SL層104、および非晶質炭化SL層10
3をそれぞれ所定の形状にエツチングした。
Finally, an AI layer 107 is deposited as an electrode, and the A1 layer 1
07, microcrystalline n-type Si layer 106, amorphous Si layer 105,
Amorphous nitride SL layer 104 and amorphous carbide SL layer 10
3 was etched into a predetermined shape.

各半導体層のバンドギャップは、光学的に測定したとこ
ろ、非晶質p型膜化Si層が2.OeV 、非晶質窒化
Si層が2.4eV s非晶質Si層が1.8eV 、
微結晶n型Si層が1.9eVであった。
When the band gap of each semiconductor layer was optically measured, the amorphous p-type Si film layer had a band gap of 2. OeV, 2.4 eV for amorphous Si nitride layer, 1.8 eV for amorphous Si layer,
The microcrystalline n-type Si layer had a voltage of 1.9 eV.

上記試料に、波長460 nmの光(光量2.36X1
0”photons/s−em”)をp層側から照射し
て光電流を測定した。第2図(b)は、a−3iN  
(非晶質窒化Si)層の膜厚を0〜500人と変化させ
たときのJ−V (直流電流電圧)特性であるが、a−
3iNを挿入すると量子効率は1を越え、しかも厚くな
るにつれて電流の増加率も大きくなるという結果が得ら
れた。
Light with a wavelength of 460 nm (light intensity 2.36 x 1
0"photons/s-em") was irradiated from the p-layer side and the photocurrent was measured. FIG. 2(b) shows a-3iN
The J-V (direct current voltage) characteristics when the film thickness of the (amorphous Si nitride) layer is varied from 0 to 500 layers are a-
The results showed that when 3iN was inserted, the quantum efficiency exceeded 1, and the rate of increase in current also increased as the thickness increased.

すなわち、印加電圧30Vで約2倍の増倍率が、また、
印加電圧40Vで約4倍の増倍率が得られた。
That is, at an applied voltage of 30 V, the multiplication factor is about 2 times, and
At an applied voltage of 40 V, a multiplication factor of approximately 4 times was obtained.

また、信号電流と暗電流の比は2桁以上得られた。Moreover, the ratio of signal current to dark current was obtained by more than two orders of magnitude.

また、本実施例の光電変換素子に照射する光を点滅させ
て光応答速度を測定したところ、第2図(c)に示すよ
うに約2 m5ecの立ち上り応答速度が得られた。
Furthermore, when the light response speed was measured by blinking the light irradiated onto the photoelectric conversion element of this example, a rise response speed of about 2 m5ec was obtained as shown in FIG. 2(c).

また、これを、80℃で長時間連続動作させた場合にも
、特性変化は生じなかった。
Further, even when this was operated continuously for a long time at 80° C., no change in characteristics occurred.

さらにまた、非晶質窒化Si層の厚さは、上記実施例で
は、200人であったが、堆積時間を変えと、これを5
00人としても、第2図(b)に示すように上記実施例
と同様の効果が得られた。また、非晶質窒化Si層の層
厚を上記実施例の200人よりも薄い100人としたと
きには、第2図(b)に示すように十分な増倍効果は得
られなかった。
Furthermore, the thickness of the amorphous Si nitride layer was 200 in the above example, but by changing the deposition time, the thickness was increased to 5.
Even if the number of participants was 0.00, the same effect as in the above example was obtained as shown in FIG. 2(b). Furthermore, when the thickness of the amorphous Si nitride layer was set to 100 layers, which is thinner than the 200 layers in the above example, a sufficient multiplication effect could not be obtained as shown in FIG. 2(b).

(実施例2) 本発明の第2の実施例を第3図(a)に示す。(Example 2) A second embodiment of the invention is shown in FIG. 3(a).

本素子は次の操作により作成した。This device was created by the following operations.

まず、コーニング社製の7059ガラス基板20L上に
、蒸着装置により、ITO/5nOaからなる透明電極
202を作成し、電極の形状が所定の形状になるように
エツチングした。
First, a transparent electrode 202 made of ITO/5nOa was formed using a vapor deposition apparatus on a 7059 glass substrate 20L manufactured by Corning, and etched so that the electrode had a predetermined shape.

次に、容量結合型の堆積膜形成装置のアノード電極に基
板を設置し、堆積室内を、約10−’Torrに排気し
、ヒーターにより基板を約300℃に加熱した。基板が
所定の温度になった後に、水素ガス中2でio%に希釈
したシランガスSiH<101005e、およびメタン
ガスCI410eccmを堆積室に導入する堆積室の内
圧が所定の圧力約0.3Torrになったことを確認し
てから、高周波電力(13,56MHz) 0゜5W/
cm”を堆積室内に投入した。所定の時間グロー放電を
行なって、非晶質p型炭化Siからなるブロキッング層
および受光層203を200人堆積した。
Next, the substrate was placed on the anode electrode of a capacitively coupled deposited film forming apparatus, the inside of the deposition chamber was evacuated to about 10-' Torr, and the substrate was heated to about 300° C. with a heater. After the substrate reached a predetermined temperature, silane gas SiH<101005e diluted to io% with hydrogen gas and methane gas CI410eccm were introduced into the deposition chamber.The internal pressure of the deposition chamber became a predetermined pressure of about 0.3 Torr. After checking, high frequency power (13,56MHz) 0゜5W/
cm" was placed in the deposition chamber. Glow discharge was performed for a predetermined period of time to deposit 200 blocking layers and light-receiving layers 203 made of amorphous p-type Si carbide.

 5 その後、ブロッキング層および受光層203と同様の手
順で水素ガス中2で10%に希釈したシランガス5iH
4100secmから非晶質Si層204を5000人
と、水素ガス中2で10%に希釈したシランガスSiH
< 100 sccmとアンモニアガスNH。
5 After that, silane gas 5iH diluted to 10% with 2 in hydrogen gas was added in the same manner as the blocking layer and light receiving layer 203.
From 4100 sec to 5000 sec, the amorphous Si layer 204 was diluted to 10% with silane gas SiH in hydrogen gas.
<100 sccm and ammonia gas NH.

5 secmとから非晶質窒化Si層205を200人
と、水素ガス中2で10%に希釈したシランガス5iH
4100sccmから非晶質SL層206を500o人
と、水素ガス中2で10%に希釈したシランガスSiH
< 100 secmとフォスフインガスPHs 10
eccmから微結晶n型シリコン層207を500人を
順次堆積した。
The amorphous Si nitride layer 205 from 5 sec.
From 4100 sccm to 500 sccm, silane gas SiH diluted to 10% with 2 in hydrogen gas
< 100 sec and phosphine gas PHs 10
Five hundred microcrystalline n-type silicon layers 207 were sequentially deposited from eccm.

最後に、電極として、A1層208を蒸着し、A1層2
08、微結晶n型Si層207、非晶質SL層206、
非晶質窒化SL層205、非晶質SL層204および非
晶質炭化Si層203をそれぞれ所定の形状にエツチン
グした。
Finally, the A1 layer 208 is deposited as an electrode, and the A1 layer 208 is deposited as an electrode.
08, microcrystalline n-type Si layer 207, amorphous SL layer 206,
Amorphous nitrided SL layer 205, amorphous SL layer 204, and amorphous Si carbide layer 203 were each etched into predetermined shapes.

各半導体層のバンドギャップは、光学的に測定したとこ
ろ、非晶質p塑成化りt層が2.OeV 、非晶質窒化
Si層が2.4eV 、非晶質Si層が1.8eV 、
微結 6 晶n型Si層が1.9eVであった。
The band gap of each semiconductor layer was optically measured, and the amorphous p-plasticized t-layer had a band gap of 2. OeV, 2.4 eV for the amorphous Si nitride layer, 1.8 eV for the amorphous Si layer,
The microcrystalline 6 crystal n-type Si layer had a voltage of 1.9 eV.

本実施例の光電変換素子に、波長660nm、光量7.
6 X 10−’W/cm”の光を照射し、直流電流電
圧特性を測定したところ、第3図(b)に示すような特
性が得られた。すなわち印加電圧30Vで約1゜5倍の
増倍率が、また、印加電圧40Vで約4倍の増倍率が得
られた。
The photoelectric conversion element of this example has a wavelength of 660 nm and a light intensity of 7.
When we irradiated it with light of 6 x 10-'W/cm" and measured the DC current-voltage characteristics, we obtained the characteristics shown in Figure 3 (b). That is, at an applied voltage of 30 V, the A multiplication factor of approximately 4 times was obtained at an applied voltage of 40 V.

また、信号電流と暗電流の比は2桁以上得られた。Moreover, the ratio of signal current to dark current was obtained by more than two orders of magnitude.

また、本実施例の光電変換素子に照射する光を点滅させ
て光応答速度を測定したところ、第3図(c)に示すよ
うに約50μsecの立ち上り応答速度が得られた。
Further, when the photoresponse speed was measured by blinking the light irradiated to the photoelectric conversion element of this example, a rise response speed of about 50 μsec was obtained as shown in FIG. 3(c).

また、これを、80℃で長時間連続動作させた場合にも
、特性変化は生じなかった。
Further, even when this was operated continuously for a long time at 80° C., no change in characteristics occurred.

[発明の効果] 以上から明らかなように、本発明により、高感度で、光
応答性も良好で、耐熱性にも優れ、作成も容易な、既存
回路上への積層も可能で、大面積化も可能な非晶質半導
体光電変換素子を得ることができる。
[Effects of the Invention] As is clear from the above, the present invention has high sensitivity, good photoresponsiveness, excellent heat resistance, is easy to create, can be laminated on existing circuits, and has a large area. It is possible to obtain an amorphous semiconductor photoelectric conversion element that can also be converted into

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a) (b)は、本発明の光電変換素子の概略
的なエネルギ帯同である。 第2図(a)は、本発明の第1の実施例の概略的素子構
成図、第2図(b)は、a−3iN層の膜厚を0−50
0Åと変化させたときの光照射に対する直流電流電圧(
J−V)特性図、第2図(c)は光電変換素子に照射す
る光を点滅させた時の光応答性を示す特性図である。 第3図(a)は、本発明の第2の実施例の概略的素子構
成図、第3図(b)は、光照射に対する直流電流電圧(
J−V)特性図、第3図(c)は光電変換素子に照射す
る光を点滅させた光応答性を示す特性図である。 1.103,203・・・非晶質炭化Si層2.104
,205・・・非晶質窒化31層3.3  ′、  1
05,204,206・・・非晶質Si層
FIGS. 1(a) and 1(b) are schematic energy band diagrams of the photoelectric conversion element of the present invention. FIG. 2(a) is a schematic diagram of the device configuration of the first embodiment of the present invention, and FIG. 2(b) shows the thickness of the a-3iN layer of 0-50.
DC current voltage (
FIG. 2(c) is a characteristic diagram showing the photoresponsiveness when the light irradiated to the photoelectric conversion element is blinked. FIG. 3(a) is a schematic diagram of the element configuration of the second embodiment of the present invention, and FIG. 3(b) is a diagram showing the direct current voltage (
J-V) characteristic diagram, FIG. 3(c) is a characteristic diagram showing the photoresponsiveness when the light irradiated to the photoelectric conversion element was blinked. 1.103,203...Amorphous Si carbide layer 2.104
, 205...Amorphous nitride 31 layer 3.3', 1
05,204,206...Amorphous Si layer

Claims (2)

【特許請求の範囲】[Claims] (1)i層が非晶質Siで構成されるpin型光電変換
素子において、 p型半導体層とn型半導体層との間に非晶質窒化Si層
を設け、この非晶質窒化Si層を有する前記光電変換素
子に逆バイアス電圧を印加したときに、前記非晶質窒化
Si層又は/及び前記非晶質窒化Si層近傍に電界を集
中させて電荷増幅を行なうことを特徴とする光電変換素
子。
(1) In a pin-type photoelectric conversion element in which the i-layer is made of amorphous Si, an amorphous Si nitride layer is provided between a p-type semiconductor layer and an n-type semiconductor layer, and this amorphous Si nitride layer When a reverse bias voltage is applied to the photoelectric conversion element having the above, an electric field is concentrated in the amorphous Si nitride layer and/or in the vicinity of the amorphous Si nitride layer to perform charge amplification. conversion element.
(2)前記非晶質窒化Si層の膜厚が200Å以上、5
00Å以下であることを特徴とする請求項1記載の光電
変換素子。
(2) The thickness of the amorphous Si nitride layer is 200 Å or more,
2. The photoelectric conversion element according to claim 1, wherein the photoelectric conversion element has a thickness of 00 Å or less.
JP1201452A 1989-08-04 1989-08-04 Optoelectric transducer Pending JPH0366178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1201452A JPH0366178A (en) 1989-08-04 1989-08-04 Optoelectric transducer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1201452A JPH0366178A (en) 1989-08-04 1989-08-04 Optoelectric transducer

Publications (1)

Publication Number Publication Date
JPH0366178A true JPH0366178A (en) 1991-03-20

Family

ID=16441325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1201452A Pending JPH0366178A (en) 1989-08-04 1989-08-04 Optoelectric transducer

Country Status (1)

Country Link
JP (1) JPH0366178A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129649A (en) * 1991-11-06 1993-05-25 Hamamatsu Photonics Kk Solid-state image sensor
US5634816A (en) * 1994-08-04 1997-06-03 Yazaki Corporation Structure of mounting electrical unit on wall surface

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129649A (en) * 1991-11-06 1993-05-25 Hamamatsu Photonics Kk Solid-state image sensor
US5634816A (en) * 1994-08-04 1997-06-03 Yazaki Corporation Structure of mounting electrical unit on wall surface

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