JPH05129169A - Manufacture of semiconductor wafer - Google Patents

Abstract

PURPOSE:To manufacture an unwarpped multilayered wafer without complicating the device processing steps while suppressing the cost and maintaining the electrical properties. CONSTITUTION:At first, an N<+>/N<-> silicon wafer 13 is formed by epitaxially depositing a highly concentrated N<+> layer 12 of 10 to 12mum in thickness on a single crystal silicon wafer (N<-> wafer) 11 in which N-type impurities of a given concentration such as phosphorus are doped. Besides this silicon wafer 13, a highly concentrated boron-doped P<+> type polished wafer 14 is prepared. The polished surface of this P<+> silicon wafer 14 and the surface of the N<+> epitaxial layer 12 of the N<+>/N<-> silicon wafer 13 are superposed and adhesively bonded at room temperature. The N<-> layer 11 of this P<+>/N<+>/N<-> silicon wafer 15 is cut off by a given thickness. After this bonding, a heat treatment is executed at a given temperature.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor wafer, more specifically, by using a bonding method.
The present invention relates to a method for manufacturing a semiconductor wafer that suppresses warpage that occurs in a semiconductor wafer composed of multiple layers that are composed of layers having different impurity concentrations and types.

[0002]

2. Description of the Related Art The manufacture of semiconductor wafers is carried out, for example, by IGB
A semiconductor wafer used for manufacturing T is usually a silicon wafer containing a high concentration (1 × 10 ¹⁹ cm ⁻³ ) of P-type impurities (for example, boron) and having a thickness of 10 to 15 μm and a concentration of N-type impurities. 2 to 50 × 10 ¹⁷ cm ⁻³ N ⁺ layer, and a thickness of 40 μm or more and an N-type impurity concentration of 1.5 ×
10 ^{1 4} cm ^-3 or less of N ^- being performed by the layers formed by epitaxial growth method. That is, N ⁻
An IGBT is formed on a semiconductor wafer having a laminated structure of / N ⁺ / P ⁺ .

In this case, if the type and concentration of impurities contained in the silicon wafer are different, the expansion coefficient of the silicon wafer is also different. When two substances having different expansion coefficients are attached to each other, the bimetal effect usually causes warpage in one direction.

In the IGBT device manufacturing process, as the SiO ₂ film and the Si ₃ N ₄ film are successively formed on the N ⁻ layer, the warp of the semiconductor wafer increases.

Conventionally, the above-mentioned warpage has not been a fatal problem in the manufacturing process of the IGBT device for the following reason. That is, the N ⁻ layer is relatively thin and the device breakdown voltage is low. In addition, the diameter of the semiconductor wafer used is small. Furthermore, the device design rule is large, for example, 7 to 5 μm, stepper exposure is unnecessary, and the influence of warpage is relatively small. That is, in the proximity exposure method and the projection exposure method, the tolerance for the warp of the exposure equipment is larger than that of the stepper exposure method.

However, as the withstand voltage of the IGBT device characteristics becomes higher, the pattern becomes finer, and the diameter of the wafer becomes larger, the absolute value of the warp increases, and the use of a stepper exposure apparatus becomes indispensable, and the tolerance for warpage is small. became.
As a result, it becomes necessary to suppress warpage of the semiconductor wafer for manufacturing the IGBT device.

In order to suppress the warp, for example, an LTO film having an appropriate thickness or a Si ₃ film is previously formed on the back surface of the P ⁺ wafer.
An N ₄ film is formed in advance. By this film, the stress is balanced with the silicon layer epitaxially grown on the surface side.

[0008]

However, according to this method, in order to prevent the peeling of the film, it was necessary to seal the back surface in the device manufacturing process. This backside seal complicates the device manufacturing process and raises the cost.

Therefore, it is conceivable to increase the thickness of the P ⁺ wafer so as to withstand the tensile stress generated in the N ⁻ layer and the N ⁺ layer. But in this case, P ⁺
The cost of the wafer increases, and the collector series resistance of the IGBT element increases, deteriorating the electrical characteristics.

Therefore, an object of the present invention is to manufacture a semiconductor wafer which eliminates such drawbacks and can manufacture a semiconductor wafer having a small warp among semiconductor wafers in which it is necessary to form multiple layers such as IGBTs. It is to provide a method.

[0011]

In the method of manufacturing a semiconductor wafer according to the present invention, a plurality of semiconductor wafers having different conductivity types or different impurity concentrations are individually manufactured, and these semiconductor wafers are bonded at room temperature. By combining them, a semiconductor wafer having a plurality of layers having different impurity concentrations and / or conductivity types is formed, and then the surface of the semiconductor wafer is ground.

A semiconductor wafer having an N ⁻ / N ⁺ / P ⁺ laminated structure is formed by separately preparing an N ⁻ / N ⁺ wafer and a P ⁺ wafer and bonding these wafers together. Is a manufacturing method.

[0013]

According to the semiconductor wafer manufacturing method of the present invention, the thick semiconductor wafer withstands the thermal stress in the device manufacturing process, so that warpage due to the bimetal effect does not occur. Further, by polishing the surface of the semiconductor wafer after bonding, a warped-free semiconductor wafer can be manufactured.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a process diagram for explaining a method for manufacturing a semiconductor wafer according to the first embodiment.

[0015] As shown in this figure, according to the method of the present invention, firstly, 1.5 × 10 ¹⁴ cm ^-3 or less of the concentration of the N-type impurity, such as phosphorus, a single crystal silicon wafer doped with antimony (N ^- Wafer) 11 on 2 to 50 × 10
An N ⁺ layer 12 having a phosphorus concentration of ¹⁷ cm ⁻³ is epitaxially grown to a thickness of 10 to 15 μm. As a result, the N ⁺ / N ^- silicon wafer 13 is formed.

Separately from the silicon wafer 13, a boron-doped P ⁺ polished wafer (P ⁺ wafer) 14 having a concentration of 1 × 10 ¹⁹ cm ^-3 is prepared.

Then, the polished surface of the P ⁺ silicon wafer 14 and the surface of the N ⁺ epitaxial layer 12 of the N ⁺ / N ^- silicon wafer 13 are laminated and bonded at room temperature. As a result, P ⁺ / N ⁺ / N ^- silicon wafer 15
Is created.

Then, on the P ⁺ / N ⁺ / N ^- silicon wafer 15, the N ^- layer 11 is shaved off by a predetermined thickness. Then, the surface of the N ⁻ layer 11 after this grinding is polished and finished. Further, if necessary, the front surface (back surface) of the P ⁺ layer 14
Polish off.

At the time of bonding the silicon wafers 13 and 14 to each other, the surface of the N ⁺ layer 12 as the bonding surface may be polished in order to improve the accuracy of the bonding surface. In this case, the N ⁺ layer 12 is thickly formed by the polishing amount. After the bonding, heat treatment is performed at a predetermined temperature (1000 ° C.).

FIG. 2 shows a second embodiment of the present invention.
In this embodiment, the N ⁺ layer 22 is formed on the N ⁻ wafer 21.
Is formed by epitaxial growth to a thickness of about 5 to 10 μm. Alternatively, by high concentration diffusion of phosphorus, N ⁺ /
An N ^- silicon wafer 23 is created. And separately,
An N ⁺ / P ⁺ silicon wafer 26 in which an N ⁺ layer 25 is epitaxially grown by 5 to 10 μm on a P ⁺ wafer (1 × 10 ¹⁹ cm ⁻³ ) 24 is prepared.

Then, these silicon wafers 23,
26 is adhered to the N ⁺ layers 22 and 25 in close contact with each other.
After that, the N ⁻ layer 21 and the P ⁺ layer 24 are ground to a predetermined thickness to produce an N ⁻ / N ⁺ / P ⁺ silicon wafer 27. Others are the same as those in the above embodiment.

FIG. 3 shows a third embodiment of the present invention. In this embodiment, N ^- by an N ⁺ layer 32 on a silicon wafer 31 for example epitaxial growth is formed to a predetermined thickness, the N ⁺ / N ^- silicon wafer 33 N ⁺
P ⁺ layer 3 containing a higher concentration of boron impurities on the layer 32
4 is formed to a thickness of 5 to 10 μm by epitaxial growth. In this way, the N ⁻ / N ⁺ / P ⁺ silicon wafer 35 is manufactured.

Then, a separately prepared P ⁺ polished silicon wafer 36 and this N ⁻ / N ⁺ / P ⁺ silicon wafer 3
5 and P ⁺ surfaces are closely adhered to each other, and then N ⁻ layer 31
And the P ⁺ layer 36 is ground to a predetermined thickness. As a result,
An N ⁻ / N ⁺ / P ⁺ silicon wafer 37 having a predetermined thickness is produced.

[0024] As described above, N ^- N ⁺ layer by epitaxial growth wafer or a silicon wafer to form a N ⁺ layer and the P ⁺ layer, desired by bonding the P ⁺ wafer N ^- / N ⁺ / P ⁺ wafers can be manufactured. However, according to the present invention, in addition to this, a silicon wafer having an N ⁺ layer or an N ⁺ layer and a thin N ⁻ layer formed on a P ⁺ wafer and an N ⁻ wafer are bonded together, and then an N ⁻ wafer is formed. It is also possible to grind the P ⁺ layer to a predetermined thickness to produce an N ⁻ / N ⁺ / P ⁺ silicon wafer.

In the above embodiments, the production of the P ⁺ / N ⁺ / N ^- wafer for producing the IGBT element has been described, but the present invention is not limited to this, and the N ⁺ / N ^- wafer is not limited to this. It can also be applied to the manufacturing of etc.

[0026]

According to the present invention, a warp-free semiconductor wafer can be obtained at room temperature even after the bonding process.
In this case, the device manufacturing process does not become complicated. Therefore, the cost does not increase. Moreover, the electrical characteristics of the semiconductor wafer are not deteriorated.

[Brief description of drawings]

FIG. 1 is a first method of manufacturing a semiconductor wafer according to the present invention.
It is a figure showing a process for explaining an example.

FIG. 2 is a second method of manufacturing a semiconductor wafer according to the present invention.
It is a figure which shows the process for demonstrating an Example.

FIG. 3 is a third method of manufacturing a semiconductor wafer according to the present invention.
It is a figure which shows the process for demonstrating an Example.

[Explanation of symbols]

13 N ⁺ / N ^- Wafer 14 P ⁺ wafer ^{15 N - / N + / P} + wafer

Claims (2)

[Claims] 1. A plurality of semiconductor wafers having different impurity concentrations and / or conductivity types are prepared by individually manufacturing a plurality of semiconductor wafers having different conductivity types or impurity concentrations and bonding these semiconductor wafers at room temperature. A method for manufacturing a semiconductor wafer, which comprises forming a semiconductor wafer and then grinding the surface of the semiconductor wafer. 2. An N ⁻ / N ⁺ wafer and a P ⁺ wafer are separately prepared, and these wafers are adhered to each other to obtain N ⁻ / N ^+.
/ P ⁺ A semiconductor wafer having a laminated structure is formed.