JPH0512853A - First in first out storage device - Google Patents

Abstract

PURPOSE:To transfer data to many directions with one memory. CONSTITUTION:By a write request and a read request from a first and a second input/output port A105, B106, the first and the second write pointer A107, B109 and the first and the second read pointer A108, B110, which generate write pointers and read pointers respectively, are provided. A direction data part in which information on the transfer direction of data is stored, a valid bit part in which information on the data existance of the same address is stored, and the pointer part are provided; and an association memory cell 113 by which the address of the data, in which the value of the direction data part and that of the valid bit part coincide and also the value of the pointer part and that of the read pointer part coincide, is outputted to the memory cell 117 is provided. A dead number setting counter 111 by which dead numbers are set in the pointer part of the association memory 113, a dead address retrieval number counter 112 in order to find dead numbers, and a selector 118 to decide to which input/output port, A105 or B106, the outputted data of the memory cell 17 is outputted in accordance to the value of the direction data part are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device for temporarily storing data, and more particularly to a first-in first-out storage device in which reading is performed in the order in which data is written.

[0002]

2. Description of the Related Art Generally, a first-in first-out storage device, that is, a FIFO (First In First Out) memory is a memory that is temporarily stored in the order in which an external signal sequence is input and is formed in the order in which an output is input. It is used as a data buffer that temporarily stores data between blocks with different operating speeds. There are the following two methods for realizing this FIFO memory. The first method is called the shift register type, and the written data is written to the next stage if it is empty. On the other hand, the second method is called a direct fall type and is composed of a random access memory (hereinafter abbreviated as RAM) and an address pointer.

In the FIFO memory constructed by the second method, the data input from the input port is temporarily stored in the memory and then output to the output port. Therefore, when this FIFO memory is applied to a bidirectional data transfer system, the structure shown in FIG. 2 must be adopted. That is, in this data transfer system, in the data transfer from the first CPU 31 to the second CPU 32, the first CPU 31 writes data in the FIFO memory 33 and the second CPU 32 writes in the FIFO memory 3.
Data transfer from the second CPU 32 to the first CPU 31 is performed by the second CPU 32 writing data to the FIFO memory 34, and the first CPU 31 is transferred to the FIFO memory 34.
It was realized by reading the data from.

A data transfer system having a plurality of CPUs has a structure as shown in FIG. That is, between the CPUs 41 to 4n and the data bus 61, the FIFO memories 51 to 5n corresponding to the number of the CPUs 41 to 4n are required.

[0005]

However, since the data transfer direction of the conventional FIFO memory is limited to a single direction, when two-way data transfer is performed, two blocks for data transfer are connected. The two FIFO memories 33 and 34 must be inserted in parallel to the data bus, which has a drawback that the system configuration becomes large and complicated.

Similarly, in the case of exchanging data between N blocks, N F blocks are connected in parallel to the data bus 61 connecting the N blocks for transferring data.
The IFO memories 51 to 5n had to be inserted, and the system configuration became large and complicated. In addition, a plurality of FIFO memories 51
.About.5n function independently of each other, the use efficiency of the storage area in each of the FIFO memories 51 to 5n is also reduced.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a first-in first-out storage device capable of multidirectional data transfer with a single memory.

[0008]

In order to achieve the above object, the means taken by the present invention is to provide a pointer for each port and manage the pointer by putting data in an associative memory. It is a thing.

Specifically, the means taken by the invention according to claim 1 firstly comprises a first input / output port, a second input / output port, and a randomly accessible memory cell. Then, a first write pointer and a second write pointer that generate a write pointer in response to a write request from the first input / output port and the second input / output port, and the first input / output port and the second write pointer. A first read pointer and a second read pointer that generate a read pointer in response to a read request from the input / output port are provided corresponding to the first input / output port and the second input / output port, respectively. . Further, one word has a direction data section for storing information indicating a transfer direction of data at the same address as the memory cell, and a valid bit section for storing information indicating whether data exists at the same address as the memory cell. And a pointer part whose initial value is set to the same value as the address, which matches the values given to the direction data part and the valid bit part, and in which the value of the write pointer has been written. There is provided an associative memory cell that searches for data whose value matches the value of the read pointer and outputs the address of the data as an address to the memory cell. In addition, when data is read from the memory cell, a vacant number setting counter that sets a vacant number in the pointer portion of the read address of the associative memory cell, and a vacant portion when data is written to the memory cell A free address search number counter holding a free number to be compared with the pointer part of the associative memory cell, and the output data from the memory cell is determined by the value from the direction data part of the associative memory cell. It is configured to include a selector that determines to which of the input / output port or the second input / output port the signal is output.

Further, the means taken by the invention according to claim 2 is the two input / output ports, the two write pointers, the two read pointers and the selector in the invention according to the above-mentioned claim 1. Instead, N input / output ports,
N write pointers that generate write pointers in response to write requests from N input / output ports, N read pointers that generate read pointers in response to read requests from N input / output ports, and the associative memory cell And a selector that determines to which input / output port the output data from the memory cell is output according to the value from the direction data section.

[0011]

According to the present invention, each write pointer and read pointer generate a value according to a write request signal and a read request signal from the input / output port, and the write request signal has the value associative memory cell. Send to. Then, the associative memory cell stores the value of the write pointer in the pointer part of the address where the contents of the empty address search number counter and the value of the pointer part match, and
Data is written in the direction data part and the valid bit part of the address. Further, the memory cell receives the input data sent through the input / output port, and the input data is written at the same address as the address at which the data was written in the associative memory cell.

On the other hand, the read pointer sends the value to the associative memory cell, the associative memory cell matches the received value and the value in the direction data section, and further, the valid bit section stores the valid data. Search for. Then, the associative memory cell sends to the memory cell the address at which the data satisfying the condition exists. After that, the memory cell sends the data to be output from the location of the received address to the selector,
The selector determines to which input / output port the data from the memory cell is sent. In addition, an empty number is written in the pointer portion by the empty number setting counter.

As a result, bidirectional data transfer is possible by managing the write pointer and the read pointer.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows the structure of a FIFO memory (first-in first-out storage device) according to the present invention. In this embodiment, the case where data is transferred from two ports will be described.

First, a write request signal A1 is externally supplied to the first write pointer A107 and the first read pointer A108 through the first input / output port A105.
01 and the read request signal A102 are given respectively. Also, the second write pointer B109 and the second read pointer B110 have a second input / output port B1.
A write request signal B103 and a read request signal B104 are externally supplied through 06. The respective values of the first write pointer A107 and the second write pointer B109 are the associative memory cell 1
It is connected to 16 input lines. In addition, the first read pointer A108 and the second read pointer B110
Each value of is also connected to the input line to the associative memory cell 116.

The associative memory cell 116 includes a direction data section 113, a valid bit section 114 and a pointer section 115.
Each word is composed of a direction data section 113, a valid bit section 114 and a pointer section 115, and the output line from the associative memory cell 116 is connected to the memory cell 117. The direction data unit 113 stores information indicating the transfer direction of data having the same address as the memory cell 117, and the valid bit unit 114 stores the information in the memory cell 117.
Information indicating whether or not data exists at the same address as 17 is stored, and the pointer unit 115 has an initial value set to the same value as the address. Then, the associative memory cell 11
6, the values from the read pointers A108 and B110 and the value of the pointer unit 115 match, the direction data given from the outside matches the value of the direction data unit 113, and the bit of the valid bit unit 114 Is searched, and the address of the corresponding data is output as an address to the memory cell 117.

The memory cell 117 has a first input / output port A.
The input data is received through 105 and the second input / output port B106, and the output is sent to the selector 118. The output line of the selector 118 is connected to the first input / output port A105 and the second input / output port B106.

The values of the vacant number setting counter 111 and vacant address search number counter 112 indicate the address of the associative memory cell 116. Then, the vacant number setting counter 111 is configured to set a vacant number in the pointer portion 115 of the read address of the associative memory cell 116 when the data is read from the memory cell 117, and the vacant address search number counter 112 is When data is written in the memory cell 116, the pointer unit 115 of the associative memory cell 116 is used to find a vacant portion.
Is configured to hold a free number to compare with.

Further, the selector 118 is the associative memory cell 1
The output data from the memory cell 117 is transferred to the first input / output port A 105 according to the value from the 16 direction data section 113.
Alternatively, it is configured to determine which one of the second input / output ports B106 is to be output. 119 and 120
Are input / output data A and B input / output to / from the input / output ports A105 and B106.

The operation of the FIFO memory configured as described above will be described in detail below.

First, it is assumed that the same value as the address is set as the initial value of the pointer section 115 of the associative memory cell 116, and the valid bit section 114 and the direction data section 113 are cleared to zero.

On the other hand, the first write pointer A107 and the first read pointer A108 generate values according to the write request signal A101 and the read request signal A102 sent from the outside through the first input / output port A105. . Further, when the write request signal A101 is input, the first write pointer A107 updates the value up to now (usually increments by +1) and sends the value to the associative memory cell 116.

Then, the associative memory cell 116 stores the received value in the pointer section 115, and the address to be stored is determined by the vacant address search number counter 112. That is, the free address search number counter 112
The value of the first write pointer A107 is stored in the pointer section 115 at the address where the contents of the above and the value of the pointer section 115 match.

At this time, the direction data section 11 of the address concerned
Data is also written in 3. These data may be given from the outside or generated internally.
In the case of this embodiment, the direction data is given from the outside. Further, the bits of the valid bit unit 114 are generated inside the associative memory cell 116. This pointer part 11
After storing in 5, the value of the free address search number counter 112 is incremented by +1.

At the same time that data is written in the associative memory cell 116, the first input / output port A is externally supplied.
The memory cell 117 receives the input data sent through the input port 105 and the second input / output port B106, and the input data is written at the same address where the data is written in the associative memory cell 116.

On the other hand, the first read pointer A108
When the read request signal A102 is input, the current value is updated (usually incremented by +1) and the value is sent to the associative memory cell 116. The associative memory cell 116 matches the received value, the direction data given from the outside matches the value of the direction data part 113, and further searches for the word in which the bit of the valid bit part 114 is valid. Then, the associative memory cell 116 sends the address where the data satisfying the condition exists to the memory cell 117. Then, the memory cell 117 sends the data to be output from the location of the received address to the selector 118.

When the content of the associative memory cell 116 matches the designated value, the bit of the valid bit section 114 is cleared and the value of the vacant number setting counter 111 is written in the pointer section 115. After this writing, the value of the vacant number setting counter 111 is incremented by +1. Further, the selector 118 determines which of the input / output ports A105 and B106 the data received from the memory cell 117 is to be sent to, based on the information from the direction data section 113.

In this way, the first input / output port A10
Input / output from 5 is performed by a first write pointer A107, a first read pointer A108, a vacant number setting counter 111 and a vacant address search number counter 112. The first write pointer A107 and the first read pointer A108 are handled according to the read pointer and write pointer of a normal direct-fall type FIFO memory.

On the other hand, in the same procedure, the second write pointer B109, the second read pointer B110, the vacant number setting counter 111 and the vacant address search number counter 112 are used for input / output from the second input / output port B106. Done. The second write pointer B109 and the second read pointer B110 are handled according to the read pointer and write pointer of a normal direct-fall type FIFO memory.

Although not shown in FIG. 1, the FIF
FULL or EM which is a signal indicating the state of the O memory to the outside
PTY and the like can be easily generated from the values of the vacant number setting counter 111 and the vacant address search number counter 112, and can be easily accessed from each of the input / output ports A105 and B106 without any problem.

In the above embodiment, the two input / output ports A105 and B106 and the two write pointers A10 are used.
7, B109 and two read pointers A108, B
110 is provided, but N input / output ports are provided, and N write pointers and N read pointers are provided corresponding to the N input / output ports, and the associative memory cell 116 has each Data may be written and an address may be output by a signal from the pointer. At that time, the selector 118 determines to which input / output port the data is to be sent based on the information in the direction data section 113 of the associative memory cell 116.

In summary, the essence of the present invention is that, in the direct-fall type FIFO memory, by using the associative memory 116 for management of the write and read pointers, a plurality of write and read operations for a single RAM (memory cell 117) are performed. The purpose is to manage the dashi pointer.

[0034]

As described above, according to the first-in first-out memory device of the present invention, the write pointer and the read pointer are provided corresponding to the input / output ports, and each pointer is managed by the associative memory cell. , Multi-directional data transfer can be performed by one memory cell. As a result, it is possible to easily configure a smaller-scale multi-directional data transfer system as compared with the conventional one, and to effectively use the storage area of the memory cell, and the present invention is extremely effective in practice.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a FIFO memory showing an embodiment of the present invention.

FIG. 2 shows a conventional example and is a configuration diagram of a bidirectional data transfer system using two FIFO memories.

FIG. 3 shows another conventional example and is a configuration diagram of a bidirectional data transfer system using N FIFO memories.

[Explanation of symbols]

105 I / O port A 106 I / O port B 107 write pointer A 108 read pointer A 109 write pointer B 110 Read pointer B 111 Empty number setting counter 112 Free address search number counter 113 direction data section 114 Valid bit part 115 Pointer part 116 Associative memory cell 117 memory cells 118 selector

Claims (2)

[Claims] 1. A first input / output port, a second input / output port, a randomly accessible memory cell, and a memory cell provided corresponding to the first input / output port and the second input / output port, respectively. A first write pointer and a second write pointer that generate a write pointer in response to a write request from the first input / output port and the second input / output port; and the first input / output port and the second input / output. A first read pointer and a second read pointer which are provided corresponding to the respective ports and generate a read pointer in response to a read request from the first input / output port and the second input / output port; A direction data section that stores information indicating the transfer direction of data at the same address as the memory cell and data exists at the same address as the memory cell. It consists of a valid bit portion for storing or not information that indicates how to, a pointer section which initial value is set to the same value as the address,
Searches for data that matches the values given to the direction data part and the valid bit part, respectively, and that the value of the write pointer matches the value of the pointer part and the value of the read pointer. An associative memory cell that outputs an address of data as an address to a memory cell, and an empty number setting counter that sets an empty number in a pointer part of the read address of the associative memory cell when data is read from the memory cell A vacant address search number counter holding a vacant number to be compared with a pointer part of the associative memory cell to find a vacant part when data is written to the memory cell; and a direction data part of the associative memory cell. The output data from the memory cell depends on the value from the first input / output port or the second input / output port. First-in-first-out storage device which is characterized in that it comprises a selector for determining whether to output. 2. N input / output ports, random-accessible memory cells, and N input / output ports are provided corresponding to each of the input / output ports, and write pointers are generated in response to write requests from the N input / output ports. N write pointers and N read pointers that are respectively provided corresponding to the N input / output ports and generate read pointers in response to read requests from the N input / output ports; A direction data part that stores information indicating the transfer direction of data at the same address as the memory cell, a valid bit part that stores information indicating whether data exists at the same address as the memory cell, and an initial value is the address. It consists of the pointer part where the same value is set,
Searches for data that matches the values given to the direction data part and the valid bit part, respectively, and that the value of the write pointer matches the value of the pointer part and the value of the read pointer. An associative memory cell that outputs an address of data as an address to a memory cell, and an empty number setting counter that sets an empty number in a pointer part of the read address of the associative memory cell when data is read from the memory cell A vacant address search number counter that holds a vacant number to be compared with the pointer part of the associative memory cell to find a vacant part when data is written to the memory cell; and a direction data part of the associative memory cell. Select the input / output port to which the output data from the memory cell is output according to the value from First-in-first-out storage device which is characterized in that it comprises a motor.