JPH05127694A - Digital signal processing system - Google Patents

Abstract

PURPOSE:To make the precision of acoustic signal editing operation higher by decreasing the pitch of an acoustic signal in a digital signal state at an optional rate. CONSTITUTION:This system has a constitution part 2 for the extension and interpolation of a sampling period, an oversampling filter 3, an oversampling filter 4 for interpolation signal generation, a selector 5, and an anti-aliasing filter 6. When the pitch of the acoustic signal is decreased in the digital signal state at the optional rate, namely, when an input signal is reproduced at a 1/J speed (J>1), (i)th data Xi among data stored in a buffer memory is read out repeatedly as many times as the integer part of the numeral J and linear interpolation with next data is performed for the decimal part of the numeral J; and this signal processing is repeated successively for the data. Then output data are obtained through the anti-aliasing filter 6 which removes return components in the generated data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing system capable of reducing the pitch of an acoustic signal in a digital signal state at an arbitrary ratio.

[0002]

2. Description of the Related Art It is well known that audio signals have been edited for various purposes, and analog signals that have been widely used as audio signal editing devices have been known. In addition to the morphological sound signal editing device, a digital signal morphological signal editing device is also used. The above-described audio signal editing device is, for example, a recording / reproducing function, fade-in, in order to edit the audio signal.
It is configured to have fade-out, cross-fade, edit / playback function based on edit list, and many other functions. When detecting an edit point, the acoustic signal is greatly expanded on the time axis. That is, it has been conventionally performed to reduce the pitch of the acoustic signal.

[0003]

Conventionally, as a means for lowering the pitch of the acoustic signal of the digital signal, there is a method of lowering the sampling frequency into an analog signal. After converting to an analog signal, an anti-alias filter is used to remove aliasing noise. This conventional method requires an analog-to-digital converter for resampling when returning to a digital signal having a sampling period after the pitch is reduced and before the pitch is reduced. Since the deterioration of the signal for returning to the signal is unavoidable, there is a drawback that high-precision conversion cannot be performed. The above-mentioned drawbacks can be solved by performing the signal processing in the state of the digital signal, but in the signal processing in the state of the digital signal, aliasing noise occurs if the data is simply zero-interpolated or hold-interpolated. Therefore, when the pitch is lowered with the digital signal as it is, a signal processing method capable of removing the aliasing noise well is required. In addition, the reduction of pitch is not limited to an integer ratio, and if it is possible to reduce the pitch at an arbitrary ratio, it will be meaningful for audio signal editing work. Mareta.

[0004]

The present invention reduces the input signal to 1 /
When playing at J times speed (where J is a number greater than 1),
The i-th data Xi in the stored data is
The value is repeatedly read as many times as the integer part of J, and the value of Xi (1-j) + X (i + 1) .j is generated, where j is the fractional part of J. The i + 1th data X (i + 1) of the read data is read repeatedly by the number of times of the integer part of J- (1-j), and J- (1-
j) Digital signal processing comprising means for repeatedly generating data for the decimal part and means for obtaining output data via an anti-aliasing filter for removing aliasing components in the generated data. Provide a scheme.

[0005]

When the pitch of the acoustic signal is lowered at an arbitrary ratio in the digital signal state, that is, when the input signal is reproduced at 1 / J times speed (where J is a number of 1 or more), it is stored in the buffer memory. The i-th data Xi in the stored data is read repeatedly by the number of times of the integer part of J, and the above-mentioned decimal part of J is sequentially subjected to signal processing such as linear interpolation with the next data. Apply data. Then, output data is obtained through an anti-aliasing filter that removes aliasing components in the generated data.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The specific contents of the digital signal processing system of the present invention will be described in detail below with reference to the accompanying drawings. 1 and 7 are block diagrams showing a schematic configuration of a digital signal processing system according to the present invention, FIG. 2 is a diagram showing an example of the configuration of a filter, FIG. 3 is a diagram illustrating filter coefficients of an odd-order FIR filter, and FIG. 4 is a block diagram when the digital signal processing method of the present invention is applied to an audio signal jog device,
FIG. 5 is an explanatory diagram of the expansion of the sampling section and the interpolation operation, and FIG. 6 is a diagram for explaining the characteristics of the oversampling filter. 1 and 7 showing the schematic configuration of the digital signal processing method of the present invention, 1 is an input terminal of a digital signal which is a target of signal processing for lowering the pitch, and 2 is an extension and interpolation of a sampling interval. A component unit, 3 is an oversampling filter, 4 is an oversampling filter for generating an interpolation signal, 5 is a selector,
Reference numeral 6 is an anti-alias filter, 7 is an output terminal of a digital signal whose pitch is lowered, and 4 in FIG.
Is an oversampling filter for generating an interpolation signal.

In the digital signal processing system of the present invention,
The digital signal that is the target of signal processing that can reduce the pitch of the acoustic signal to 1 / J (where J is a number of 1 or more) in the state of the digital signal is used for expanding the sampling interval and for interpolation. When supplied to the configuration unit 2, in the configuration unit 2 for extending and interpolating the sampling interval, as shown in FIG. 5, for the digital signal whose pitch is to be reduced, the integer part of J When the digital signal, which has been subjected to the above-described pitch reduction by the number of times, is repeatedly read from the storage device and arranged on the time axis at each sampling period, and the above-mentioned fractional part of J is j, X
A value of i (1-j) + X (i + 1) · j is generated, and then the i + 1th data X (i + 1) of the stored data is
Repeatedly read the number of times of the integer part of J- (1-j),
In the same manner as described above, the process for the decimal part of J- (1-j) is repeated to generate data. That is, the linear interpolation for the decimal part is {Xi + X (i + 1)}
/ 2 data is generated. The data generated as described above, that is, the sample value series, is transmitted through the terminal 8 to FIG.
(A) is supplied to the oversampling filter 3 and the interpolation signal generating oversampling filter 4 having the characteristics as shown by T1 in FIG. b) T
It is supplied to the anti-aliasing filter 6 having a characteristic as shown by e, and the aliasing filter 6 removes the aliasing distortion, so that the output terminal is indicated by circles and crosses in FIG. The pitch is 1 / J
Then, the digital signal which has been reduced to 1 is transmitted. The signal processing unit 16 in the jog device illustrated in FIG.
7 may be configured to include respective components such as the oversampling filter 3, the interpolation signal generating oversampling filter 4, the selector 5, and the anti-alias filter 6 shown in FIG. 1, or FIG. The oversampling filter 3, the selector 5, the anti-alias filter 6 and the like shown in FIG. The value of J described above is input to the control unit 15 by the operator from the operation unit 21 in FIG.

The above-mentioned configuration unit 2 for expanding and interpolating the sampling interval is the same as the configuration example of FIG. 4, which is shown as a block diagram when the digital signal processing method of the present invention is applied to an audio signal jog device. In the jog device, a digital signal read from a recording / reproducing unit (for example, a recording / reproducing unit configured by using a magneto-optical recording medium) 18 in which a digital signal targeted for pitch reduction is recorded is an interface with a digital signal. A buffer memory 17 which is provided via 20 and which is stored and then read is operated by a digital signal processor provided in association therewith in accordance with a control command from the control unit 15
The control of the operation of No. 7 and the interpolation operation are performed, and it is used as a component 2 for expanding and interpolating the sampling interval. In the jog device shown in FIG. 4 described above, the digital signal supplied to the input terminal 14 is supplied to the signal processing unit 16, and the digital signal supplied to the signal processing unit 16 is controlled by the control unit 15. The data is recorded on, for example, a magneto-optical recording medium provided in the recording / reproducing unit 18 via the buffer memory 17. The digital signal recorded in the recording / reproducing unit 18 is
The buffer memory 17 is read under the control of the control unit 15.
And is read from the buffer memory 17.

The buffer memory 17 reads the digital signal therefrom, and has the same sample value that is sequentially generated at every sampling period Tns of the digital signal which is the target of the pitch reduction of 1 / J. Is read and transmitted for each integral part of J, and a sample value for linear interpolation is generated by calculating {Xi + X (i + 1)} / 2 for the fractional part of J. The sample value sequence output from the buffer memory 17 that operates as the component 2 for expanding and interpolating the sampling interval has a characteristic similar to T1 shown in FIG. 6A from the terminal 8 in FIG. Is supplied to the oversampling filter 3 having the above and the oversampling filter 4 for generating the interpolation signal, and the data which is oversampled and converted to 1 / J times speed is output. FIG. 5 shows the data sequence generated by the oversampling filter 3 and the interpolation signal generation oversampling filter 4 when J = 3.5, the data generated by the oversampling filter 3 being circled, and the interpolation being performed. The data generated by the signal generation oversampling filter 4 is indicated by a cross.

That is, in the example shown in FIG. 5, J =
When signal processing of 3.5 (3.5 times speed) is performed,
Corresponding the i-th data Xi to the numerical value 3 of the integer part of J,
The buffer memory 1 is repeated every sampling period Tns of the digital signal targeted for the 1 / J pitch reduction.
It is read from 7 and sent out, and the fractional part of J is
A sample value of linear interpolation is generated by the calculation of {Xi + X (i + 1)} / 2. As a result, when J = 3.5, the sample value sequence output from the buffer memory 17 that operates as the configuration unit 2 for expanding and interpolating the sampling interval is shown in FIG.
Becomes a state as shown by the lengths of the sequential line segments shown in FIG. Is
The data generated by the oversampling filter 3 is shown by a circle in FIG. 5, and the data generated by the interpolation signal generating oversampling filter 4 is shown by a cross in FIG.

When the above-mentioned signal processing by the oversampling filter is performed in two stages so that an oversampling filter having a characteristic as illustrated in T2 of FIG. 6A is used, As the anti-alias filter 6, as shown in T3 of FIG. 6B, which has a cutoff region with a gentler slope than the slope of the cutoff region characteristic as illustrated in Te of FIG. 6B. It is possible to use one having a cut-off area characteristic. FIG. 2 shows a specific configuration example of the oversampling filter 3 and the interpolation signal generating oversampling filter 4 shown in FIG. 1, and the digital filter shown in FIG. The oversampling filter 3 is configured as an odd-order FIR filter, and the interpolation signal generation oversampling filter 4 is configured as an even-order FIR filter.
In FIG. 2, the component indicated by the symbol displaying T in the rectangular figure is the time delay, and the component indicated by the symbol displaying M in the triangular figure is the multiplier. Further, 10 and 11 are adders, 12 and 13 are rounders, 5 is a selector, 8 is an input terminal, and 9 is an output terminal. Further, h1, h2, ... Shown near the multiplier in each figure are filter coefficients. FIG. 3 exemplifies the filter coefficient of an odd-order FIR filter configuration.

The output Y1 of the oversampling filter 3 composed of an odd-order FIR filter (FIG. 2) and the output Y2 of an oversampling filter 4 composed of an even-order FIR filter for generating an interpolation signal (FIG. 2). Each of 2) is represented by Equation 1.

[Equation 1] Note that the embodiment of the digital signal processing system of the present invention shown in FIG. 7 has an oversampling filter 4 for generating an interpolation signal from the configuration of the digital signal processing system of the present invention shown in FIG. Although it is of the configuration mode removed, the case of the embodiment of the digital signal processing system of FIG. 1 in which 1 / J times speed reproduction at an arbitrary number J is already performed by the digital signal processing system shown in FIG. It goes without saying that it can be easily done as well.

[0013]

As is apparent from the above detailed description, the digital signal processing system of the present invention reduces the pitch of the acoustic signal by a desired ratio in the digital signal state, that is, the input signal is reduced to 1 / J times the speed (where J is a number equal to or greater than 1), the i-th data Xi in the data stored in the buffer memory is read repeatedly by the number of integral parts of J, For the decimal part, signal processing such as linear interpolation with the next data is performed on the sequential data. Since the output data is obtained through the anti-aliasing filter that removes the aliasing component in the generated data, the digital signal processing method of the present invention can change the pitch at an arbitrary number of double speeds. Since it can be satisfactorily performed in the state of a digital signal, according to the present invention, it becomes easy to significantly improve the function of, for example, a jog device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a digital signal processing system of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a filter.

FIG. 3 is a diagram exemplifying filter coefficients of odd-order FIR filters.

FIG. 4 is a block diagram when the digital signal processing method of the present invention is applied to an audio signal jog device.

FIG. 5 is an explanatory diagram of expansion of a sampling section and interpolation operation.

FIG. 6 is a diagram for explaining characteristics of an oversampling filter.

FIG. 7 is a block diagram showing a schematic configuration of a digital signal processing system of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal of the digital signal used as the object of the signal processing which reduces a pitch, 2 ... The component part for expansion and interpolation of a sampling area, 3 ... Oversampling filter,
4 ... Oversampling filter for generating interpolation signal, 5
... selector, 6 ... anti-alias filter, 7 ... output terminal of digital signal with reduced pitch, 15 ... control section,
16 ... Signal processing unit, 17 ... Buffer memory, 18 ... Recording / reproducing unit, 20 ... Interface, 21 ... Operation unit,

Claims (2)

[Claims] 1. An input signal is multiplied by 1 / J (where J is 1
In the case of reproducing with the above number), the i-th data Xi in the stored data is read repeatedly by the number of times of the integer part of J, and when the above-mentioned fractional part of J is j, Xi (1 -J) + X (i + 1) · j value is generated, and then the i + 1th data X (i + 1) of the stored data is the number of integer parts of J- (1-j). Reading is repeated, and J- (1-
j) Digital signal processing comprising means for repeatedly generating data for the decimal part and means for obtaining output data via an anti-aliasing filter for removing aliasing components in the generated data. method. 2. A buffer memory for writing data to a recording / reproducing apparatus using an external recording medium and reading data from the recording / reproducing apparatus using an external recording medium, and repeatedly reading out data to be signal-processed. The digital signal processing system according to claim 1, which is used as a storage means.