JPH05122196A - Scramble/descramble system - Google Patents

Abstract

PURPOSE:To reduce the size of circuitry and to make the decoding of data hand by performing the data identification of the scramble/descramble part using data and patterns different in the start and the end of data identification. CONSTITUTION:Scramble and descramble parts have the same constitution shown in a figure (b). The digital signal of the frame shown in a figure (a) is inputted to an I terminal 10. When a starting flag detection part 1 detects a start flag, a frame synchronizing circuit 4 sets a shift register in an (n)-order M system generation circuit 5 in the synchronizing position to a pattern other than all '0's. Then the circuit 5 and an EX-OR gate 6 perform scrambling and descrambling of data after the start flag. An abort/pattern detection part 2 detects abort/pattern, and a reset circuit 3 resets the circuit 5 to finish scrambling and descrambling. Thus, the size of circuitry can be reduced and the data is hardly decoded while corresponding to a single/packet format.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for scrambling / descramble data in digital signal transmission.

[0002]

2. Description of the Related Art FIG. 3 (c) is a block diagram of a conventional circuit that scrambles / descrambles a digital signal. The circuit shown in FIG. 3 (c) is a reset type scramble / descramble circuit, and scrambling / descramble of a digital signal is performed by the circuit shown in FIG. 3 (c). FIG. 3A is a single format frame configuration diagram of a digital signal, and FIG. 3B is a packet format frame configuration diagram of a digital signal. The frames shown in FIGS. 3 (a) and 3 (b) are the same as those shown in FIG. 3 (c).
Input to the I terminal 10, is scrambled / descrambled, and is output from the O terminal 20. Figure 3 (a) and Figure 3
The data part sandwiched between the start flag, end flag or start / end flag in the frame (b) is scrambled / descrambled by the circuit of FIG. 3 (c).
The start flag, end flag, and start / end flag have the same bit pattern.

Next, the operation will be described. First, the scramble start operation will be described. In Figure 3 (c),
The frames shown in FIGS. 3A and 3B are input to the I terminal 10, and the start flag detection unit 1 detects the start flag. Up to this point, the nth-order M-sequence generation circuit 5 has been in the reset state. After the detection of the start flag, the frame synchronization circuit 4 sets the shift register in the n-th order M sequence generation circuit 5 to a certain pattern other than all zeros at the synchronization position, and an exclusive OR (hereinafter referred to as EX-OR) gate 6 Then, the output of the n-th M-sequence generator circuit 5 and the data after the start flag are EX-ORed to scramble the data portion.

As described above, since the circuit shown in FIG. 3C performs scrambling / descramble, if the frame input to the I terminal 10 is a scrambled frame, O
A descrambled frame is output to the output of the terminal 20, and conversely, if the frame input to the I terminal 10 is a non-scrambled frame, a scrambled frame is output to the output of the O terminal 20.

Next, the scramble ending operation will be described. The end of scrambling is performed by detecting the end flag by the end flag detector 2 and resetting the n-th order M sequence generation circuit 5 by the reset circuit 3. Here, scrambling is data up to the end flag, and the circuit in FIG. 3C is configured to scramble the data between the start flag and the end flag.

[0006]

Conventional scrambling /
The descramble system is configured as described above, and the scramble / descramble processes the data part sandwiched between the start flag and the end flag. Therefore, the circuit of FIG. 3 (c) is used. As you can see, the end flag detection is
It must be performed before the EX-OR gate 6. At this time,
There is a possibility that the same pattern as the end flag exists in the scrambled data, and a circuit that distinguishes the original end flag from the same pattern as the end flag in the scrambled data is required, but this is realized. Therefore, the circuit scale becomes very large. Also, since the start flag and end flag are not scrambled, they are easy to decipher.

The present invention has been made in order to solve the above-mentioned problems of the conventional ones, and obtains a scramble / descramble system in which the circuit scale can be reduced and the scramble is hard to be decoded. The purpose is to

[0008]

A scramble / descramble system according to the present invention, when performing data scramble / descramble in digital signal transmission, starts data identification in a data scramble / descramble section. At the end, different data patterns are used.

Further, in the scramble / descramble system according to the present invention, when data scramble / descramble is performed in digital signal transmission, the identification of the data in the data scramble / descramble section is different at the start and end. The data pattern that indicates the start or end of data, which is performed in the data pattern and can be included between the start and end of the entire data to be scrambled / descrambled, is designed to be ignored.

[0010]

According to the present invention, when data scrambling / descramble is performed in digital signal transmission, the data size of the data scramble / descramble section is identified by different data patterns at the start and end, thereby making it possible to reduce the circuit scale. Can be made smaller, and scrambling is less likely to be deciphered.

Further, in the present invention, when data scramble / descramble is performed in digital signal transmission, the data of the data scramble / descramble part is identified by different data patterns at the start and end, and By ignoring the data pattern that indicates the start or end of data that may be included between the start and end of the entire data to be scrambled / descrambled, the frame format of the digital signal is a single format. However, the packet format can be used, the circuit scale can be reduced, and the scramble is difficult to be decoded.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 (b) is a block diagram showing a circuit for scrambling a digital signal according to an embodiment of the present invention.
The circuit shown in FIG. 1 (b) is a reset type scramble circuit. 1C is a block diagram showing a circuit for descrambling a digital signal according to an embodiment of the present invention. The circuit of FIG. 1 (c) is a reset type descramble circuit.

FIG. 1A shows a single signal of a digital signal.
It is a block diagram which shows one Example of a format structure, FIG.
The frame shown in (a) is input to the I terminal 10 of FIGS. 1 (b) and (c), scrambled and descrambled by the circuits of FIGS. 1 (b) and 1 (c), respectively, and the O terminal 20 outputs the frame. Is output. That is, the data after the start flag in FIG. 1A to the abort pattern are scrambled and descrambled by the circuits in FIGS. 1B and 1C, respectively.

Next, an embodiment of the present invention will be described. In FIG. 1 (b), the digital signal is input to the I terminal 10, is input to the start flag detection unit 1 and the abort pattern detection unit 2, and the respective outputs are input to the reset circuit 3 and the frame synchronization circuit 4. .. Then, the outputs of the reset circuit 3 and the frame synchronization circuit 4 are input to the n-th order M series circuit 5. Further, the random number output from the n-th order M series circuit 5 and the digital signal input to the I terminal 10 are subjected to the EX-OR operation in the EX-OR gate 6 and output to the O terminal 20.

Further, in FIG. 1 (c), the digital signal is input to the I terminal 10, and the EX-OR operation is executed by the random number output from the nth-order M series circuit 5 and the EX-OR gate 6.
It is output to the O terminal 20. The output of the EX-OR gate 6 is
It is input to the start flag detection unit 1 and the abort pattern detection unit 2, and the respective outputs are input to the reset circuit 3 and the frame synchronization circuit 4. Then, the outputs of the reset circuit 3 and the frame synchronization circuit 4 are input to the n-th order M series circuit 5.

Next, the operation of the scramble unit will be described. First, the scramble start operation will be described. In FIG. 1B, the frame shown in FIG.
The start flag is detected by the start flag detector 1. At this time, the nth-order M series circuit 5 is in the reset state. After the detection of the start flag, the frame synchronization circuit 4 sets the shift register in the n-th order M series circuit 5 at a synchronization position to a pattern other than all zeros, and scrambles the data after the start flag from the n-th order M series circuit 5. And EX-OR gate 6 performs an EX-OR operation.

Next, the scramble ending operation will be described. In FIG. 1B, when the scrambling ends, the abort pattern detection unit 2 detects an abort pattern from the digital signal input to the I terminal 10, and the reset circuit 3 resets the nth-order M series circuit 5. By doing. Here, the scramble is data up to the abort pattern, and the circuit in FIG. 1B is configured to scramble the data after the start flag to the abort pattern. Note that the abort pattern may be any pattern other than the flag.

Next, the operation of the descrambling unit will be described. First, the descrambling start operation will be described. In FIG. 1 (c), the frame shown in FIG. 1 (a) is input to the I terminal 10, and the start flag detection unit 1 detects the start flag. At this time, the nth-order M series circuit 5 is in the reset state. After the detection of the start flag, the frame synchronization circuit 4 sets the shift register in the n-th order M series circuit 5 at a synchronization position to a pattern other than all zeros, and descrambles the data after the start flag from the n-th order M series circuit. 5 and EX-
It is executed by performing an EX-OR operation in the OR gate 6.

Next, the descrambling end operation will be described. In FIG. 1 (c), the end of descrambling is to detect the abort pattern from the output of the EX-OR gate 6 by the abort pattern detection unit 2 and reset the nth-order M series circuit 5 by the reset circuit 3. By Here, the descramble is data up to the abort pattern, and the circuit of FIG. 1C is configured to descramble the data after the start flag to the abort pattern. Note that the abort pattern may be any pattern other than the flag.

In the above embodiment, I of the circuit shown in FIG.
The digital signal input to the terminal 10 can be input only in the single format frame shown in FIG. 1 (a), but in order to support the packet format frame shown in FIG. 2 (a). The circuit of 2 (b) is shown in Fig. 1 (b).
In addition to the above circuit, a start flag / abort / inter-pattern flag non-detection circuit 7 is added. The start flag / abort / inter-pattern flag desensitization circuit 7 desensitizes all the flags detected between the first start flag and the abort pattern, thereby desensitizing the flags in the meantime. By configuring
The circuit in Figure 2 (b) is a single format frame,
It is possible to support any of packet formats and frames.

[0021]

As described above, according to the scramble / descramble system according to the present invention, when the data scramble / descramble is performed in the digital signal transmission, the data of the data scramble / descramble part is Since the identification is performed with different data patterns at the start and the end, the circuit scale can be reduced and the scramble becomes difficult to be decoded.

Further, according to the scramble / descramble system according to the present invention, the identification of the data in the data scramble / descramble part is started and ended when the data scramble / descramble is performed in the digital signal transmission. The data pattern that indicates the start or end of the data, which may be included between the start and end of the entire data to be scrambled / descrambled, is ignored. The frame format can be compatible with both the single format and the packet format, the circuit scale can be reduced, and the scramble is difficult to be decoded.

[Brief description of drawings]

FIG. 1 is a diagram showing a scramble / descramble system according to an embodiment of the present invention, and FIG. 1 (a) is a frame configuration diagram showing an example of the configuration of a single format frame used in this system. 1 (b), Fig. 1
FIG. 1C is a block diagram showing a configuration example of a circuit for processing the frame of FIG. 1A.

FIG. 2 is a diagram showing a scramble / descramble system according to another embodiment of the present invention, and FIG. 2 (a) is a frame configuration diagram showing one configuration example of a packet format frame used in this system; 2 (b) and 2 (c) are block diagrams showing a configuration example of a circuit for processing the frame of FIG. 2 (a).

3 is a diagram showing a conventional scramble / descramble system, FIG. 3 (a) is a frame configuration diagram of a single format frame used in this system, and FIG. 3 (b) is used in this system. Frame format diagram of packet format frame according to FIG.
FIG. 3C is a block diagram showing a configuration of a circuit for processing the frames of FIGS. 3A and 3B.

[Explanation of symbols]

1 Start Flag Detecting Section 2 Abort / Pattern Detecting Section 3 Reset Circuit 4 Frame Synchronizing Circuit 5 nth-Order M Sequence Generating Circuit 6 EX-OR Gate 7 Start Flag / Abort Pattern Inter-Flag Non-Detecting Circuit 10 Digital Signal Input Terminal 20 Digital Signal Output terminal F flag

Claims (2)

[Claims] 1. In digital signal transmission, when data is scrambled / descrambled, the data to be scrambled / descrambled is identified by different data patterns at the start and end of the data. Scramble / descramble system. 2. In digital signal transmission, when data is scrambled / descrambled, the data to be scrambled / descrambled is identified by different data patterns at the start and end of the data, and the scramble / descramble is also performed. A scramble / descramble system characterized by ignoring a data pattern indicating the start or end of data, which may be included between the start and end of the entire data to be processed.