JPH05122194A - Spread spectrum communication equipment - Google Patents

Abstract

PURPOSE:To speedily perform the initial synchronizing matching by developing a diffusion code on the frequency axis using discrete data decided by each digit value of the diffusion code allocated with the phase of each frequency component or the displacement from the center frequency previously stored in a memory. CONSTITUTION:A clock source circuit 11 and a clock reproduction circuit 113 generate addresses by supplying an address clock having frequency more than double that of the signal data to address generation circuits 12 and 115. Memories 13 and 116 store discrete data, decided by each digit value, of diffusion codes allocated with the displacement from the center frequency of each frequency component to output the data. A transmitter-receiver is constructed, through a transmission line 19, of D/A converters 14 and 17, local oscillators 17 and 120, demodulator 114, a mixer, LPF, and BPF or the like. Thus, diffusion codes are developed on the frequency axis using the discrete data, and the initial synchronizing matching can speedily be performed without a synchronization acquisition circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication device for converting information into a signal having a very large bandwidth compared to an information band when transmitting information by wire or wirelessly.

[0002]

2. Description of the Related Art A spread spectrum communication system is a system for transmitting as a signal having an extremely wide bandwidth compared with information data, but there have been roughly two systems to realize this.

The first method is direct diffusion (Direct Sequenc).
e: DS) method. This is to multiply a digitized baseband signal with a spreading code such as a high-speed pseudo noise code to generate a baseband signal having an extremely wide bandwidth as compared with the original data, and further phase shift keying (PSK), Frequency shift keying (FS
K) or the like is modulated, converted into an RF (radio frequency) signal and transmitted. On the other hand, on the receiving side, the same spreading code as that on the transmitting side is used to perform despreading that correlates with the received signal to demodulate the original data.

The second method is frequency hopping (Freque).
In a method called ncy hopping (FH) method, the frequency of a carrier wave modulated by a baseband signal is switched and transmitted at a time interval of 1 bit of data, or 1 / integer thereof, or an integer multiple thereof according to a spread code. On the receiving side, the same spreading code as that on the transmitting side is used to perform a correlation operation of tuning the carrier wave on the receiver side to the transmitting side to perform despreading and demodulate the original data.

In these systems, the spreading code needs to be accurately synchronized on the transmitting side and the receiving side in order to obtain a correct correlation on the receiving side. A synchronization circuit that realizes this has conventionally used a synchronization method called a sliding correlation loop.

FIG. 4 is a block diagram showing a sliding correlation loop for the DS method.

In the figure, the received spread signal is a mixer 401.
Is multiplied by the spreading code sequence generated from the spreading code generator 406. The output of the mixer 401 is a bandpass filter (BPF) having a bandwidth corresponding to the original data.
Input to 402. Further, the output of the BPF 402 is subjected to envelope detection by the detection circuit 403 and smoothed by the low pass filter (LPF) 404.

If autocorrelation is obtained, the mixer 40
The despread signal is obtained at the output of 1, and the BPF 402
And is subjected to envelope detection in the detection circuit 403.
Further, it is smoothed by the LPF 404 to obtain a DC level.

On the other hand, when the autocorrelation cannot be obtained, the despread signal cannot be obtained at the output of the mixer 401, and most of the received spread signal power is blocked by the BPF 402.
Then, the envelope is detected in the detection circuit 403 and LPF4 is detected.
Although it is smoothed at 04, the obtained DC level is sufficiently smaller than when the autocorrelation is obtained.

The DC level output of LPF 404 is provided to a voltage controlled oscillator (VCO) 405. If the autocorrelation cannot be obtained, the DC level of the output of the LPF 404 is sufficiently small, so that the VCO 405 obtains an output of a frequency slightly different from the frequency of the spread code included in the received spread signal. This is supplied to the spread code generator 406 as a clock. Since the clock speed of the spread code generated by the spread code generator 406 is slightly different from the clock speed of the received spread signal, the phases of the two will gradually shift. As a result, by the time the phases of both are shifted by one synchronization of the spread code, synchronization is achieved and autocorrelation is obtained. Then, the DC output level of the LPF 404 rises and V
Lock the oscillation frequency of CO405 to the current frequency,
Synchronization between the received spreading code and the spreading code generated by the spreading code generator 406 is obtained. The synchronization acquisition time of this system generally becomes extremely long because the phase of the spreading code on the receiving side is gradually shifted.

FIG. 5 is a block diagram showing a sliding correlation loop for the FH method.

FIG. 5 is a block diagram of the frequency synthesizer 5 shown in FIG.
It has the same configuration except that 07 is added. The entire operation is similar to that of the DS method.

[0013]

As described above, in the conventional spread spectrum communication system, since the spread code is changed on the time axis, the spread code synchronization acquisition circuit is necessary, and the synchronization acquisition is required. There was a drawback that the time required was extremely long.

The present invention eliminates the need for a spread code synchronization acquisition circuit that changes the spread code on the time axis by expanding the spread code on the frequency axis, and can reduce the time required for synchronization acquisition. The purpose is to provide.

[0015]

According to the present invention, there is provided an address clock having an integral multiple of an information transmission rate, a clock means for generating a data clock having the same rate as the information transmission rate, and the data clock. Address generating means for generating an address signal from the input data and the address clock, and a plurality of frequencies that are an integral multiple of the data clock and are 1/2 or less of the address clock by the address signal output from the address generating means. A memory means having a component, which outputs discrete data in which the displacement or phase of each frequency component from the center frequency is determined by the value of each digit of the pre-assigned spreading code;
D for outputting a discrete analog signal according to the discrete data
/ A conversion means, low-pass filtering means for anti-aliasing the discrete analog signal, mixer means and local oscillating means for converting a baseband analog signal output from the low-pass filtering means into a transmission band signal, Band filtering means for taking out only the transmission band signal from the output of the mixer means and sending it to the transmission path.

The present invention further comprises band-pass filter means for extracting only the transmission band signal from the signal received from the transmission line, and mixer means for converting the transmission band signal into an intermediate frequency signal.
Band-pass filtering means for extracting only a predetermined frequency band signal from the intermediate frequency signal, clock regenerating means for regenerating a data clock from the output of the band-pass filtering means, and generating an address clock from the data clock, Demodulation means for reproducing data from the output of the band filtering means for extracting only the data clock and the predetermined frequency band signal, address generation means for generating an address signal from the address clock, and the data clock of the data clock by the address signal. A discrete number having a plurality of frequency components equal to or less than 1/2 of the address clock, which is an integral multiple, and the displacement or phase of each frequency component from the center frequency is determined by the value of each digit of the pre-assigned spreading code. Memory means for outputting data, and inputting the discrete data and outputting a discrete analog signal according to the data D / A conversion means, low-pass filtering means for anti-aliasing the discrete analog signal, mixer means for converting the baseband analog signal output from the low-pass filtering means into a predetermined frequency band signal, and local It is characterized by comprising an oscillating means and a band-pass filtering means for extracting only the predetermined frequency band signal from the output of the mixer means and outputting it to the mixer means for converting it into an intermediate frequency signal.

With the above configuration, the spreading code can be expanded on the frequency axis, and multiple access can be performed without using a circuit for changing the spreading code on the time axis to acquire synchronization.

[0018]

1 is a block diagram showing the configuration of a first embodiment of the present invention.

In the figure, a clock source 11 is a memory 1
A frequency that is at least twice the maximum frequency of the signal data stored in 3 is output to the address generation circuit 12 as an address clock, and a frequency obtained by appropriately dividing this frequency is supplied to the information source as a data clock.

The address generation circuit 12 includes a clock source 11
The address is generated from the address clock and the data input from and is output to the memory 13.

The memory 13 is a memory for outputting prestored signal data based on the address signal input from the address generation circuit 12.

The D / A converter 14 D / A converts the output of the memory 13 and is a low-pass filter (LPF).
Reference numeral 15 is for anti-aliasing the output of the D / A converter 14.

The mixer 16 and the local oscillator 17 are LP
The baseband signal output from F15 is converted into a transmission band, and the bandpass filter (BPF) 18 removes signals outside the transmission band.

The BPF 110 removes out-of-band signals mixed in the transmission path 19, and the BPF 112 removes signals other than a predetermined data bandwidth from the output of the mixer 111.

The clock recovery circuit 113 is provided with the BPF 112.
The data clock and the address clock are reproduced from the output of the B.sub.2, and the demodulator 114 reproduces the data from the output of the BPF 112 and the output of the clock reproduction circuit 113.

The address generation circuit 115 is for generating an address from the address clock from the clock recovery circuit 113, and the memory 116 is for the address generation circuit 1.
The pre-stored signal data is output on the basis of the address signal input from 15.

The D / A converter 117 has a memory 116.
The output of is converted from digital to analog, and the LPF 118
The output of the D / A converter 117 is anti-aliased. Mixer 119 and local oscillator 120
Is for converting the baseband signal output from the LPF 118 into a predetermined frequency band signal.
Is to remove signals other than the predetermined frequency band signal.

Next, prior to the description of the operation, the data stored in the memory 13 and the memory 116 will be described in detail.

The signal in the memory 116 is composed of n frequency components. Then, for each frequency component, reception spread codes C0 ', C1', C2 ', ... Cn-
1 'is given, and each has a value of 0 or 1.

Assuming that the data clock frequency is fd, the respective frequency components are (4p + 2C0 ') fd, {4 (p + 1) + 2C1'}.
fd, {4 (p + 2) + 2C2 '} fd, ... {4 (p
+ N-1) + 2Cn-1 '} fd. However, p is a positive integer here.

The address clock is mfd (m ≧
8 (p + n-1) +1). Then, the data in the memory 116 is as shown in FIG.

On the other hand, in the memory 13, depending on the data, P
The most significant bit of the address is assigned to the data in order to perform SK modulation. That is, the data in the memory 13 is as shown in FIG. In addition, C0 in FIG.
C1, C2, ... Cn-1 are transmission spread codes, and have a value of 0 or 1, respectively.

FIG. 8 is a schematic diagram showing a list of arithmetic expressions used in the description of this embodiment.

In the configuration as described above, the output of the memory 13 passes through the D / A converter 14 and the LPF 15 and becomes an analog signal shown in the equation 1 of FIG.

FIG. 2 is a waveform diagram showing the waveform of this analog signal.

This analog signal is frequency-converted by the mixer 16, only the transmission band signal is extracted by the BPF 18, and sent out to the transmission line. Set the frequency of the local oscillator 17 to fc
Then, the transmitted signal is as shown in Equation 2 in FIG.

On the receiving side, the BPF 110 removes unnecessary signals mixed in the transmission path and inputs them to the mixer 111. The output of the LPF 118 has the form of Equation 3 in FIG.
A predetermined frequency band signal is obtained by passing through the BPF 121 via the mixer 119. Local oscillator 120
When the frequency of is fc ′, the output of the BPF 121 is as shown in FIG.
Equation 4 is obtained. Therefore, the outlet of the mixer 111 is fc-
If fc ′ = f _IF , then Equation 5 in FIG. 8 is obtained.

If the BPF 112 has a center frequency f _IF and a bandwidth of 2 fd, the signal passing through the BPF 112 is
Equation 6 in FIG. 8 is obtained. That is, if the spreading code on the transmitting side and the spreading code on the receiving side are the same, Ci−Cj ′ = 0, and all the signals that have passed through the BPF 112 are added in phase, so the signal voltage becomes n times.

On the other hand, the noise voltages are all uncorrelated assuming additive white Gaussian noise, so that the average addition voltage is only n ^1/2 times the maximum, so the BPF 112
The signal-to-noise power ratio (S / N) after passing is n ² / (n
^1/2 ) ² = n times.

When the spreading code {Ci} is configured to be selected from a set having a small cross-correlation, a receiver using a different code does not multiply the signal after passing through the BPF 112 by n times, so that a signal sufficient for demodulation is obtained. You will not get power.
Therefore, multiple access by code division becomes possible.

From the output of the BPF 112, the data clock and the address clock are reproduced by the clock regenerating circuit 113, and are supplied to the demodulator 114 and the address generating circuit 115, respectively. The demodulator 114 performs PSK demodulation with the data clock and the output of the BPF 112.

Next, a second embodiment of the present invention will be described.

The second embodiment has the same configuration as that of the first embodiment except for the data stored in the memory 13.
Therefore, the data stored in the memory 13 will be described here.

In the first embodiment, since the data stored in the memory 13 is a PSK modulated wave whose band is not limited for each frequency slot, the out-of-band signal component interferes with other frequency slots. Acts as
There is an inconvenience that adversely affects demodulation performance.

Therefore, in the second embodiment, in order to suppress the out-of-band component of the signal corresponding to each frequency slot, the envelope of the signal corresponding to each frequency slot of the data stored in the memory 13 in the first embodiment is set. The waveform-shaped data is used as the data stored in the memory 13. An example of using the weighting of the amplitude level as an example of the band limitation is schematically shown in FIG. This makes it possible to obtain better demodulation performance as compared with the first embodiment.

Next, a third embodiment of the present invention will be described.

The third embodiment is the same as the first embodiment except that the data stored in the memory 13 and the memory 116 is replaced, and the other structure is the same as that of the first embodiment. Therefore, first, the memory 13 and the memory 1
The data stored in 16 will be described in detail.

The signal in the memory 116 is composed of n frequency components. When the data clock frequency is fd, the respective frequency components are 2pfd, 2 (p + 1) fd, 2 (p + 2) fd, ...
2 (p + n-1) fd. However, p is a positive integer here.

The address clock is mfd (m ≧
8 (p + n-1) +1). Furthermore, for each frequency component, the reception spreading codes C0 ', C1', C2 are previously set.
', ... Cn-1' is given, and each has a value of 0 or 1.

The data in the memory 116 is shown in FIG.
Is shown in.

On the other hand, in the memory 13, depending on the data, P
The most significant bit of the address is assigned to the data in order to perform SK modulation. That is, the data in the memory 13 is as shown in FIG. Note that C in FIG.
0, C1, C2, ... Cn-1 are transmission spread codes,
Each has a value of 0 or 1.

FIG. 11 is a schematic diagram showing a list of arithmetic expressions used in the description of this embodiment.

In the present embodiment, the output of the memory 13 is
It passes through the D / A converter 14 and the LPF 15 and becomes an analog signal shown in Expression 11 in FIG.

FIG. 12 is a waveform diagram showing the waveform of this analog signal.

This analog signal is frequency-converted by the mixer 16, only the transmission band signal is extracted by the BPF 18 and sent out to the transmission line. Set the frequency of the local oscillator 17 to fc
Then, the transmitted signal is as shown in Expression 12 of FIG.

On the receiving side, the BPF 110 removes unnecessary signals mixed in the transmission path and inputs them to the mixer 111. The output of the LPF 118 has the form of Expression 13 in FIG. 11, and passes through the BPF 121 via the mixer 119 to become a predetermined frequency band signal. Local oscillator 1
When the frequency of 20 is fc ', the output of the BPF 121 is Equation 14 in FIG. Therefore, assuming that fc−fc ′ = f _IF , the outlet of the mixer 111 is as shown in Expression 15 of FIG. 11.

If the BPF 112 has a center frequency f _IF and a bandwidth of 2 fd, the signal passing through the BPF 112 is
Equation 16 in FIG. 11 is obtained. That is, if the spreading code on the transmitting side and the spreading code on the receiving side are the same, Ci−Cj ′ = 1
Since all the signals that have passed through the BPF 112 are added in phase, the signal voltage becomes n times.

On the other hand, assuming that additive white Gaussian noise is used, the noise voltages are all uncorrelated, so that the average addition voltage is only n ^1/2 times as large as possible.
The signal-to-noise power ratio (S / N) after passing is n ² / (n
^1/2 ) ² = n times.

When the spreading code {Ci} is configured to be selected from a set having a small cross-correlation, a receiver using a different code does not have a signal n times after passing through the BPF 112, so that a signal sufficient for demodulation is obtained. You will not get power.
Therefore, multiple access by code division becomes possible.

From the output of the BPF 112, the data clock and the address clock are reproduced by the clock regenerating circuit 113, and are supplied to the demodulator 114 and the address generating circuit 115, respectively. The demodulator 114 performs PSK demodulation with the data clock and the output of the BPF 112.

Next, a fourth embodiment of the present invention will be described.

The fourth embodiment has the same structure as that of the third embodiment except for the data stored in the memory 13.
Therefore, the data stored in the memory 13 will be described here.

In the third embodiment, since the data stored in the memory 13 is a PSK modulated wave that is not band-limited for each frequency slot, the out-of-band signal component interferes with other frequency slots. Acts as
There is an inconvenience that adversely affects demodulation performance.

Therefore, in the fourth embodiment, like the second embodiment, in order to suppress the out-of-band component of the signal corresponding to each frequency slot, each frequency slot of the data stored in the memory 13 in the third embodiment is suppressed. The data stored in the memory 13 is obtained by performing waveform shaping on the envelope of the signal corresponding to. FIG. 13 schematically shows an example in which weighting of the amplitude level is used as an example of the band limitation. As a result, it becomes possible to obtain better demodulation performance as compared with the third embodiment.

[0065]

As described above, according to the present invention,
By expanding the spread code on the frequency axis, it is possible to eliminate the spread code synchronization acquisition circuit and eliminate the time overhead at the time of initial information demodulation for spread code synchronization.
Initial synchronization can be performed at high speed, and there is an effect that spread spectrum communication with a wide range of applications can be realized.

Further, according to the present invention, since the code synchronization between the transmitting side and the receiving side is not lost during communication, there is no need to resynchronize, and highly reliable communication can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a waveform diagram showing a waveform of an analog signal based on data stored in a memory in the first embodiment.

FIG. 3 is a waveform diagram showing a waveform of an analog signal based on data stored in a memory according to the second embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional technique.

FIG. 5 is a block diagram showing another example of the conventional technique.

FIG. 6 is a schematic diagram showing the contents of memory data in the first embodiment.

FIG. 7 is a schematic diagram showing contents of memory data in the first embodiment.

FIG. 8 is a schematic diagram showing a list of arithmetic expressions used in the description of the first embodiment.

FIG. 9 is a schematic diagram showing the contents of memory data in the third embodiment of the present invention.

FIG. 10 is a schematic diagram showing the contents of memory data in the third embodiment.

FIG. 11 is a schematic diagram showing a list of arithmetic expressions used in the description of the third embodiment.

FIG. 12 is a waveform diagram showing a waveform of an analog signal based on data stored in a memory according to the third embodiment.

FIG. 13 is a waveform diagram showing a waveform of an analog signal based on data stored in a memory according to a fourth embodiment of the present invention.

[Explanation of symbols]

 11 ... Clock source, 12 ... Address generation circuit, 13, 116 ... Memory, 14, 117 ... D / A converter, 15, 118 ... LPF, 16, 111, 119 ... Mixer, 17, 120 ... Local oscillator, 18, 110 , 112, 121 ... BPF, 113 ... Clock recovery circuit, 114 ... Demodulator, 115 ... Address generation circuit.

Claims (4)

[Claims] 1. A clock means for generating an address clock having a speed which is an integer multiple of the information transmission speed and a data clock having the same speed as the information transmission speed; data inputted by the data clock and the address clock. Address generating means for generating an address signal by and;
By the address signal output from the address generation means, an integer multiple of the data clock,
Memory means for outputting a discrete data having a plurality of frequency components of 2 or less, the displacement of each frequency component from the center frequency being determined by the value of each digit of the spreading code assigned in advance; D / A conversion means for outputting a corresponding discrete analog signal; low-pass filtering means for anti-aliasing the discrete analog signal; and baseband analog signal output from the low-pass filtering means for conversion to a transmission band signal A spread spectrum communication device comprising: a mixer means and a local oscillating means; and a band-pass filter means for extracting only a transmission band signal from the output of the mixer means and sending it to a transmission line. 2. Band-pass filtering means for extracting only a transmission band signal from a signal received from a transmission line; mixer means for converting the transmission band signal into an intermediate frequency signal; and a predetermined frequency band signal in the intermediate frequency signal. And a clock regenerating unit for regenerating a data clock from the output of the band filtering unit and generating an address clock from the data clock; only the data clock and the predetermined frequency band signal; Demodulation means for reproducing data from the output of the band-pass filtering means for extraction; address generation means for generating an address signal from the address clock; integer multiple of the data clock by the address signal, and 1/2 of the address clock Each spread code has a plurality of frequency components below, and the displacement of each frequency component from the center frequency is assigned to each spread code in advance. Memory means for outputting discrete data determined by the value of the digit; D / A converting means for inputting the discrete data and outputting a discrete analog signal according to the data; anti-aliasing for the discrete analog signal Low-pass filtering means; mixer means and local oscillating means for converting the baseband analog signal output from the low-pass filtering means into a predetermined frequency band signal; and the predetermined frequency band from the output of the mixer means. A spread spectrum communication device, comprising: band-pass filtering means for extracting only a signal and outputting it to a mixer means for converting it into an intermediate frequency signal. 3. An address clock having a speed which is an integral multiple of the information transmission speed, and clock means for generating a data clock having the same speed as the information transmission speed; data inputted by the data clock and the address clock. Address generating means for generating an address signal by and;
By the address signal output from the address generation means, an integer multiple of the data clock,
Memory means for outputting discrete data having a plurality of frequency components of 2 or less and the phase of each frequency component being determined by the value of each digit of the spreading code assigned in advance; and a discrete analog corresponding to the discrete data. D / that outputs the signal
A conversion means; low-pass filtering means for anti-aliasing the discrete analog signal; mixer means and local oscillating means for converting a baseband analog signal output from the low-pass filtering means into a transmission band signal; A spread spectrum communication device comprising: band-pass filtering means for extracting only a transmission band signal from the output of the mixer means and sending it to a transmission line. 4. Band-pass filtering means for extracting only a transmission band signal from a signal received from a transmission line; mixer means for converting the transmission band signal into an intermediate frequency signal; and a predetermined frequency band signal in the intermediate frequency signal. And a clock regenerating unit for regenerating a data clock from the output of the band filtering unit and generating an address clock from the data clock; only the data clock and the predetermined frequency band signal; Demodulation means for reproducing data from the output of the band-pass filtering means for extraction; address generation means for generating an address signal from the address clock; integer multiple of the data clock by the address signal, and 1/2 of the address clock It has the following multiple frequency components, and the phase of each frequency component is determined by the value of each digit of the spread code that is assigned in advance. Memory means for outputting fixed discrete data; D / A converting means for inputting the discrete data and outputting a discrete analog signal corresponding to the data; low-pass filtering for anti-aliasing the discrete analog signal Means; a mixer means and a local oscillating means for converting the baseband analog signal output from the low-pass filtering means into a predetermined frequency band signal; and only the predetermined frequency band signal from the output of the mixer means, Band-pass filtering means for outputting to a mixer means for converting into an intermediate frequency signal;
A spread spectrum communication device having: