JPH05122024A - Dynamic latch circuit - Google Patents

Abstract

PURPOSE:To prevent erroneous operations caused by the reduction of threshold voltage by irradiation of radioactive rays and the occurrence of leak current, in a dynamic latch circuit which is used under ionizing radiations circumstances. CONSTITUTION:Circuits 6, 7 holding an input terminal 18 and a clock terminal 19 of a dynamic latch circuit in a LOW state at a standby time are constituted. As gate terminals 13, 14 of a n type MOS transistor which is used for a clock gate composing a dynamic latch circuit are always held in a LOW state when the dynamic latch becomes the standby state, the reduction of the threshold voltage of the n form MOS transistor by irradiation of ionizing radioactive rays and the occurrence of leak current between source drain can be prevented.

Description

Detailed Description of the Invention

[0001]

The present invention relates to space, nuclear reactors, accelerators,
The present invention relates to a dynamic latch circuit that constitutes a radiation resistant semiconductor integrated circuit used in a radiation environment such as medical care.

[0002]

2. Description of the Related Art Regarding semiconductor devices used in a radiation environment, I.E.E., Transaction on Nuclear Science N.S. 36.
(1989) pages 2252 to 2257 (IEEE Tra
nsaction on Nuclear Science Vol.NS-36 pp.2252-2257,
1989). Large-scale integrated circuits (LSIs) used in a radiation environment such as space receive a large amount of radiation and generate leakage current inside and between semiconductor elements. The latch circuit was not used.

However, it is expected that a large amount of semiconductor elements for signal processing will be used in artificial satellites and future unmanned space stations, and it has become necessary to develop LSIs that operate at high speed. For this reason, it has become necessary to use a dynamic latch circuit characterized by high-speed operation.

[0004]

In the conventional circuit configuration method, for example, as shown in FIG. 2, the dynamic latch circuit 1 is formed by connecting two logic circuits 4 and 5. That is, in the dynamic latch circuit 1, the output terminal of the clocked gate 2 is connected to the input terminal of the inverter 3, and the clocked gate 2 has two p-channel type (hereinafter referred to as p-type) MOS transistors 11 and 12.
And two n-channel type (hereinafter referred to as n-type) MOS transistors 13 and 14. This p-type M
The gate terminals of the OS transistor 11 and the n-type MOS transistor 14 are connected to each other and serve as a data input terminal 18. The gate terminal of the p-type MOS transistor 12 is connected to the input terminal 20 for the inverted clock signal CLKN, and the gate terminal of the n-type MOS transistor 13 is the input terminal 19 for the clock signal CLK. Further, the drain terminal of the p-type MOS transistor 12 and the drain terminal of the n-type MOS transistor 13 are connected to each other and serve as an output of the clocked gate 2.

Therefore, in the dynamic latch circuit 1, the data is held by using the input capacitance of the inverter 3 when the clock CLK is in the LOW state. Therefore,
When this circuit is irradiated with ionizing radiation, the n-type MOS transistors 13 and 14 forming the clocked gate 2 are formed.
At this point, a decrease in the threshold voltage and a leak current from the drain terminal to the source terminal are observed, and the charge accumulated in the input capacitance of the inverter 3 disappears due to the leak current.
There is a problem that the circuit malfunctions.

Therefore, it is an object of the present invention to provide a dynamic latch circuit which can suppress the deterioration of a MOS transistor even when irradiated with radiation and can enhance the reliability of operation under a radiation environment. It is in.

[0007]

To achieve the above object, according to one embodiment (FIG. 1) of the present invention, a data input terminal (18) and a clock input terminal (19) and a clock are inverted. The drain terminal of the first n-type MOS transistor (6) is connected to the data input terminal of the dynamic latch circuit (1) having the input terminal (20) for the signal CLKN, and the first n-type MOS transistor (6) is connected. )
The gate terminal of the dynamic latch circuit (1) is connected to the reset signal (RES) and is connected to the clock input terminal (19).
The drain terminal of the second n-type MOS transistor (7) is connected to the gate terminal of 3), and the gate terminal of the second n-type MOS transistor (7) is connected to the reset signal (RE
S) is connected. According to another embodiment (FIG. 3) of the present invention, the voltage source of the first logic circuit 4 connected to the input terminal of the dynamic latch circuit is connected to the first p-type MOS transistor (17). The dynamic type connected to the drain terminal, the gate terminal of the first p-type MOS transistor (17) to the reset signal (RES), and connected to the clock input terminal of the dynamic type latch circuit (1). L-type M of the latch circuit (1)
The output of the inverter (21) whose supply voltage is controlled by the p-type MOS transistor (9) is connected to the gate terminal of the OS transistor (13), and the gate terminal of the p-type MOS transistor (9) is reset signal (RES). And a signal (CLKN) having a phase opposite to that of the clock terminal is connected to the input terminal of the inverter (21).

[0008]

When the conventional dynamic latch circuit is irradiated with the ionizing radiation, the decrease of the threshold voltage and the leakage current path between the drain and the source in the n-type MOS transistor forming the dynamic latch circuit are caused. Occurrence is seen. These deteriorations are caused by irradiation with ionizing radiation.
It becomes remarkable when a positive voltage is applied to the gate electrode of the MOS transistor. Therefore, in the conventional dynamic type latch circuit (FIG. 2), the clock input terminal 19 of the dynamic type latch circuit and the signal C obtained by inverting the clock are used.
No clock is input to the input terminal 20 for LKN,
The dynamic latch circuit stops and the data input terminal 1
When 8 or the clock input terminal 19 is in the HIGH state, the deterioration of the n-type MOS transistors 13 and 14 due to the radiation becomes maximum. After that, even when it is operated, the data of the dynamic latch circuit is not retained due to the decrease in the threshold voltage of the n-type MOS transistors 13 and 14 and the generation of the drain-source leak current path.

Therefore, in the typical embodiment of the present invention (FIG. 1), when the dynamic latch circuit 1 is stopped,
The reset signal becomes HIGH, the n-type MOS transistor 6 connected to the data input terminal 18 of the dynamic latch circuit 1 becomes ON, and the input of the dynamic latch circuit 1 becomes LOW. Further, the n-type MOS transistor 7 connected to the clock terminal of the dynamic type latch circuit 1 is also turned on, and the clock input on the n-type MOS transistor side of the dynamic type latch circuit 1 is also held in the LOW state. Therefore, the deterioration of the n-type MOS transistors 13 and 14 forming the dynamic latch circuit 1 is suppressed, and the reliability of the operation under a radiation environment can be improved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG.

The present embodiment is new to the conventional dynamic latch circuit shown in FIG. 2 in the following points. That is, the gate terminal of the n-type MOS transistor 13 in the clocked gate 2 is constituted by the n-type MOS transistors 7, 8 and the p-type MOS transistors 9, 10 instead of the clock CLK, and the clock CLKN and the reset signal RES are exclusive. It is connected to the output of the CMOS NOR circuit that outputs a logical OR. Further, the data input terminal 18 of the dynamic latch circuit 1 has an n-type MO
Connect the drain terminal of the S-transistor 6 to this n-type M
The gate terminal of the OS transistor 6 is reset signal RES
Connected to. Further, the voltage supply source of the logic circuit 4 has p
The drain terminal of the MOS transistor 17 is connected,
The gate terminal of the p-type MOS transistor 17 is connected to the reset signal RES.

In the present embodiment, during standby, that is, when the reset signal RES becomes HIGH, the n-type MOS transistors 6 and 7 are turned on, the p-type MOS transistors 9 and 17 are turned off, and the n-type MOS transistors 13 and 14 are turned on. Ground the gate terminal. As a result, it is possible to prevent the threshold voltage from lowering and the generation of leak current due to the irradiation of the ionizing radiation of the n-type MOS transistors 13 and 14 during standby, and to prevent the malfunction of the dynamic latch circuit in the radiation environment.

A second embodiment of the present invention will be described with reference to FIG.

In this embodiment, n is different from the first embodiment.
The MOS transistors 6 and 7 are removed. That is, the reset signal RES during standby is HIGH.
In such a case, the p-type MOS transistors 9 and 17 are turned off, and power is not supplied to the logic circuit 4 and the p-type MOS transistor 10. Although the gate terminals of the n-type MOS transistors 13 and 14 are not forced to be in the LOW state, the pn junction leakage current flows to gradually approach the LOW state. This time constant is estimated to be several tens of milliseconds at most, which is much shorter than the time of radiation deterioration of the element in the universe, which is a low irradiation dose rate (about 1 month when a radiation dose of 10 ² Gy is assumed). Therefore, under a low irradiation dose rate, n
The decrease in the threshold voltage and the generation of the leak current due to the irradiation of the ionizing radiation of the MOS transistors 13 and 14 can be suppressed, and the malfunction of the dynamic latch circuit in the radiation environment can be prevented. Further, in this embodiment, the number of transistors is reduced by two as compared with the first embodiment, and the increase in chip area can be suppressed.

A third embodiment of the present invention will be described with reference to FIG.

This embodiment is different from the first embodiment in that a p-type MOS transistor 22 is provided in the dynamic latch circuit 1, its source terminal is used as a power source, and its drain terminal is the source of the p-type MOS transistor 11. The terminal and the gate terminal are connected to the reset signal. Furthermore, n type M
An OS transistor 23 is provided, its drain terminal is connected to the input terminal of the inverter 3, and its gate terminal is connected to the reset signal RES.

In this embodiment, the deterioration of the inverter 3 is prevented. That is, in the first embodiment shown in FIG.
In the standby state, that is, when the reset signal RES becomes HIGH, the n-type MOS transistors 6 and 7 are turned on and the p-type MO transistor is turned on.
Although the S transistors 9 and 17 are turned off, on the other hand, the p-type MOS transistor 11 is turned on,
When the clock CLKN is held LOW, the input of the inverter 3 becomes HIGH, and the n-type MOS transistor 16 may be deteriorated during irradiation of ionizing radiation. As a result, the drive capability for the next stage of the inverter 3 is reduced after irradiation with radiation. On the other hand, in the present embodiment shown in FIG. 4, when the reset signal RES becomes HIGH, the p-type MOS transistor 22 is turned OFF and the n-type MOS transistor 23 is turned ON, so that the input of the inverter 3 is LOW. The state is maintained, and the deterioration of the inverter 3 at the time of radiation irradiation can be prevented.

A fourth embodiment of the present invention will be described with reference to FIG.

This embodiment is different from the third embodiment in that the control of the voltage supply source and the control of the input voltage of the logic circuit 5 on one side are performed. That is, the p-type MOS transistor 24 is provided in the dynamic type latch circuit 1, the source terminal thereof is used as a power source, the drain terminal thereof is used as the source terminal of the p-type MOS transistor 15 in the inverter 3, and the gate terminal thereof is used as a reset signal. Connected.
Further, the drain terminal of the p-type MOS transistor 25 is connected to the voltage supply source of the logic circuit 5, and the gate terminal of the p-type MOS transistor 25 is connected to the reset signal RES. Further, an n-type MOS transistor 27 is provided, the drain terminal of which is connected to the output terminal of the logic circuit 5 and the gate terminal of which is connected to the reset signal RES. As a result, the input and output of the logic circuit 5 become LO during standby.
The W state is maintained, and the deterioration of the n-type MOS transistor in the logic circuit 5 during radiation irradiation can be prevented.

In this embodiment, the logic circuits 4 and 5, and further, the gate terminals of all n-type MOS transistors in the dynamic latch circuit 1 are held in the LOW state during standby, and deterioration due to radiation irradiation can be prevented. ..

A fifth embodiment of the present invention will be described with reference to FIG.

This embodiment shows a latch circuit which is staticized by a feedback loop. For the first embodiment,
An inverter 28 is provided, the output terminal of the inverter 28 is connected to the input terminal of the inverter 3, and the input terminal of the inverter 28 is connected to the output terminal of the inverter 3. In this embodiment, a loop is formed by the inverter 28 and the inverter 3 and data can be held even during standby. The fact that deterioration can be prevented during irradiation of radiation is exactly the same as in the first embodiment.

[0023]

According to the present invention, the gate terminal of the n-type MOS transistor used for the clock gate constituting the dynamic latch circuit is always kept in the LOW state when the dynamic latch is in the standby state. It is possible to prevent the threshold voltage of the n-type MOS transistor from being lowered and the generation of the leak current between the source and the drain due to the irradiation of the ionizing radiation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a conventional dynamic latch circuit.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fifth embodiment of the present invention.

[Explanation of symbols]

1 ... Dynamic type latch circuit, 2 ... Clocked gate, 3, 21, 28 ... Inverter, 4, 5 ... Logic circuit,
6, 7, 8, 13, 14, 16, 23, 26, 27, 3
0 ... n-type MOS transistor, 9, 10, 11, 12,
15, 22, 24, 25, 29 ... P-type MOS transistor, 18 ... Data input terminal, 19 ... Clock input terminal,
20 ... Input terminal for inverted clock signal.

Claims (3)

[Claims] 1. A drain terminal of a first n-channel MOS transistor is connected to the data input terminal of a dynamic type latch circuit having a data input terminal and a clock input terminal, and an input terminal of a signal having a phase opposite to that of the clock. The gate terminal of the first n-type MOS transistor is connected to the reset signal, and the drain terminal of the second n-channel type MOS transistor is connected to the gate terminal of the n-type MOS transistor of the dynamic type latch circuit connected to the clock input terminal. A dynamic latch circuit characterized in that a terminal is connected and a gate terminal of the second n-channel MOS transistor is connected to the reset signal. 2. A voltage supply source of a first logic circuit connected to an input terminal of a dynamic type latch circuit having a data input terminal, a clock input terminal and an input terminal for a signal having a phase opposite to that of the clock, and a first p The drain terminal of the channel type MOS transistor is connected to the first p-channel type MOS transistor.
The gate terminal of the transistor is connected to the reset signal, and the output of the inverter whose supply voltage is controlled by the p-channel MOS transistor to the gate terminal of the n-channel MOS transistor of the dynamic latch circuit connected to the clock input terminal. , A gate terminal of the p-channel MOS transistor is connected to a reset signal, and an input terminal of the inverter is connected to a signal having a phase opposite to that of a clock. 3. A dynamic latch circuit in which the gate voltages of all n-channel MOS transistors are in a LOW state in the reset state.