JPH05121700A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To sufficiently reduce resistance value and enable high speed operation, in the case that gate electrodes of peripheral transistors and gate electrodes of select transistors in memory cells in a FLASHEEPROM are formed by using the same layer. CONSTITUTION:A side wall type gate electrode 34 of a select transistor in a memory cell part is composed of polycrystalline silicon films 31, 32 between which a WSi film 32 is sandwiched. In other case, said gate electrode 34 is composed of a WSi film obtained by making a polycrystalline silicon film formed in a side wall type and a W film formed on the polycrystalline silicon film reacts with silicon in a substratum. A gate electrodes 35 of a transistor in the peripheral part is simultaneously formed by using the same layer constitution as the side wall type gate electrode 34 of the select transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to FLASHEE, for example.
Electrically erasable MIS (metal such as PROM)
The present invention relates to an improvement in a semiconductor device including an insulator semiconductor (non-insulator semiconductor) type non-volatile semiconductor memory device and a manufacturing method thereof.

Currently, EEPROM and FLASHEEPR
The OM has become a representative of electrically erasable MIS type nonvolatile semiconductor memory devices, but in future trends, it is easy to achieve high integration and low cost.
It is considered that FLASHEEPROM, which is capable of batch erasing, is often used.

However, the FLASHEEPROM is
Unlike the EEPROM, the memory cell does not have a select transistor but is composed of only a memory transistor, and therefore has the following problems. That is,

Due to over-erasing, one memory transistor cannot be selected at the time of reading because the memory transistor is in a normally-on state. There is variation in the threshold voltage after erasing, making it difficult to sense. Therefore, in order to realize a stable FLASHEEPROM, the above problems must be solved.

[0005]

2. Description of the Related Art In order to solve the above-mentioned problems, a FLASHEEPROM having a structure in which a side wall is formed of a conductor on a side surface of a gate in a memory transistor and the side wall is used as a gate electrode of a select transistor. It has been known.

FIG. 25 shows an improved FLASHEEPRO.
FIG. 26 is a plan view of a main part for explaining M, and FIG. 26 is the same improved FL cut along the line XX seen in FIG. 25.
3A and 3B respectively show cutaway side views of main parts for explaining the ASHEEPROM.

In each figure, 1 is a substrate, 2 is a gate insulating film, 3 is a floating gate electrode, 4 is a control gate electrode, 5 is a gate electrode in a select transistor, 6 is a source region, and 7 is a source region. Indicates a drain region, and 8 indicates a bit line (BL). It goes without saying that the control gate electrode 4 is the word line WL. In the illustrated example, the gate electrode of the select transistor is formed only on one side of the gate of the memory transistor.

The illustrated FLASHEEPROM is operated by applying the following voltages, for example.

CG electrode drain SG electrode source write 12.5 [V] 8 [V] 5 [V] 0 [V] erase 0 [V] ≈ 15 [V] float float read 5 [V] 1 [V] 5 [V] 0 [V] In this table, the CG electrode is the control gate electrode 4, the drain is the drain region 7, and the SG electrode is select.
The gate electrode 5 and the source in the transistor represent the source region 6.

In this FLASHEEPROM, even if a state in which the memory transistor is normally turned on due to overerasure is performed, the select transistor does not substantially turn it on normally, and after erasing. It is less affected by the variation in the threshold voltage.

[0011]

The FLASHEEPROM described with reference to FIGS. 25 and 26 is useful because it can solve the problems (1) and (2) described above to a large extent, but in order to further speed it up, A low resistance conductor such as tungsten (W) is used for the material of each electrode.
When using molybdenum or molybdenum (Mo), inconvenience occurs.

That is, when the gate electrode of the peripheral transistor and the control gate electrode of the memory transistor are formed in the same layer, the side surface of the gate electrode of the peripheral transistor is the same as the gate electrode of the select transistor. Conductor sidewalls are created.

In order to avoid the above problem, it is conceivable that the gate electrode of the peripheral transistor and the gate electrode of the select transistor in the memory cell are formed in the same layer. In this case, a side wall-shaped gate electrode made of a low-resistance conductor such as W or Mo must be formed for the select transistor, and it is very difficult to form such a gate electrode satisfactorily.

FIG. 27 is a sectional side view of the essential part of the FLASHEEPROM at the process steps for explaining the formation of the gate electrode in the select transistor. In the figure, (A) shows a state before the electrode material film is processed into a side wall-shaped gate electrode, and (B) shows a state after the electrode material film is processed into a side wall-shaped gate electrode. Respectively.

As shown in (A), an insulating film 12 made of SiO ₂ , a floating gate electrode 13 made of polycrystalline silicon, and SiO _{2 are} formed on a silicon semiconductor substrate 11.
_{After the} insulating film 14 made of ₂ and the control gate electrode 15 made of polycrystalline silicon and the control gate electrode 16 made of W or Mo are formed, the insulating film 17 made of SiO ₂ is covered and the polycrystalline silicon film is formed thereon. 18 and a refractory metal film 19 such as W or Mo is formed.

As shown in (B), reactive ion etching (re
By applying the active ion etching (RIE) method, the refractory metal film 19 and the polycrystalline silicon film 18 are anisotropically etched to form side wall gate electrodes of the select transistor. When the steps described above are adopted, the refractory metal film 19 remaining as the side wall-shaped gate electrode is very small, and it cannot be expected to reduce the resistance.

In the FLASHEEPROM according to the present invention, when the gate electrode of the peripheral transistor and the gate electrode of the select transistor in the memory cell are formed in the same layer, the resistance value is sufficiently lowered to increase the speed. Be able to plan.

[0018]

In the present invention, there are two basic flows in which the order of the steps is slightly different, which will be described below. 1 to 8 are sectional side views of essential parts of a semiconductor device in process steps for explaining the principle of the present invention. In addition, as shown in the figure,
The left side of the drawing is the memory cell portion, and the right side is the peripheral portion.

1- (1) A gate insulating film 23, an electrode material film to be a storage electrode, an interelectrode insulating film 25, and a control electrode, for example, a silicon film are formed on a semiconductor substrate 21.

See FIG. 2 2- (1) A low resistance metal film such as WSi or MoSi which also becomes a part of the control electrode is formed on the silicon film which becomes a part of the control electrode.

See FIG. 3 3- (1) Resist film 28 ₁ having a gate electrode pattern
To form.

See FIG. 4. 4- (1) The resist film 28 ₁ is used as a mask to form a low-resistance metal film as a control electrode, a silicon film as a control electrode, an interelectrode insulating film 25, and an electrode material film as a storage electrode. Pattern. As a result, the control electrode 27, the control electrode 26, and the storage electrode 24 are formed, and nothing is left on the gate insulating film 23 in the peripheral portion.

5- (1) After removing the resist film 28 ₁ , an insulating film 29 covering the entire surface including the gate portion is formed. 5- (2) Ion implantation is performed to form the drain region 30.

See FIG. 6 6- (1) Silicon film 3 such as polycrystalline silicon
1. Low resistance metal film 32 made of, for example, WSi or MoSi, silicon film 33 made of, for example, polycrystalline silicon
To form.

7- (1) A resist film 28 ₂ having a pattern for forming a gate electrode of a transistor in the peripheral portion is formed.

See FIG. 8 8- (1) For example, by applying the RIE method, the silicon film 33, the low resistance metal film 32, and the silicon film 31 are anisotropically etched. As a result, the side wall-shaped gate electrode 34 in the select transistor and the gate electrode 35 in the peripheral transistor are formed. 8- (2) The resist film 28 ₂ is removed.

9 to 11 are also side sectional views of essential parts of the semiconductor device in process steps for explaining the basic point of the present invention. Even in this case, the memory cell portion is on the left side and the peripheral portion is on the right side in the figure, and the steps described above with reference to FIGS. 1 to 5 can be applied as they are. Here, the following steps will be described.

See FIG. 9 9- (1) For example, a silicon film 31 such as polycrystalline silicon
To form.

10- (1) A resist film (not shown) for forming a gate electrode in the peripheral portion is formed. 10- (2) For example, the silicon film 31 is anisotropically etched by applying the RIE method. Accordingly, in the memory cell portion, the silicon film 31 is patterned into a sidewall shape for forming the gate electrode of the select transistor, and in the peripheral portion, the silicon film 31 is gate electrode. Is patterned into a shape for forming the. 10- (3) The resist film (not shown) is removed.

See FIG. 11 11- (1) Low resistance metal film 3 such as W or Mo
2 is selectively formed. The low resistance metal film 32 is formed only on silicon. After that, the low-resistance metal film 32 and the silicon film 31 are heat-treated in appropriate steps to be converted into metal silicide, and the unreacted low-resistance metal film 3 is formed.
2 is removed.

According to the above, both the side wall gate electrode of the select transistor in the memory cell portion and the gate electrode of the transistor in the peripheral portion are silicidized, which is advantageous for speeding up. Becomes In any case, the control electrode of the memory transistor in the memory cell portion may have a silicide structure if necessary.

From the above, in the semiconductor device and the manufacturing method thereof according to the present invention, (1) the gate electrode of the memory transistor in the electrically erasable MIS type nonvolatile memory cell portion A gate electrode formed by forming a silicon film (for example, a polycrystalline silicon film) on a side surface (for example, a control electrode 26 and a storage electrode 24) with a metal silicide film (for example, a WSi film) interposed therebetween in a side wall shape. A select transistor having (for example, a sidewall-shaped gate electrode 34), and a transistor having a gate electrode (for example, a gate electrode 35) formed in the same layer as the gate electrode of the select transistor in the peripheral portion, Or comprising, or

(2) In the above (1), a silicon film in which the side wall-shaped gate electrode in the select transistor is formed in a side wall shape (for example, polycrystalline silicon formed in a side wall shape) The film 43, that is, the gate electrode 43 _SG ) and the metal film (for example, the W film) formed on the surface of the silicon film, and the metal silicide film (for example, the WSi film 4) obtained by reacting the underlying silicon.
4) and the gate electrode of the transistor in the peripheral portion is in the same layer as the gate electrode of the select transistor (for example, a polycrystalline silicon film 43) and a metal film (for example, a W film) formed on the surface of the silicon film. ) And the underlying silicon are made to react with each other to form a metal silicide film (for example, a WSi film 44), or

(3) A step of forming a gate electrode (for example, the control electrode 26 and the storage electrode 24) of the memory transistor in the electrically erasable MIS type nonvolatile memory cell portion, and then the memory A step of forming an insulating film (for example, the insulating film 29) covering the gate electrode of the transistor and then forming a silicon film (for example, a polycrystalline silicon film) with a metal silicide film (for example, a WSi film) sandwiched between them; A step of forming a mask film for forming a gate electrode of a transistor on a silicon film sandwiching the metal silicide film in the peripheral portion, and then a silicon film sandwiching the metal silicide film Side walls of the select transistor are formed on the side surfaces of the gate electrode of the memory transistor by performing anisotropic etching (example If either characterized by comprising contains a step of forming a gate electrode of at transistor in the peripheral portion (e.g., the gate electrode 35) to form a gate electrode 34), or,

(4) A step of forming a gate electrode (for example, the control electrode 26 and the storage electrode 24) of the memory transistor in the electrically erasable MIS type nonvolatile memory cell portion, and then the memory. A silicon film (for example, a polycrystalline silicon film 43) after forming an insulating film (for example, an insulating film 29) covering the gate electrode of the transistor
A step of forming a mask film for forming a gate electrode of a transistor on the silicon film existing in the peripheral portion, and then performing anisotropic etching of the silicon film to form the memory. Forming a sidewall-shaped gate electrode (for example, the gate electrode 43 _SG ) in the select transistor on the side surface of the gate electrode of the transistor and forming a gate electrode (for example, the gate electrode 43 _G ) of the transistor in the peripheral portion A step of forming a metal film (for example, a W film) covering the side wall-shaped gate electrode of the select transistor and the gate electrode of the transistor in the peripheral portion, and then forming the metal film And a step of reacting with underlying silicon to convert it into a metal silicide film (for example, a WSi film 44). It is characterized by

[0036]

According to the present invention, the side wall gate electrode of the select transistor formed on the side surface of the gate electrode of the memory transistor in the memory cell portion and the gate electrode of the transistor in the peripheral portion are formed in the same layer. Since it is formed, a side wall made of a conductive material is not formed on the side surface of the gate electrode in the transistor in the peripheral portion, and the side wall-shaped gate electrode of the select transistor is a metal film in the silicon film. It is possible to obtain sufficient low resistance and withstand voltage by adopting a structure in which a silicide film is interposed, or a structure in which a metal film is deposited on a silicon film formed in a sidewall shape to form a silicide. did.

[0037]

12 to 20 are sectional side views of a main part of a semiconductor device at a process step for explaining a first embodiment of the present invention, which will be described below with reference to these drawings. To do.
The same symbols as those used in FIGS. 1 to 11 represent the same parts or have the same meanings.

See FIG. 12 12- (1) Selective thermal oxidation of a selectively formed Si ₃ N ₄ film on which an extremely thin SiO ₂ film is used as an oxidation resistant mask.
The thickness of the silicon semiconductor substrate 21 is, for example, 5000 by applying the ilicon: LOCOS method.
Field insulating film 2 made of SiO _{2 of} about [Å]
Form 2.

12- (2) The oxidation resistant mask or the like is removed to expose the active region in the silicon semiconductor substrate 21. 12- (3) By applying the thermal oxidation method, the gate insulating film 23 made of SiO ₂ having a thickness of 100 [Å] to 400 [Å] is formed.

See FIG. 13 13- (1) Chemical vapor deposition
Or deposition (CVD) method is applied to form a polycrystalline silicon film having a thickness of, for example, 1000 [Å]. The polycrystalline silicon film is later patterned to become a storage electrode. 13- (2) By applying the thermal oxidation method, the inter-electrode insulating film 25 made of SiO ₂ having a thickness of, for example, 200 [Å] is formed.
To form.

See FIG. 14 14- (1) By applying the CVD method, a polycrystalline silicon film having a thickness of, for example, about 1000 [Å] to 2000 [Å] is formed. Incidentally, this polycrystalline silicon film is later patterned to become a control electrode.

See FIG. 15. 15- (1) A resist film (not shown) having a gate electrode pattern is formed by applying a resist process in a general lithography technique. 15-(2) RIE to the etching gas and bromine gas (for polycrystalline silicon) and fluorine-based gas (for SiO ₂₎
By applying the method, the polycrystalline silicon film to be the control electrode, the interelectrode insulating film 25, and the polycrystalline silicon film to be the storage electrode are patterned. Accordingly, the control electrode 2
6 and the storage electrode 24 are formed, and in the peripheral portion, all except the gate insulating film 23 are removed.

16- (1) By removing the resist film used as the mask for patterning and then applying the CVD method, the thickness covering the entire surface including the gate portion is set to, for example, 200.
An insulating film 29 made of SiO _{2 of} [Å] is formed. 16- (2) A resist film (not shown) having an opening at a portion where a drain region is to be formed is formed by applying a resist process in a normal lithography technique. 16- (3) By applying the ion implantation method, the dose amount is 1 × 10 ¹⁵ [cm ⁻² ], and the ion acceleration voltage is 60 [ke
V], As ions are implanted to form the n-drain region 30.

See FIG. 17 17- (1) By applying the CVD method, a polycrystalline silicon film having a thickness of, for example, about 500 [Å] is formed on the entire surface. The polycrystalline silicon film is anisotropically etched to serve as a side wall gate electrode of the select transistor and a gate electrode of the transistor in the peripheral portion.

17- (2) By applying the sputtering method, the entire surface has a thickness of, for example, 1000 [Å] to 200.
A 0 [Å] WSi film is formed. The WSi film is anisotropically etched to form side wall gate electrodes of select transistors and gate electrodes of peripheral transistors. The WSi film is MoSi
A film, a TiSi ₂ film, or another heat-resistant metal silicide film can be substituted, and salicide may be used to generate a heat-resistant metal and a silicide if necessary. 17- (3) By applying the CVD method, a polycrystalline silicon film having a thickness of, for example, 500 [Å] is formed on the entire surface.
The polycrystalline silicon film is anisotropically etched to serve as a side wall gate electrode of the select transistor and a gate electrode of the transistor in the peripheral portion.

See FIG. 18 18- (1) A resist film (not shown) for forming a gate electrode of a transistor in a peripheral portion by applying a resist process in a general lithography technique. To form. 18- (2) RI with chlorine gas as etching gas
By applying the method E, the polycrystalline silicon film formed in step 17- (1) and the WS formed in step 17- (2)
The i film and the polycrystalline silicon film formed in step 17- (3) are anisotropically etched to form the side wall gate electrode 34 of the select transistor in the memory cell portion and the transistor in the peripheral portion. The gate electrode 35 is formed.

See FIG. 19. 19- (1) Unnecessary one side wall shape due to application of resist process in ordinary lithography technique and RIE method using fluorine gas as etching gas The gate electrode 34 is removed. Note that this step is not essential.

See FIG. 20. 20- (1) By applying the CVD method, an insulating film 36 made of SiO _{2 having} a thickness of, for example, about 200 [Å] is formed. 20- (2) By applying the ion implantation method, the dose amount is 1 × 10 ¹⁵ [cm ⁻² ], and the ion acceleration voltage is 60 [ke].
V] is implanted with As ions to form an n-source region 37 of the select transistor in the memory cell portion and an n-source region 38 and an n-drain region 39 of the transistor in the peripheral portion.

20- (3) By applying the CVD method, PSG (phosph) having a thickness of, for example, 8000 [Å]
An interlayer insulating film 40 made of o-silicate glass is formed. 20- (4) Selective etching of the interlayer insulating film 40 and the insulating film 36 is performed by applying the resist process in the ordinary lithography technique and the RIE method using a fluorine-based gas as an etching gas to selectively etch the source. Form an electrode contact window.

20- (5) Heat treatment at a temperature of 900 [° C.] and a time of 10 [min] causes the interlayer edge film 40 made of PSG.
Reflow. 20- (6) By applying the sputtering method,
An Al film having a thickness of, for example, 1 [μm] is formed.

20- (7) Step 2 is carried out by applying the resist process in the ordinary lithography technique and the RIE method using chlorine gas as the etching gas.
The Al film formed by 0- (6) is patterned to form the source electrode / wiring 41. By applying the 20- (8) CVD method, the cover film 42 made of PSG having a thickness of, for example, 1 [μm] is formed.

In the first embodiment, three layers of a polycrystalline silicon film, a low resistance conductive film, and a polycrystalline silicon film are used as the electrode material film to be the side wall gate electrodes in the select transistor in the memory cell portion. Since the structure is adopted, even if the sidewall is formed by anisotropic etching, the low resistance conductive film can be left to an extent sufficient to reduce the resistance value of the gate electrode. If the amount of the low-resistance conductive film is too large, the problem of lowering the breakdown voltage occurs, so it is useful to interpose the polycrystalline silicon film under the low-resistance conductive film.

21 to 24 are side sectional views of a main part of a semiconductor device at a process step for explaining a second embodiment of the present invention, which will be described below with reference to these figures. ..
Note that the same symbols as those used in FIGS. 1 to 20 represent the same parts or have the same meanings, and the steps described with reference to FIGS. Since it can be applied to the example as well, the description will be given from the next stage.

21- (1) By applying the CVD method, a polycrystalline silicon film 43 having a thickness of, for example, about 2000 [Å] to 4000 [Å] is formed.

22- (1) A resist film (not shown) for forming a gate electrode of a transistor in a peripheral portion is formed by applying a resist process in the lithography technique. .. 22- (2) RI using bromine gas as etching gas
By applying the E method, the polycrystalline silicon film 43 is anisotropically etched. As a result, in the memory cell portion, the polycrystalline silicon film 43 is formed in a side wall shape for forming the gate electrode of the select transistor, and in the peripheral portion, the polycrystalline silicon film 43 is formed. 43 is patterned into a shape for forming the gate electrode of the transistor. Here, the side wall-shaped gate electrode in the select transistor formed by anisotropically etching the polycrystalline silicon film 43 is designated by the symbol 43 _SG , and the gate of the transistor in the peripheral portion is designated. The electrodes shall be designated by the symbol 43 _G.

22- (3) The resist film (not shown) is removed. 22- (4) By applying the CVD method, for example, W
The film is selectively formed. The W film is formed only on silicon.

22- (5) Temperature 900 [° C.], Time 10
The heat treatment of [minute] is performed to react the W film with the underlying polycrystalline silicon to convert into WSi, and the unreacted W film is removed. The WSi film is designated by the symbol 44. As a result, the surface of the side wall gate electrode 43 _SG of the select transistor in the memory cell portion and the surface of the gate electrode 43 _G of the transistor in the peripheral portion are covered with the WSi film 44.

See FIG. 23. 23- (1) By using a resist process in a normal lithography technique and a chemical wet etching method using a fluorine-based gas as an etchant, unnecessary one side The wall-shaped gate electrode 43 _SG is removed. Note that this step is not essential.

See FIG. 24 24- (1) By applying the CVD method, the insulating film 36 made of SiO ₂ and having a thickness of, for example, about 200 [Å] is formed. 24- (2) By applying the ion implantation method, the dose amount is 1 × 10 ¹⁵ [cm ⁻² ], and the ion acceleration voltage is 60 [ke
V] is implanted with As ions to form an n-source region 37 of the select transistor in the memory cell portion and an n-source region 38 and an n-drain region 39 of the transistor in the peripheral portion.

24- (3) By applying the CVD method, PSG (phosph) having a thickness of, for example, 8000 [Å]
An interlayer insulating film 38 made of o-silicate glass is formed. 24- (4) Selective etching of the interlayer insulating film 38 and the insulating film 36 is performed by applying a resist process in a normal lithography technique and an RIE method using a fluorine-based gas as an etching gas. Forming a source electrode contact window.

24- (5) Heat treatment at a temperature of 900 [° C.] and a time of 10 [min] causes the interlayer insulating film 3 made of PSG.
8 reflow is performed. 24- (6) By applying the sputtering method,
An Al film having a thickness of, for example, 1 [μm] is formed.

24- (7) Step 2 is carried out by applying the resist process in the ordinary lithography technique and the RIE method using chlorine gas as the etching gas.
The Al film formed by 0- (6) is patterned to form the source electrode / wiring 39. The 24- (8) CVD method is used to form the cover film 42 made of PSG having a thickness of, for example, 1 [μm].

In the second embodiment, when forming the gate electrode in the select transistor in the memory cell portion, patterning is performed so that the polycrystalline silicon film on the side surface of the gate electrode of the memory transistor remains in the shape of a side wall. After that, a metal film of W or the like is formed on the surface of the gate electrode so as to be silicided. It is easy to properly reduce.

[0064]

In the semiconductor device and the method of manufacturing the same according to the present invention, the side wall gate electrode of the select transistor in the electrically erasable MIS type non-volatile memory cell portion is metal silicide. A silicon film having a film sandwiched between them, or a silicon film formed in a sidewall shape and a metal silicide film obtained by reacting a metal film formed on the silicon film with the underlying silicon film Then, the gate electrodes of the transistors in the peripheral portion are simultaneously formed in the same layer structure as the side wall gate electrodes of the select transistors.

According to this structure, the side wall gate electrode of the select transistor formed on the side surface of the gate electrode of the memory transistor in the memory cell portion and the gate electrode of the transistor in the peripheral portion are the same. Since it is formed of one layer, the side surface of the gate electrode of the transistor in the peripheral portion is made of a conductive material.
The wall is never formed, and the side wall-shaped gate electrode of the select transistor has a structure in which a metal silicide film is interposed in a silicon film or is formed in a side wall shape. Since a metal film is deposited on the formed silicon film to be silicidized, it is possible to easily achieve both low resistance sufficient to improve operation speed and sufficient withstand voltage. Is possible.

[Brief description of drawings]

FIG. 1 is a side sectional view of a main part of a semiconductor device in a process main part for explaining a basic point of the present invention.

FIG. 2 is a side sectional view of a main part of a semiconductor device at a process main part for explaining the basic point of the present invention.

FIG. 3 is a side sectional view of a main part of a semiconductor device in a process main part for explaining the basic point of the present invention.

FIG. 4 is a sectional side view of a main part of a semiconductor device at a process key point for explaining the basic point of the present invention.

FIG. 5 is a side sectional view of a main part of a semiconductor device at a process main part for explaining the basic point of the present invention.

FIG. 6 is a side sectional view of a main part of a semiconductor device at a process main part for explaining the basic point of the present invention.

FIG. 7 is a side sectional view of a main part of a semiconductor device in a process main part for explaining the basic point of the present invention.

FIG. 8 is a side sectional view of a main part of a semiconductor device in a process main part for explaining the basic point of the present invention.

FIG. 9 is a side sectional view of a main part of a semiconductor device at a process main part for explaining the basic point of the present invention.

FIG. 10 is a side sectional view of a main part of a semiconductor device at a process main part for explaining the basic point of the present invention.

FIG. 11 is a side sectional view of a main part of a semiconductor device at a process main part for explaining the basis of the present invention.

FIG. 12 is a side sectional view of a main part of a semiconductor device in a process main part for explaining a first embodiment of the present invention.

FIG. 13 is a sectional side view of a main part of a semiconductor device in a process key point for explaining a first embodiment of the present invention.

FIG. 14 is a side sectional view of a main part of a semiconductor device in a process main part for explaining a first embodiment of the present invention.

FIG. 15 is a side sectional view of a main part of a semiconductor device in a process main part for explaining a first embodiment of the present invention.

FIG. 16 is a side sectional view of a main part of a semiconductor device in a process main part for explaining a first embodiment of the present invention.

FIG. 17 is a side sectional view of a main part of a semiconductor device in a process key point for explaining a first embodiment of the present invention.

FIG. 18 is a side sectional view of a main part of a semiconductor device in a process main part for explaining a first embodiment of the present invention.

FIG. 19 is a sectional side view of a main part of a semiconductor device in a process main part for explaining a first embodiment of the present invention.

FIG. 20 is a side sectional view of a main part of a semiconductor device in a process main part for explaining a first embodiment of the present invention.

FIG. 21 is a fragmentary side view of a semiconductor device in a process essential part for explaining a second embodiment of the present invention.

FIG. 22 is a side sectional view of a main part of a semiconductor device in a process main part for explaining a second embodiment of the present invention.

FIG. 23 is a side sectional view of a main part of a semiconductor device in a process key point for explaining a second embodiment of the present invention.

FIG. 24 is a side sectional view of a main part of a semiconductor device in a process main part for explaining a second embodiment of the present invention.

FIG. 25 is a plan view of relevant parts for explaining an improved FLASHEEPROM.

FIG. 26 is a cutaway side view of essential parts of the FLASHEEPROM taken along line XX seen in FIG. 25.

FIG. 27 is a FLAS at a process step for explaining formation of a gate electrode in a select transistor.
It is a principal part cutting side view of HEEPROM.

[Explanation of symbols]

21 silicide semiconductor substrate 22 field insulating film 23 gate insulating film 24 storage electrode 25 interelectrode insulating film 26 control electrode 27 control electrode 29 insulating film 30 n-drain region 34 side wall gate electrode 35 gate electrode 36 insulating film 37 n -Source region 38 n-Source region 39 n-Drain region 40 Interlayer insulating film 41 Source electrode / wiring 42 Cover film 43 Polycrystalline silicon film 43 _SG Gate electrode 43 _G Gate electrode 44 WSi film

Claims (4)

[Claims] 1. A silicon film is formed in a sidewall shape on a side surface of a gate electrode of a memory transistor in an electrically erasable MIS type nonvolatile memory cell portion with a metal silicide film interposed therebetween. And a transistor having a gate electrode formed in the same layer as the gate electrode of the select transistor in the peripheral portion. 2. A side of a select transistor.
The gate electrode of the transistor in the peripheral portion is composed of a silicon film in which the wall-shaped gate electrode is formed in the shape of a side wall and a metal silicide film obtained by reacting the metal film formed on the surface of the silicon film with the underlying silicon. The electrode is composed of a silicon film in the same layer as the gate electrode of the select transistor, and a metal silicide film obtained by reacting the metal film formed on the surface of the silicon film with the underlying silicon film. The semiconductor device according to claim 1. 3. A step of forming a gate electrode of a memory transistor in an electrically erasable MIS type nonvolatile memory cell portion, and then forming an insulating film covering the gate electrode of the memory transistor. And then forming a silicon film sandwiching the metal silicide film between them, and then forming a mask film for forming a gate electrode of the transistor on the silicon film sandwiching the metal silicide film in the peripheral portion. Then, the silicon film sandwiching the metal silicide film is anisotropically etched to form a side wall-shaped gate electrode in the select transistor on the side surface of the gate electrode of the memory transistor. And a step of forming a gate electrode of a transistor in a peripheral portion of the semiconductor device. Method. 4. A step of forming a gate electrode of a memory transistor in an electrically erasable MIS type nonvolatile memory cell portion, and then forming an insulating film covering the gate electrode of the memory transistor. A step of forming a silicon film after that, a step of forming a mask film for forming a gate electrode of a transistor on the silicon film in the peripheral portion, and then performing an anisotropic etching of the silicon film. A step of forming a side wall-shaped gate electrode in the select transistor on the side surface of the gate electrode of the memory transistor and forming a gate electrode of the transistor in the peripheral portion, and then forming the gate electrode of the transistor in the peripheral portion. A metal that covers the side wall-shaped gate electrode and the transistor gate electrode in the peripheral portion A method of manufacturing a semiconductor device, comprising: a step of forming a film; and a step of subsequently reacting the metal film with underlying silicon to convert into a metal silicide film.