JPH05121566A - Manufacture of semiconductor devices - Google Patents

Abstract

PURPOSE:To form connection holes which produce no disconnection failure of a wiring layer nor reliability degradation in a formation processing of connection holes for wiring which connect device of integrated circuits having a large number of devices. CONSTITUTION:After the formation of diffusion layer 4 or a first wiring layer 7, an interlaminar insulation film is formed thicker than a specified film thickness, thereby forming a pattern of a photoresist 6 for a connection hole. Some portion of the film thickness is etched with an etching liquid or isotropically dry-etched so as to eliminate the photoresist. The remaining interlaminar insulation film is anisotropically dry-etched until the first wiring layer 7 appears on surface, thereby forming a connection hole in a smooth cross section shape having no offset between the upper portion whose opening area spreads over and the bottom. It is possible to prevent the generation of constriction when forming a second wiring layer and hence protect the wiring from disconnection and enhance the reliability of integrated circuit by adopting a formation method of the connection hole in the structure described above.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a connection hole for a wiring connecting elements of an integrated circuit including a large number of elements inside.

[0002]

2. Description of the Related Art FIGS. 2 (a) to 2 (d) are cross-sectional views in order of steps showing a conventional method of manufacturing a connection hole for a wiring connecting elements of an integrated circuit.

In the figure, 1 is a silicon substrate, 2 is LO
COS oxide film, 3 is a polycrystalline silicon layer, 4 is a diffusion layer, 5
Is a phosphorus glass film, 6 is a photoresist, and 7 is an AL (aluminum) alloy layer.

This manufacturing method is a method that is generally used in forming connection holes for wirings connecting elements of an integrated circuit, and therefore will be briefly described below.

In FIG. 2A, the LOC is formed on the silicon substrate 1.
A pattern of the OS oxide film 2 and the polycrystalline silicon layer 3 is formed, and a diffusion layer 4 is formed by thermal diffusion or ion implantation.

In FIG. 2B, the phosphorus glass film 5 is formed by the CVD method. A pattern of the photoresist 6 is formed on this.

In FIG. 2C, the photoresist 6 is used as a mask to open the upper opening area of the phosphor glass film 5 by an etching solution or isotropic dry etching. The remaining film underneath is removed faithfully to the pattern of the resist 6.

In FIG. 2D, the photoresist 6 is removed and a pattern of the AL alloy layer 7 is formed. Here, FIG.
In (d), the polycrystalline silicon layer 3 is the first wiring layer, the phosphorus glass film 5 is the interlayer insulating film, and the AL alloy layer 7 is the second wiring layer.
Corresponding to the second wiring layer, each plays a role as a component of the integrated circuit.

[0009]

Problems to be Solved by the Invention FIGS.
The problems in the manufacturing method of the conventional example (d) are as follows.

(1) In the connection hole formed by the conventional manufacturing method, the opening area of the upper part is widened, but there is a pointed step with the bottom part of the connection hole. When a certain AL alloy layer is formed by the sputtering method, a constriction as shown in FIG. When the size of the connecting hole becomes small, a wire break may occur at the constricted portion.

(2) Even if disconnection does not occur at the constricted part of the AL alloy layer, if there is this constriction, the CVD is further formed on the upper part.
Reliability of the integrated circuit, such as the formation of cavities in the film when the interlayer insulating film and the final protective film are formed by the method, and the increase in the leak current between the wiring layer and the AL alloy layer corrosion due to the intrusion of moisture. Occurs.

The present invention has been made in order to solve the above-mentioned problems, and eliminates the constriction in the connection hole formed in the second wiring layer, which causes disconnection failure of the wiring layer and deterioration of reliability. It is an object of the present invention to provide a method for forming a connection hole for a wiring that connects elements of an integrated circuit that does not occur.

[0013]

According to a method of manufacturing a semiconductor device of the present invention, a diffusion layer or a first wiring layer is formed on a semiconductor substrate, and then the diffusion layer or the first wiring layer is formed. A step of forming an interlayer insulating film thicker than a desired film thickness, a step of forming a photoresist pattern of a connection hole on the insulating film by a photolithography technique, an etching solution or an isotropic method of the insulating film using the pattern as a mask. By a step of etching the photoresist by a certain ratio by dry etching to remove the photoresist, and a step of anisotropic dry etching the remaining interlayer insulating film until the surface of the first wiring layer appears in the connection hole. A disconnection occurs in the second wiring layer having a large opening area which is provided in the interlayer insulating film to electrically connect the diffusion layer or the first wiring layer to the second wiring layer. It is a manufacturing method of a semiconductor device and forming a pile fine contact hole. Further, the interlayer insulating film is composed of two layers of insulating films having different etching rates with respect to the etching solution or dry etching, and the difference in etching rate is caused when the upper insulating film is etched by the etching solution or isotropic dry etching. A method for manufacturing a semiconductor device is characterized in that a desired connection hole is formed by automatically adjusting the etching ratios of the upper and lower insulating films by utilizing it.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1A to 1E are cross-sectional structural views in order of steps in a process of forming a connection hole showing an embodiment of the present invention. 1 to 7 except 5 are the same as those used in the description of the conventional example shown in FIGS. 2A to 2D, and their configurations are also the same, so that the description thereof will be omitted.

In FIG. 1, 8 is a lower silicon oxide film and 9 is an upper phosphorous glass film.

1 (a) to 1 (e) will be described below in the order of steps.

In FIG. 1A, the LOC is formed on the silicon substrate 1.
A pattern of the OS oxide film 2 and the polycrystalline silicon layer 3 is formed, and a diffusion layer 4 is formed by thermal diffusion or ion implantation.

In FIG. 1B, the lower silicon oxide film 8 is formed with 80
It is formed by a high temperature CVD method at about 0 ° C. Subsequently, the upper phosphorous glass film 9 is formed by a low temperature CVD method at about 400 ° C. The total film thickness of the lower silicon oxide film 8 and the upper phosphorous glass film 9 is about twice the desired film thickness. A pattern of the photoresist 6 is formed on this.

In FIG. 1C, the upper phosphorous glass film 9 is etched by using the photoresist 6 as a mask and widening the opening area of the upper part by an etching solution or isotropic dry etching. In this state, the photoresist 6 is removed.

In FIG. 1D, the surface of the diffusion layer 4 or the polycrystalline silicon layer 3 is covered with the upper phosphorous glass film 9 and the lower silicon oxide film 8 without a mask by a dry etching device having a strong anisotropy such as an RIE etching device. The entire surface is etched until appears.

In FIG. 1E, the AL alloy layer 7 is formed by the sputtering method to form a desired pattern.

In this embodiment, FIG. 1 (d) and FIG.
As shown in (e), there is no step between the portion where the opening area of the upper part is widened and the bottom portion, and a connection hole having a smooth cross-sectional shape can be formed. When the AL alloy layer, which is the second wiring layer, is formed by the sputtering method, no constriction as shown in FIG. 1E corresponding to the step can be formed. Therefore, when the size of the connection hole becomes smaller, disconnection is less likely to occur at this constricted portion, and a connection hole with a smooth cross-sectional shape with no step between the upper opening area and the bottom is formed. is made of. In FIG. 1C, when the upper opening area is widened and etching is performed, the etching rate of the lower silicon oxide film 8 is smaller than that of the upper phosphorus glass film 9 with respect to the etching solution or the dry etching. As the etching progresses, the etching rate decreases, and the depths of a large number of connection holes on the silicon substrate become uniform, so that the etching ratio of the upper and lower insulating films can be automatically adjusted.

When the first wiring layer is an AL alloy layer and the second wiring layer is also an AL alloy layer, the lower silicon oxide film 8 and the upper phosphorous glass film 9 in FIG. 1B are used. Instead of this, a silicon oxide film or a phosphorus glass film formed by a low temperature CVD method at about 400 ° C. is deposited about twice the desired film thickness and used as an interlayer insulating film. Further, as shown in FIG. 1C, with the photoresist 6 as a mask, the upper phosphorous glass film 9 is etched by about half of the film thickness deposited by an etching solution or isotropic dry etching to finish the upper part of the interlayer insulating film. The etching can be performed by widening the opening area of. After that, the remaining portion of the interlayer insulating film is entirely etched by a dry etching apparatus having a strong anisotropy as described above until the surface of the wiring layer of the first layer appears. It is possible to form a connection hole having a smooth cross-sectional shape with no step between the bottom and the bottom.

[0024]

As described above, the present invention relates to a method of manufacturing a connection hole for a wiring that connects elements of an integrated circuit including a large number of elements inside, and includes a portion having a wide opening area at the top and a bottom portion. Since there is no step between them and the connection hole having a smooth cross-sectional shape can be formed, when the AL alloy layer which is the second wiring layer is formed by the sputtering method, a constriction corresponding to the step cannot be formed. Therefore, when the size of the connection hole becomes small, no disconnection will occur at the constricted portion, and a cavity will be formed in the film when the interlayer insulating film or the final protective film is formed on the upper part by the CVD method, Further, there is no problem that the reliability of the integrated circuit is deteriorated, such as the increase of leak current between the upper wiring layer and the corrosion of the AL alloy layer due to the intrusion of water.

Further, as an interlayer insulating film, the etching rate is different from that of an etching solution or dry etching.
By using the upper layer insulation film, the etching rate of the upper layer and the lower layer is automatically adjusted by utilizing the difference in etching rate when the upper layer insulation film is etched by an etchant or isotropic dry etching. It is possible to make the depth of many connection holes on the semiconductor substrate uniform.

Further, since the anisotropic dry etching used for the second etching selectively grinds the semiconductor substrate in the vertical direction, in the step portion formed by the first wiring layer or the like, the interlayer insulating film is formed on the side wall. As a result, by this step, the surface of the interlayer insulating film can be flattened at the same time when the connection hole is opened, and the thinning phenomenon at the step portion of the first wiring layer can be prevented.

[Brief description of drawings]

1A to 1E are cross-sectional structural views in order of steps in a step of forming a connection hole showing an embodiment of the present invention.

FIG. 2A to FIG. 2D are cross-sectional structural views in order of the steps, showing a conventional method for manufacturing a connection hole of a wiring connecting elements of an integrated circuit.

[Explanation of symbols]

 1 Silicon Substrate 2 LOCOS Oxide Film 3 Polycrystalline Silicon Layer 4 Diffusion Layer 5 Phosphor Glass Film 6 Photoresist 7 AL (Aluminum) Alloy Layer 8 Lower Silicon Oxide Film 9 Upper Phosphor Glass Film

Claims (2)

[Claims] 1. A step of forming a diffusion layer or a first wiring layer on a semiconductor substrate and then forming an interlayer insulating film on the diffusion layer or the first wiring layer to a thickness greater than a desired thickness, A step of forming a photoresist pattern of a connection hole on the insulating film by a photolithography technique, the insulating film is etched by an etching solution or isotropic dry etching to a certain proportion of the film thickness using the pattern as a mask. A step of removing the photoresist and a step of performing anisotropic dry etching on the remaining interlayer insulating film until the surface of the first wiring layer appears in the connection hole, thereby forming the diffusion layer or the first wiring layer and the second layer. Characterized in that a fine connection hole is provided in the interlayer insulating film for electrically connecting the second wiring layer for electrically conducting the second wiring layer, which is hard to cause disconnection of the second wiring layer having a large opening area above. Body device manufacturing method. 2. The interlayer insulating film according to claim 1 is composed of two layers of insulating films having different etching rates with respect to an etching solution or dry etching, and the upper insulating film is etched with the etching solution or isotropic dry etching. At this time, by utilizing the difference in etching rate, the etching rates of the upper and lower insulating films are automatically adjusted to form a fine connection hole in which the disconnection of the second wiring layer having a large opening area at the upper portion does not easily occur. A method of manufacturing a semiconductor device, comprising: