JPH09330928A - Formation of wiring layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring layer forming method by which the recent demand for making semiconductor elements finer in size can be met sufficiently without increasing the number of processes so much nor requiring the introduction of any new manufacturing facility and suppressing the rise of the manufacturing cost. SOLUTION: At the time of forming a groove 21 for wiring layer into an interlayer insulating film 12 formed on a semiconductor substrate 11, the bottom section of the groove 21 is rounded by successively performing anisotropic etching and isotropic etching. In addition, the opening of a groove 31 and its vicinity are also made round by forming an insulating film 32 on the side walls and bottom of the groove 21 by using the CVD method.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for forming a wiring layer,
In particular, the present invention relates to a method for forming a wiring layer in which a conductive film is embedded in an interlayer insulating film to form a wiring layer.

[0002]

2. Description of the Related Art In order to connect various elements formed on a semiconductor substrate, a technique of forming a wiring layer by a conductive film in an insulating film formed on a semiconductor substrate has been generalized.
These techniques will be described below with reference to the drawings.

First, as shown in FIG. 2A, Al is formed on the surface of an interlayer insulating film 112 formed on a semiconductor substrate 111.
A conductive film 113 made of Al alloy or the like is formed by a sputtering method or the like. Next, as shown in FIG. 2B, a resist pattern (not shown) is formed on the conductive film 113 by PEP (Photo Engraving Process), and the conductive film 113 is patterned by etching using this as a mask to form wiring. The layer 121 is formed. Next, as shown in FIG. 2C, CVD is performed on the surface of the wiring layer 121 and the surface of the interlayer insulating film 112.
The interlayer insulating film 131 is formed by a (Chemical Vapor Deposition) method or the like. Next, although not shown, the interlayer insulating film 1
31 The surface is flattened. This wiring layer forming method is the most widely used technology at present. However,
With the recent miniaturization of semiconductor devices, fine patterns have been formed with high density on a semiconductor substrate.
Further, wiring layers are formed in multiple layers on the semiconductor substrate. For this reason, it is becoming difficult to sufficiently flatten the interlayer insulating film with the above technique, and due to the influence of the unevenness on the surface of these wiring layers, deterioration of insulation between wiring layers, stress migration resistance, and electron migration resistance Of the wiring layer may deteriorate and the reliability of the wiring layer may decrease.

Therefore, in recent years, the following techniques have been studied. First, as shown in FIG. 3A, PE is formed on the interlayer insulating film 212 formed on the semiconductor substrate 211.
A resist pattern (not shown) is formed using P, and a wiring layer groove 213 for forming a wiring layer is formed in the interlayer insulating film 212 using the resist pattern as a mask. Next, as shown in FIG. 3B, a conductive film 221 such as Al or Al alloy is formed by the sputtering method so as to be completely buried in the wiring layer groove 213 by the sputtering method. Next, as shown in FIG.
Etching back or a CMP (Chemical Mechanical Polish) method with a good selection ratio between the insulating film and the conductive film 221 is performed to form the wiring layer 231 only in the wiring layer groove 213. Next, CV is formed on the surfaces of the wiring layer 231 and the insulating film 212.
The interlayer insulating film 232 is formed by the D method or the like.

According to this method, the flatness of the interlayer insulating film is improved and the wiring layers can be easily formed in multiple layers, as compared with the method of patterning and forming the wiring layers. However, vapor deposition of Al or Al alloy by the sputtering method does not provide sufficient coverage, so that it is difficult to completely fill the fine wiring layer trench with a particularly high aspect ratio, and a void may occur in the wiring layer. Therefore, there is a concern that the resistance value of the wiring layer may be varied, the stress migration resistance may deteriorate, the electron migration resistance may deteriorate, and the reliability of the wiring layer may decrease.

Therefore, when sputtering is performed, Al or Al
Techniques for forming Al or an Al alloy by using a technique of forming an alloy while melting or a CVD method having a better coverage than a sputtering method have been developed. Needs to be heated in advance to about 400 to 500 degrees Celsius, and in the case of the CVD method, it is necessary to add existing equipment. That is, in these methods, the introduction of a new sputtering apparatus or CVD apparatus and the increase in the number of steps are indispensable, which causes a problem of increasing the manufacturing cost.

[0007]

As described above, according to the conventional method of manufacturing the wiring layer, the insulation property between the wiring layers is deteriorated, and the stress migration and the electron migration resistance are accompanied by the recent miniaturization of the semiconductor element. There is a concern that the reliability of the wiring layer will be deteriorated due to the deterioration of In order to deal with these problems, new technologies are being developed, but with these technologies, in addition to existing manufacturing equipment,
It is necessary to introduce new equipment and increase the number of processes, which inevitably leads to an increase in cost.

In view of these problems, the present invention has been proposed for the miniaturization of semiconductor elements in recent years, while not increasing the number of steps so much and suppressing the increase in manufacturing cost without introducing new manufacturing equipment. It is intended to provide a method of forming a wiring layer which can sufficiently deal with the problem.

[0009]

The present invention uses the following means in order to solve the above problems. That is, a step of forming a mask having an opening on the surface of the first insulating film on the semiconductor substrate, and a step of etching the first insulating film by anisotropic etching using the mask to form a wiring layer groove. Then, the step of etching the wiring layer groove surface by isotropic etching to make the wiring layer groove a curved surface, the step of removing the mask, and the first insulating film surface by a vapor phase growth method. And a step of forming a conductive film on the surface of the second insulating film, and a step of leaving the conductive film only inside the wiring layer groove. To do.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. First, as shown in FIG. 1A, an interlayer insulating film 12 having a film thickness of about 2 μm, for example, a PSG (Phosph Silicate Glass) film or a laminated film of oxide films is formed on a semiconductor substrate 11. Next, a photoresist is formed on the surface of the interlayer insulating film 12, an opening is formed in a region where a wiring layer groove is to be formed, and a resist mask 13 is formed. The opening width of the resist mask is set to about 0.8 μm in consideration of the opening width of the wiring layer groove.

Subsequently, as shown in FIG. 1B, a wiring layer trench 21 having a depth of about 0.6 μm is formed in the interlayer insulating film 12 by anisotropic etching using the resist mask 13 as a mask. Since anisotropic etching was used,
The wiring layer groove 21 has a rectangular cross section.

Subsequently, as shown in FIG. 1C, subsequent to the previous step, the surface of the wiring layer groove 21 formed in the interlayer insulating film 12 by the isotropic etching method with the resist mask remaining. Is further etched by about 0.4 μm. By this step, the wiring layer groove 21 formed in a square shape is formed.
The cross section can be rounded. Further, with respect to the opening width of the resist mask 13 of 0.8 μm, the dimension conversion difference of the formed wiring layer groove is about 0.4 μm.

Subsequently, as shown in FIG. 1D, the resist mask 13 is removed by ashing. In this state, an edge 31 is formed near the opening above the wiring layer groove 21. Next, an insulating film 32 having a thickness of about 0.4 μm, for example, an oxide film is formed on the surface of the interlayer insulating film 12 by the CVD method. As a result, the vicinity of the opening of the wiring layer groove 21 can be rounded. Further, the formation of the insulating film 32 can eliminate the dimensional conversion difference.

Although not shown, in order to establish electrical continuity with other wiring layers formed under the wiring layer groove 21 and elements formed on the semiconductor substrate, insulation is performed after this step is completed. Via holes and contact holes are opened in the film 32 and the interlayer insulating film 12.

Subsequently, as shown in FIG. 1E, Al or Al alloy having a film thickness of about 1.0 μm (for example, Si is 1.0%, so as to fill the inside of the wiring layer groove 21).
A conductive film 41 such as Al) containing 0.5% Cu is formed by the sputtering method.

According to the present invention, since the bottom portion of the wiring layer groove 21 formed in the insulating film is rounded, and the opening portion is also rounded, a void is formed even by the sputtering method. Instead, the conductive film 41 is formed in the wiring layer groove 21.
It is possible to completely embed with.

When it is necessary to surely bury the conductive film 41 in the wiring layer groove 21, the semiconductor substrate is preliminarily set to 400 degrees Celsius at the time of sputtering, as in the conventional case.
A technique may be used in which Al or an Al alloy is melted while being heated to about 500 to 500 degrees. In this case, it is necessary to introduce new equipment as pointed out in the prior art, but since the wiring layer groove has a rounded shape,
It becomes possible to bury the conductive film 41 in the wiring layer groove 21 with higher reliability than before.

Subsequently, as shown in FIG. 1F, in order to leave the conductive film only in the wiring layer groove 21, the conductive film 41 is formed.
A photoresist 51 having the same etching selection ratio as the conductive film 41 is formed on the surface.

Subsequently, as shown in FIG. 1G, the conductive film 4 is formed.
1 and the photoresist 51 are etched back (resist etch back method) on the conductive film 41 formed in the regions other than the photoresist 51 and the wiring layer groove 41 by using an etching liquid having an etching selection ratio of approximately 1 to the wiring layer 61. To form. As a result, the wiring layer 61 can be formed without causing unevenness on the surface.
Can be formed.

For etching back the conductive film 41, a CMP method may be used in addition to the above method. In this case, it is not necessary to form the photoresist 51, and the progress of the CMP technique makes it possible to perform resist etching. It becomes possible to flatten more than when the back method is used. Furthermore, when the conductive film 41 is formed while being melted during the formation of the conductive film 41, the conductive film 41 can be planarized and formed on the surface of the insulating film 32. Therefore, this is etched back (blanket etch back method). ) Method may be used.

Subsequently, as shown in FIG. 1H, the wiring layer 6
1. An interlayer insulating film 71 is formed on the surface of the insulating film 32 by the CVD method or the like. Through the above steps, the wiring layer forming step according to the embodiment of the present invention is completed.

The present invention can be implemented in various modes without departing from the spirit of the present invention.
For example, in the above embodiment, the resist mask 1
3 has an opening width of 0.8 μm, and the wiring layer groove 21 formed by anisotropic etching using this resist mask as a mask is further 0.4 μm by further isotropic etching.
By extending m and forming the insulating film 32 with a film thickness of about 0.4 μm in the wiring layer groove, the dimensional conversion difference with respect to the resist mask 13 is finally eliminated. However, the amount of etching by the isotropic etching and the insulating film 32
Does not have to be the same as the film thickness of the resist layer, and the opening width of the resist mask 13, the etching amount of isotropic etching, and the insulating film 32 may be determined based on the opening width of the wiring layer groove to be finally formed. .

Besides, the film thickness and type of each film are not limited to those shown in the above embodiment. According to the present invention, when the wiring layer groove is formed in the interlayer insulating film formed on the semiconductor substrate, the wiring layer groove is formed by first performing anisotropic etching and then performing isotropic etching. Round the bottom of the. Further, by forming an insulating film in the wiring layer groove by the CVD method, the wiring layer groove is rounded near the opening. As a result, the inside of the wiring layer groove can be completely filled with the conductive film by using the conventional sputtering method. Therefore, it is possible to solve problems such as deterioration of insulation between wiring layers due to unevenness of the wiring layer, stress migration resistance, deterioration of electron migration resistance, etc., and to form the wiring layer in the interlayer insulating film with high reliability. be able to. Furthermore, it is possible to carry out the above-described embodiment without the need to introduce new manufacturing equipment, and it is possible to suppress an increase in manufacturing cost.

[0024]

According to the present invention, the wiring layer can be completely filled with the conductive film in order to form the wiring layer by using the conventional sputtering method with only a slight increase in the number of steps. It will be possible. Therefore, it is possible to solve problems such as deterioration of insulation between wiring layers due to unevenness of the wiring layer, stress migration resistance, deterioration of electron migration resistance, etc., and to form the wiring layer in the interlayer insulating film with high reliability. be able to. Furthermore, it is possible to carry out the above-described embodiment without the need to introduce new manufacturing equipment, and it is possible to suppress an increase in manufacturing cost.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view illustrating an embodiment of the present invention.

FIG. 2 is a process sectional view illustrating a conventional manufacturing method.

FIG. 3 is a process sectional view illustrating a conventional manufacturing method.

[Explanation of symbols]

11, 111, 211 semiconductor substrate 12, 71, 112, 131, 212, 232 interlayer insulating film 13 resist mask 21, 213 wiring layer groove 31 edge 32 insulating film 41, 113, 221 conductive film 51 photoresist 61, 121, 231 wiring layer

Claims (6)

[Claims] 1. A step of forming a mask having an opening on the surface of a first insulating film on a semiconductor substrate; and using the mask, the first insulating film is etched by anisotropic etching to form a wiring layer groove. Forming step, and thereafter, etching the wiring layer groove surface by isotropic etching to make the wiring layer groove a curved surface; removing the mask; and forming the first layer by vapor phase epitaxy. And a step of forming a second insulating film on the surface of the insulating film, a step of forming a conductive film on the surface of the second insulating film, and a step of leaving the conductive film only inside the trench for the wiring layer. And a method for forming a wiring layer. 2. The step of leaving the conductive film only inside the expanded wiring layer groove is performed by removing the conductive film formed on the surface of the second insulating film by a CMP method. The method for forming a wiring layer according to claim 1, wherein: 3. The step of leaving the conductive film only inside the expanded wiring layer groove includes the step of forming a photoresist on the surface of the conductive film, the conductive film, the photoresist and the conductive material. 2. The method for forming a wiring layer according to claim 1, further comprising the step of performing etching under the condition that the etching selection ratio with respect to the film is substantially the same. 4. The formation of a wiring layer according to claim 1, wherein the step of forming a conductive film on the surface of the second insulating film is performed by heating the semiconductor substrate to a melting point of the conductive film. Method. 5. The method for forming a wiring layer according to claim 1, wherein the step of forming the conductive film on the surface of the second insulating film is performed by a sputtering method. 6. A step of forming a wiring layer groove having a curved surface at the bottom in a first insulating film formed on a semiconductor substrate, and a second step on the surface of the first insulating film including the wiring layer groove surface. A wiring comprising: a step of forming an insulating film and making the wiring layer groove opening curved; and a step of burying a conductive film in the wiring layer groove in which the second insulating film is formed. Method of forming layer.