JPH05121531A - Carrier for semiconductor wafer - Google Patents

Carrier for semiconductor wafer

Info

Publication number
JPH05121531A
JPH05121531A JP9614992A JP9614992A JPH05121531A JP H05121531 A JPH05121531 A JP H05121531A JP 9614992 A JP9614992 A JP 9614992A JP 9614992 A JP9614992 A JP 9614992A JP H05121531 A JPH05121531 A JP H05121531A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
groove
carrier
grooves
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9614992A
Other languages
Japanese (ja)
Other versions
JP3263856B2 (en
Inventor
Shinobu Hidaka
忍 日高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP9614992A priority Critical patent/JP3263856B2/en
Publication of JPH05121531A publication Critical patent/JPH05121531A/en
Application granted granted Critical
Publication of JP3263856B2 publication Critical patent/JP3263856B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Packaging For Recording Disks (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

PURPOSE:To surely and easily perform the insertion operation of semiconductor wafer into a carrier for semiconductor wafer use. CONSTITUTION:A carrier is featured in the following manner: a plurality of grooves 4 for semiconductor water insertion use are formed, so as to be faced with each other, in individual inner faces of sidewalls 2, 3 which are faced with each other; the grooves 4 on both inner faces are divided into a plurality of regions; and groove discrimination marks 11 whose shape, size and/or color are different form those of adjacent regions are put on individual guards 7, 8 near groove numbers 9 at the individual grooves 4 in the individual regions. Thereby, it is possible to prevent the erroneous insertion operation of a semiconductor wafer 5 into the carrier 1, the efficiency of the insertion operation of the semiconductor wafer 5 is enhanced, and the fatigue of an operator can be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体ウエハの挿入
作業が行い易い半導体ウエハ用キャリヤ(以下、単に
「キャリヤ」と記す)に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer carrier (hereinafter, simply referred to as "carrier") for facilitating semiconductor wafer insertion work.

【0002】[0002]

【従来の技術】従来のキャリヤの一例を図8を用いて説
明する。この図はキャリヤの一部斜視図である。符号1
は全体としてキャリヤを示す。このキャリヤ1は直方体
の箱型で構成されており、その一対の相対向する側壁2
及び3のそれぞれの内面には、等間隔で平行な、複数の
細長い半導体ウエハ挿入用溝(以下、単に「溝」と記
す)4が形成されている。これらの溝4は、挿入された
半導体ウエハ5を等間隔で保持する役目をする。この図
8において、キャリヤ1の上部開口部6の前記側壁2及
び3に一体的に、それぞれ鍔7及び8が形成されてい
て、それぞれの側壁2及び3に形成された、前記複数の
溝4の近傍に、それぞれ同一順序で、溝番号9が付され
ている。
2. Description of the Related Art An example of a conventional carrier will be described with reference to FIG. This figure is a partial perspective view of the carrier. Code 1
Indicates a carrier as a whole. The carrier 1 has a rectangular parallelepiped box shape, and a pair of opposing side walls 2 thereof.
A plurality of elongated semiconductor wafer insertion grooves (hereinafter, simply referred to as “grooves”) 4 are formed on the inner surfaces of 3 and 3 in parallel at equal intervals. These grooves 4 serve to hold the inserted semiconductor wafers 5 at equal intervals. In FIG. 8, collars 7 and 8 are formed integrally with the side walls 2 and 3 of the upper opening 6 of the carrier 1, respectively, and the plurality of grooves 4 formed in the side walls 2 and 3, respectively. The groove number 9 is given in the same order in the vicinity of each.

【0003】このような構成のキャリヤ1に、作業者が
半導体ウエハ5を挿入する場合、作業者は真空ピンセッ
ト10で保持している半導体ウエハ5を、溝番号9、例
えば、22番の溝4へ挿入しようとして、作業者の手前
側にある、例えば、図8では鍔8に付されてある溝番号
9の22番を拠り所にして、先ず、矢印Aの方に半導体
ウエハ5を持ちきたし、側壁3の内面に形成されてい
る、その22番目の溝4に半導体ウエハ5を嵌め込み、
次に、矢印Bの方に視点を移して、向こう側の溝番号9
の22番を拠り所にして、溝4にその半導体ウエハ5の
向こう側の縁を嵌め込み、その半導体ウエハ5を挿入す
る。
When an operator inserts the semiconductor wafer 5 into the carrier 1 having such a structure, the operator holds the semiconductor wafer 5 held by the vacuum tweezers 10 in the groove number 9, for example, the groove 4 in the number 4. In order to insert the semiconductor wafer 5 into the front side of the operator, for example, based on No. 22 of the groove number 9 attached to the collar 8 in FIG. The semiconductor wafer 5 is fitted into the 22nd groove 4 formed on the inner surface of the side wall 3,
Next, move the viewpoint to arrow B, and the groove number 9 on the other side.
No. 22 is used as a base, and the edge of the semiconductor wafer 5 on the other side is fitted into the groove 4, and the semiconductor wafer 5 is inserted.

【0004】[0004]

【発明が解決しようとする課題】以上に記した作業手順
で、順次、半導体ウエハ5をキャリヤ1に挿入するので
あるが、溝番号9が非常に見にくいために、作業者はそ
の読み取りに神経を集中しなければならず、作業者の疲
労度は大変大きくなる。また、半導体ウエハ5の縁を溝
4に嵌め込む作業に移る時には、視点を半導体ウエハ5
の縁と溝番号9の両方を交互に切替えるため、溝番号9
を見失ったり、見間違えたりして、隣の溝4へ半導体ウ
エハ5の縁を嵌め込んでしまうことがある。半導体ウエ
ハ5の口径が大口径化してきた現在、この半導体ウエハ
5の挿入作業は、ますます作業者に負担を強いることに
なり、誤った溝4に嵌め込み易くなる。この発明は、こ
のような欠点を解消し、半導体ウエハ5をキャリヤ1の
所定の溝4に正確に、しかも容易に、挿入できるように
したものである。
The semiconductor wafer 5 is sequentially inserted into the carrier 1 by the above-described work procedure. However, since the groove number 9 is very difficult to see, the operator is sensitive to the reading. It is necessary to concentrate, and the fatigue level of the operator becomes very large. Further, when the process of fitting the edge of the semiconductor wafer 5 into the groove 4 is started, the viewpoint is changed to the semiconductor wafer 5.
Since both the edge and the groove number 9 are switched alternately, the groove number 9
There is a case where the edge of the semiconductor wafer 5 is fitted into the adjacent groove 4 due to a loss of sight or a mistake in mistake. Now that the diameter of the semiconductor wafer 5 has become larger, the work of inserting the semiconductor wafer 5 is becoming more and more burdensome to the operator, and the semiconductor wafer 5 is easily fitted into the wrong groove 4. The present invention eliminates such drawbacks and enables the semiconductor wafer 5 to be inserted into the predetermined groove 4 of the carrier 1 accurately and easily.

【0005】[0005]

【課題を解決するための手段】そのため、この発明は、
前記相対向する側壁のそれぞれに形成されたそれら双方
の溝を複数の領域に分け、各領域毎に、隣接する領域と
は異なる大きさ、形状及び又は色彩の溝識別印を相対向
するそれぞれの溝の近傍に付して、前記欠点を解決し
た。
Therefore, the present invention provides
Each of the grooves formed on each of the opposite sidewalls is divided into a plurality of regions, and each region has a groove identification mark having a size, shape, and / or color different from that of the adjacent region. It was attached near the groove to solve the above-mentioned drawback.

【0006】[0006]

【作用】従って、この発明により、キャリヤへの半導体
ウエハの挿入作業ミスを防止することができ、半導体ウ
エハの挿入作業の効率が向上し、しかも作業者の疲労を
軽減できる。
According to the present invention, therefore, it is possible to prevent mistakes in the work of inserting the semiconductor wafer into the carrier, improve the efficiency of the work of inserting the semiconductor wafer, and reduce the fatigue of the worker.

【0007】[0007]

【実施例】以下、この発明の実施例を図面を用いて説明
する。図1乃至図7はそれぞれこの発明の第1乃至第7
の実施例であるキャリヤの一部斜視図である。なお、図
8の従来のキャリヤの構成部分と同一の構成部分には、
同一の符号を付し、それらの構成等の説明は省略する。
Embodiments of the present invention will be described below with reference to the drawings. 1 to 7 are first to seventh embodiments of the present invention, respectively.
FIG. 3 is a partial perspective view of a carrier that is an embodiment of the present invention. The same components as those of the conventional carrier shown in FIG.
The same reference numerals are given and the description of their configuration and the like is omitted.

【0008】先ず、図1を用いてこの発明の第1の実施
例であるキャリヤ1の構成を説明する。この図には、そ
の各側壁の内面に、それぞれ25本の溝43が形成され
たキャリヤ1が示されている。このような多数の溝4
を、例えば、5個の領域に分割し、各領域において、溝
番号9の近傍で、その内側、即ち、溝4に近い方に、5
種類の大きさの異なる、黒塗り三角の溝識別印11を、
各溝4に対応して、手前側の鍔8と向こう側の鍔7に1
個づつ、周期的に並べて付した。
First, the structure of the carrier 1 according to the first embodiment of the present invention will be described with reference to FIG. This figure shows a carrier 1 having 25 grooves 43 formed on the inner surface of each side wall thereof. Such many grooves 4
Is divided into, for example, 5 regions, and in each region, in the vicinity of the groove number 9 and inside thereof, that is, in the direction closer to the groove 4,
Black-painted triangular groove identification marks 11 of different sizes,
Corresponding to each groove 4, 1 on the front side collar 8 and the other side collar 7
Each piece was placed side by side periodically.

【0009】図2に示したこの発明の第2の実施例で
は、図1の前記黒塗り三角の溝識別印11の代わりに、
図示したような、形状が異なる5種類の模様の溝識別印
11Aを、各溝4に対応して、手前側の鍔8と向こう側
の鍔7に1個づつ、周期的に並べて付した。
In the second embodiment of the present invention shown in FIG. 2, instead of the black-painted triangular groove identifying mark 11 of FIG.
As shown in the figure, groove identification marks 11A of five different patterns having different shapes are provided in a periodic manner, one for the front flange 8 and one for the other flange 7, corresponding to each groove 4.

【0010】図3に示したこの発明の第3の実施例で
は、図1の前記黒塗り三角の溝識別印11の代わりに、
図示したような、5個形状は同一であるが、大きさが順
次異なる5種類の模様の溝識別印11Bを、各溝4に対
応して、手前側の鍔8と向こう側の鍔7に1個づつ、周
期的に並べて付した。
In the third embodiment of the present invention shown in FIG. 3, instead of the black-painted triangular groove identifying mark 11 of FIG.
As shown in the figure, five types of groove identification marks 11B having the same shape but different sizes in sequence are provided on the front side brim 8 and the other side brim 7 corresponding to each groove 4. They were attached one by one periodically.

【0011】図4に示したこの発明の第4の実施例で
は、5個に分割した各領域内の5個の溝識別印11Cを
全てそれらの形状、大きさ及び色彩を同一にし、隣接す
る領域の溝識別印11Cと形状、大きさ及び色彩を異な
らせたものである。
In the fourth embodiment of the present invention shown in FIG. 4, all of the five groove identification marks 11C in each of the five divided regions have the same shape, size and color and are adjacent to each other. The shape, size, and color are different from the groove identification mark 11C in the area.

【0012】図5に示したこの発明の第5の実施例で
は、5個に分割した各領域内の5個の溝識別印11Dを
全てそれらの形状、大きさ及び色彩を同一にし、それら
は隣接する領域の溝識別印11Dの形状、大きさは同一
であるが、色彩のみを異ならせたものである。
In the fifth embodiment of the present invention shown in FIG. 5, all the five groove identification marks 11D in each of the five divided areas have the same shape, size and color, and they are the same. The groove identification marks 11D in the adjacent regions have the same shape and size, but are different only in color.

【0013】図6に示したこの発明の第6の実施例で
は、全体の溝4を6個の領域に分割し、各領域に、隣接
する領域とは形状、或いは大きさ、或いはその双方が異
なるが、色彩が同一の溝識別印11Eを付した。即ち、
各領域内の溝識別印11Eは形状、大きさ、色彩共に同
一である。
In the sixth embodiment of the present invention shown in FIG. 6, the entire groove 4 is divided into six regions, and each region has a shape, a size, or both as an adjacent region. Although different, the groove identification mark 11E having the same color was attached. That is,
The groove identification mark 11E in each area has the same shape, size, and color.

【0014】図7に示したこの発明の第7の実施例で
は、5個に分割した各領域内には、隣接する領域とは形
状、或いは大きさ、或いはその双方が異なるが、色彩は
同一の溝識別印11Fを付した。そして各領域内の溝識
別印11Fは5個とも形状は同一であるが、大きさが順
次異なるものである。
In the seventh embodiment of the present invention shown in FIG. 7, in each of the five divided areas, the shape and / or the size are different from the adjacent areas, but the colors are the same. The groove identification mark 11F was attached. The five groove identification marks 11F in each region have the same shape, but their sizes are sequentially different.

【0015】このような溝識別印11(11A、11
B、11C、11D、11E、11F以下同様)を付す
と、作業者が向こう側の溝識別印11と半導体ウエハ5
の縁の両方に交互に視点を切り換える場合、一度目を離
した溝識別印11を再び確認する際には、溝識別情報を
利用することができる。複数の溝を所定の領域に分割し
たので、今探そうとしている溝識別印11のおおよその
位置が、その近傍の溝識別印から容易に推定することが
できる。
Such a groove identification mark 11 (11A, 11
B, 11C, 11D, 11E, 11F and so on), the worker identifies the groove identification mark 11 and the semiconductor wafer 5 on the other side.
When the viewpoints are alternately switched to both edges of the groove, the groove identification information can be used when re-checking the groove identification mark 11 which has been released once. Since the plurality of grooves are divided into predetermined regions, the approximate position of the groove identification mark 11 to be searched now can be easily estimated from the groove identification mark in the vicinity thereof.

【0016】つまり、25個のような多数ある溝の中か
ら所望の1個の溝を特定することは難しいが、前記各実
施例に示したように、5個のような狭い範囲の領域の溝
の中から所望の1個の溝を特定することは簡単である。
即ち、この発明の溝識別印は、目で探さないといけない
範囲を狭めるためのもの、或いは所望の溝を探すための
基準となる溝を瞬時に特定できるようにしたものであ
る。
That is, it is difficult to specify a desired one groove from a large number of grooves such as 25 grooves, but as shown in each of the above-mentioned embodiments, it is possible to specify a narrow area such as 5 grooves. Identifying the desired single groove from among the grooves is straightforward.
That is, the groove identification mark of the present invention is for narrowing the range that must be searched by the eye, or for enabling instantaneous identification of the groove serving as a reference for searching for a desired groove.

【0017】また、細かい文字を確認するのではなく、
記号の大きさ、形状の違い、色彩の種類を確認するだけ
でよいので、求める溝識別印11とその両隣の溝識別印
11との判別は容易であり、最終的に1個の記号を容易
に探し出すことができる。
Also, instead of checking the fine characters,
Since it is only necessary to check the size and shape of the symbols and the type of color, it is easy to distinguish between the groove identification mark 11 to be obtained and the groove identification marks 11 on both sides of the groove identification mark 11 and finally one symbol. Can be found in.

【0018】[0018]

【発明の効果】以上のように、この発明のキャリヤによ
れば、そのキャリヤへの半導体ウエハの挿入作業ミスを
防止することができ、半導体ウエハの挿入作業の効率が
向上し、しかも作業者の疲労を軽減できる等の優れた効
果がある。
As described above, according to the carrier of the present invention, it is possible to prevent a mistake in the work of inserting a semiconductor wafer into the carrier, improve the efficiency of the work of inserting the semiconductor wafer, and moreover the operator It has excellent effects such as reducing fatigue.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の第1の実施例である半導体ウエハ用
キャリヤの一部斜視図である。
FIG. 1 is a partial perspective view of a semiconductor wafer carrier according to a first embodiment of the present invention.

【図2】この発明の第2の実施例である半導体ウエハ用
キャリヤの一部斜視図である。
FIG. 2 is a partial perspective view of a semiconductor wafer carrier according to a second embodiment of the present invention.

【図3】この発明の第3の実施例である半導体ウエハ用
キャリヤの一部斜視図である。
FIG. 3 is a partial perspective view of a semiconductor wafer carrier according to a third embodiment of the present invention.

【図4】この発明の第4の実施例である半導体ウエハ用
キャリヤの一部斜視図である。
FIG. 4 is a partial perspective view of a semiconductor wafer carrier according to a fourth embodiment of the present invention.

【図5】この発明の第5の実施例である半導体ウエハ用
キャリヤの一部斜視図である。
FIG. 5 is a partial perspective view of a semiconductor wafer carrier according to a fifth embodiment of the present invention.

【図6】この発明の第6の実施例である半導体ウエハ用
キャリヤの一部斜視図である。
FIG. 6 is a partial perspective view of a semiconductor wafer carrier according to a sixth embodiment of the present invention.

【図7】この発明の第7の実施例である半導体ウエハ用
キャリヤの一部斜視図である。
FIG. 7 is a partial perspective view of a semiconductor wafer carrier according to a seventh embodiment of the present invention.

【図8】従来の半導体ウエハ用キャリヤの一部斜視図で
ある。
FIG. 8 is a partial perspective view of a conventional semiconductor wafer carrier.

【符号の説明】[Explanation of symbols]

1 半導体ウエハ用キャリヤ 2 側壁 3 側壁 4 半導体ウエハ挿入用溝(溝) 5 半導体ウエハ 6 開口部 7 鍔 8 鍔 9 溝番号 10 真空ピンセット 11 溝識別印11 DESCRIPTION OF SYMBOLS 1 Carrier for semiconductor wafer 2 Side wall 3 Side wall 4 Semiconductor wafer insertion groove (groove) 5 Semiconductor wafer 6 Opening 7 Tsuba 8 Tsuba 9 Groove number 10 Vacuum tweezers 11 Groove identification mark 11

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】相対向する側壁のそれぞれの内面に、複数
の半導体ウエハ挿入用溝をそれぞれ相対向して形成し、
それら双方の半導体ウエハ挿入用溝を複数の領域に分
け、各領域毎に、隣接する領域とは異なる大きさ、形状
及び又は色彩の溝識別印を相対向するそれぞれの半導体
ウエハ挿入用溝の近傍に付したことを特徴とする半導体
ウエハ用キャリヤ。
1. A plurality of semiconductor wafer insertion grooves are formed on respective inner surfaces of opposed side walls so as to oppose each other.
Both of these semiconductor wafer insertion grooves are divided into a plurality of areas, and in each area, a groove identification mark having a size, shape, and / or color different from that of the adjacent area is provided in the vicinity of each semiconductor wafer insertion groove that faces each other. A carrier for a semiconductor wafer, characterized by being attached to.
【請求項2】前記半導体ウエハ用溝の溝番号が前記側壁
で形成された開口部に相対して形成された鍔に付されて
おり、前記溝識別印を前記溝番号より前記開口部に近
い、前記半導体ウエハ挿入用溝の近傍に付したことを特
徴とする請求項1に記載の半導体ウエハ用キャリヤ。
2. The groove number of the semiconductor wafer groove is attached to a collar formed facing the opening formed in the side wall, and the groove identification mark is closer to the opening than the groove number. The carrier for semiconductor wafer according to claim 1, wherein the carrier is provided near the groove for inserting the semiconductor wafer.
【請求項3】前記各領域の内、少なくとも1つの領域は
2つ以上の半導体ウエハ挿入用溝からなることを特徴と
する請求項1に記載の半導体ウエハ用キャリヤ。
3. The carrier for a semiconductor wafer according to claim 1, wherein at least one of the regions comprises two or more semiconductor wafer insertion grooves.
JP9614992A 1991-09-02 1992-04-16 Carrier for semiconductor wafer Expired - Fee Related JP3263856B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9614992A JP3263856B2 (en) 1991-09-02 1992-04-16 Carrier for semiconductor wafer

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP22169491 1991-09-02
JP3-221694 1991-09-02
JP9614992A JP3263856B2 (en) 1991-09-02 1992-04-16 Carrier for semiconductor wafer

Publications (2)

Publication Number Publication Date
JPH05121531A true JPH05121531A (en) 1993-05-18
JP3263856B2 JP3263856B2 (en) 2002-03-11

Family

ID=26437366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9614992A Expired - Fee Related JP3263856B2 (en) 1991-09-02 1992-04-16 Carrier for semiconductor wafer

Country Status (1)

Country Link
JP (1) JP3263856B2 (en)

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CN100462291C (en) * 2005-06-08 2009-02-18 株式会社东芝 Electronic component tray and identification method of similar electronic component tray
JP2014113649A (en) * 2012-12-07 2014-06-26 Daihen Corp Robot teaching method, transport method, and transport system
JP2015050401A (en) * 2013-09-04 2015-03-16 株式会社ディスコ Cassette
JP2020136614A (en) * 2019-02-25 2020-08-31 住友金属鉱山株式会社 Wafer case jig

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JP2001354280A (en) * 2000-06-12 2001-12-25 Nix Inc Plate material storing frame
JP2005320033A (en) * 2004-05-10 2005-11-17 Daiwa Shinku:Kk Conveying container of liquid crystal panel with lead pin
CN100462291C (en) * 2005-06-08 2009-02-18 株式会社东芝 Electronic component tray and identification method of similar electronic component tray
JP2007273643A (en) * 2006-03-30 2007-10-18 Phyzchemix Corp Wafer cassette and wafer storing method
JP2014113649A (en) * 2012-12-07 2014-06-26 Daihen Corp Robot teaching method, transport method, and transport system
JP2015050401A (en) * 2013-09-04 2015-03-16 株式会社ディスコ Cassette
JP2020136614A (en) * 2019-02-25 2020-08-31 住友金属鉱山株式会社 Wafer case jig

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