JPH05121319A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05121319A JPH05121319A JP13968891A JP13968891A JPH05121319A JP H05121319 A JPH05121319 A JP H05121319A JP 13968891 A JP13968891 A JP 13968891A JP 13968891 A JP13968891 A JP 13968891A JP H05121319 A JPH05121319 A JP H05121319A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- substrate
- silicon single
- oxygen
- epitaxial growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造法に関
し、特に高集積微細化素子で構成される半導体シリコン
基板の回路の電気特性のバラツキを、小さくするために
必要な高品位エピタキシャル基板の製造法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a high-quality epitaxial substrate which is required to reduce variations in electrical characteristics of a circuit of a semiconductor silicon substrate composed of highly integrated miniaturization elements Regarding manufacturing method.
【0002】[0002]
【従来の技術】従来、高集積微細化する半導体集積回路
において、基板の大口径に有利なチョコラルスキー(C
Z)法によって製造されたCZ単結晶から切り出された
シリコン単結晶基板(ウェーハ)では、特定の加熱処理
を施すことにより、基板表面に無欠陥層(Denuded Zon
e)を、この基板内部に結晶欠陥(Bulk Micro Defect:B
MD)を、それぞれ形成している。このBMDにより、半
導体集積回路の製造過程中に侵入する微量の重金属等を
析出させるイントリンシック・ゲッタリング(IG)効
果を積極的に利用し、歩留まりの向上を図っている。2. Description of the Related Art Conventionally, in a semiconductor integrated circuit which is highly integrated and miniaturized, Czochralski (C
In a silicon single crystal substrate (wafer) cut out from a CZ single crystal manufactured by the Z) method, a defect-free layer (Denuded Zon) is formed on the substrate surface by performing a specific heat treatment.
e) crystal defects (Bulk Micro Defect: B
MD) are formed respectively. This BMD positively utilizes the intrinsic gettering (IG) effect of precipitating a trace amount of heavy metals and the like that enter during the manufacturing process of the semiconductor integrated circuit, thereby improving the yield.
【0003】[0003]
【発明が解決しようとする課題】IG効果では、シリコ
ン単結晶基板中に含有されている酸素([Oi]:格子
間に存在する酸素)濃度が関連する。すなわち、結晶成
長時、坩堝や雰囲気から混入し、シリコン中に溶解して
いる過剰の酸素は、熱処理によって結晶内部に析出し、
その析出部の周囲に結晶欠陥を形成する。この形成によ
り、結晶格子に歪が生じ、この歪場を利用して重金属等
が析出するようになるものである。The IG effect is related to the concentration of oxygen ([Oi]: oxygen existing between the lattices) contained in the silicon single crystal substrate. That is, during crystal growth, excess oxygen mixed in from the crucible or the atmosphere and dissolved in silicon is precipitated inside the crystal by heat treatment,
Crystal defects are formed around the deposited portion. This formation causes strain in the crystal lattice, and heavy metal or the like is deposited by utilizing this strain field.
【0004】ところが、このIG効果を高めるため、酸
素[Oi]析出核を高密度に形成させると、残留酸素
[Oi]が少なくなり、シリコン単結晶基板の機械的強
度が弱くなってしまう。例えば、半導体集積回路の製造
工程中の熱処理では、デバイス回路の電気的活性領域に
まで転位欠陥が発生し、結晶特性が悪くなった。そのた
め、デバイス特性を損なうことがないように、IG効果
を狭い範囲で、制御しなければならなかった。However, if oxygen [Oi] precipitation nuclei are formed at a high density in order to enhance the IG effect, the residual oxygen [Oi] is reduced and the mechanical strength of the silicon single crystal substrate becomes weak. For example, in the heat treatment during the manufacturing process of the semiconductor integrated circuit, dislocation defects are generated even in the electrically active region of the device circuit, and the crystal characteristics deteriorate. Therefore, the IG effect has to be controlled within a narrow range so as not to impair the device characteristics.
【0005】また、高濃度アンチモン不純物を含有する
シリコン単結晶基板に対して、ランピング比を0.1℃
/min以下で低温処理工程をおこなえば、高いIG効
果をもたせることができたが、熱処理炉の占有時間が非
常に長く、コスト的にも半導体装置の量産の製造には適
さなかった。In addition, a ramping ratio of 0.1 ° C. is applied to a silicon single crystal substrate containing a high concentration of antimony impurities.
Although a high temperature IG effect could be obtained if the low temperature treatment step was performed at less than 1 min./min, the occupation time of the heat treatment furnace was very long, and the cost was not suitable for mass production of semiconductor devices.
【0006】本発明の目的は、その機械的強度を損なう
ことなく、高いIG能力を有する単結晶シリコン基板を
安価に提供することにある。An object of the present invention is to provide a single crystal silicon substrate having a high IG capability at low cost without deteriorating its mechanical strength.
【0007】[0007]
【課題を解決するための手段】請求項1に記載の発明
は、高酸素MCZ法で製造したシリコン単結晶より加工
したシリコン単結晶基板上に、シリコン単結晶をエピタ
キシャル成長させる半導体装置の製造法である。According to a first aspect of the present invention, there is provided a semiconductor device manufacturing method in which a silicon single crystal is epitaxially grown on a silicon single crystal substrate processed from a silicon single crystal manufactured by a high oxygen MCZ method. is there.
【0008】また、請求項2に記載の発明は、請求項1
に記載の高酸素MCZシリコン基板中の酸素濃度が、
1.0×1018/cm3以上の場合において、1100℃
以上の高温処理を行った後、エピタキシャル成長を行う
半導体装置の製造法である。The invention described in claim 2 is the same as claim 1
The oxygen concentration in the high oxygen MCZ silicon substrate according to
In the case of 1.0 × 10 18 / cm 3 or more, 1100 ° C
This is a method of manufacturing a semiconductor device in which epitaxial growth is performed after performing the above high-temperature treatment.
【0009】また、請求項3に記載の発明は、請求項1
に記載の製造法において、1100℃以上の高温処理を
行った後、500〜1050℃の範囲の温度で更に熱処
理した後、エピタキシャル成長を行うことを特徴とする
半導体装置の製造法である。The invention described in claim 3 is the same as claim 1
In the manufacturing method described in (1), the semiconductor device is manufactured by performing high temperature treatment at 1100 ° C. or higher, further performing heat treatment at a temperature in the range of 500 to 1050 ° C., and then performing epitaxial growth.
【0010】[0010]
【作用】本発明に係る半導体装置の製造法では、高酸素
MCZ法(高濃度の酸素雰囲気の中で、融液対流を制御
する磁場を設置したCZ法)によってシリコン単結晶を
製造し、このシリコン単結晶から切り出した基板を使用
する。また、この基板中の酸素[Oi]濃度が1.0×1
018/cm3以上の場合は、1100℃以上の高温処理
をおこなう。また、高温処理の後500〜1050℃の
範囲で熱処理をおこなう。この基板は、CZ単結晶基板
に比べて結晶成長縞(ストリエーション)のピッチが密
であるので、エピタキシャル成長後デバイス熱処理をお
こなっても、熱応力発生が小さい。また、ストリエーシ
ョンのないエピタキシャル成長層との間に内部応力
(歪)の発生が小さいため、エピタキシャル成長層にス
リップ・ライン(SL)の発生がない。この結果、デバ
イス製造工程中で熱的機械強度に強く、高いIG能力を
有する基板ができる。In the method of manufacturing a semiconductor device according to the present invention, a silicon single crystal is manufactured by the high oxygen MCZ method (CZ method in which a magnetic field controlling melt convection is set in a high-concentration oxygen atmosphere). A substrate cut out from a silicon single crystal is used. Further, the oxygen [Oi] concentration in this substrate is 1.0 × 1.
In the case of 0 18 / cm 3 or more, high temperature treatment of 1100 ° C. or more is performed. After the high temperature treatment, heat treatment is performed in the range of 500 to 1050 ° C. Since this substrate has a denser pitch of crystal growth stripes (striation) than a CZ single crystal substrate, thermal stress is small even when device heat treatment is performed after epitaxial growth. Further, since the internal stress (strain) is small with respect to the epitaxial growth layer having no striation, no slip line (SL) is generated in the epitaxial growth layer. As a result, a substrate having high thermal mechanical strength and high IG capability can be obtained in the device manufacturing process.
【0011】[0011]
【実施例】実施例1[Example] Example 1
【0012】以下、実施例1を説明する。高い濃度の酸
素雰囲気の中で、シリコン単結晶素材を石英坩堝に入れ
ておいて、加熱によってこの素材を溶かして、融点14
14℃より少し高い温度に保っておく。この融液にシリ
コン単結晶の種子結晶を浸して、十分なじませたのち、
軸と坩堝とを回転させながらゆっくりと引き上げる。こ
の間、磁場を印加することによって、融液の動粘性を高
くした状態で、坩堝との反応を抑制または促進しなが
ら、シリコン単結晶中の酸素濃度を制御する。このよう
にして種子結晶の方位配列をもった円柱状のシリコン単
結晶をうる。このように作った高酸素MCZシリコン単
結晶を、エピタキシャル成長基板として使用する。The first embodiment will be described below. In a high-concentration oxygen atmosphere, put a silicon single crystal material in a quartz crucible, and melt this material by heating to a melting point of 14
Keep at a temperature just above 14 ° C. After immersing the seed crystal of silicon single crystal in this melt and letting it mix well,
Gently pull up while rotating the shaft and crucible. During this time, by applying a magnetic field, the oxygen concentration in the silicon single crystal is controlled while suppressing or accelerating the reaction with the crucible while the kinematic viscosity of the melt is increased. In this way, a columnar silicon single crystal having a seed crystal orientation arrangement is obtained. The high oxygen MCZ silicon single crystal thus produced is used as an epitaxial growth substrate.
【0013】高酸素MCZシリコン単結晶基板の表面
は、CZシリコン単結晶基板より、ストリエーションピ
ッチが小さく、密であるため、面内方向の応力場の発生
が小さい。この基板上に、シリコン単結晶の薄膜をエピ
タキシャル成長させる。更に、半導体装置製造工程にお
ける、熱履歴に近似のシミュレーション熱処理をした
後、ジルトルエッチング液にて選択エッチングすると、
このエピタキシャル成長層中に、スリップラインの発生
がみられない。すなわち、デバイス製造工程中での、熱
的機械強度の強いシリコン基板であることがわかる。Since the surface of the high oxygen MCZ silicon single crystal substrate has a smaller striation pitch and a higher density than the CZ silicon single crystal substrate, the stress field in the in-plane direction is small. A silicon single crystal thin film is epitaxially grown on this substrate. Furthermore, in the semiconductor device manufacturing process, after performing a simulation heat treatment close to the thermal history, if selective etching is performed with a Zirtor etching solution
No slip line is found in this epitaxial growth layer. That is, it can be seen that the silicon substrate has high thermal mechanical strength during the device manufacturing process.
【0014】実施例2Example 2
【0015】以下、実施例2を説明する。実施例1の高
酸素MCZシリコン単結晶に、アンチモンを添加してお
いて作ったN型シリコン単結晶を、エピタキシャル成長
基板として使用する。The second embodiment will be described below. An N-type silicon single crystal prepared by adding antimony to the high oxygen MCZ silicon single crystal of Example 1 is used as an epitaxial growth substrate.
【0016】エピタキシャル成長前に、1200℃の熱
処理した後、550℃〜950℃までの時に950℃の
熱処理の温度上昇速度を0.1℃/minより早くして
熱処理を行う。次に、エピタキシャル成長を行う。更に
実施例1と同じように、デバイス熱処理と選択エッチン
グを行うと、IG層が明確化できる。すなわち高いIG
効果を有するエピタキシャル基板を安価に製造できる。Before the epitaxial growth, after the heat treatment at 1200 ° C., the heat treatment is performed at a temperature of 550 ° C. to 950 ° C. at a temperature rising rate of 950 ° C. higher than 0.1 ° C./min. Next, epitaxial growth is performed. Further, when the device heat treatment and selective etching are performed as in the first embodiment, the IG layer can be clarified. Ie high IG
An epitaxial substrate having an effect can be manufactured at low cost.
【0017】[0017]
【発明の効果】以上説明してきたように、本発明によれ
ば、機械的強度を損なうことなく、高いIG能力を有す
る半導体シリコン基板を安価に製造できる。As described above, according to the present invention, a semiconductor silicon substrate having a high IG capability can be manufactured at low cost without impairing the mechanical strength.
Claims (3)
晶より加工したシリコン単結晶基板上に、シリコン単結
晶をエピタキシャル成長させることを特徴とする半導体
装置の製造法。1. A method of manufacturing a semiconductor device, which comprises epitaxially growing a silicon single crystal on a silicon single crystal substrate processed from a silicon single crystal manufactured by a high oxygen MCZ method.
基板中の酸素濃度が、1.0×1018/cm3以上の場合
において、 1100℃以上の高温処理を行った後、 エピタキシャル成長を行うことを特徴とする半導体装置
の製造法。2. When the oxygen concentration in the high oxygen MCZ silicon substrate according to claim 1 is 1.0 × 10 18 / cm 3 or more, high temperature treatment of 1100 ° C. or more is performed, and then epitaxial growth is performed. A method for manufacturing a semiconductor device, which is characterized by the above.
の製造法。3. The semiconductor device according to claim 1, wherein after high temperature treatment at 1100 ° C. or higher, further heat treatment is performed at a temperature in the range of 500 to 1050 ° C., and then epitaxial growth is performed. Manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3139688A JP2779556B2 (en) | 1991-05-15 | 1991-05-15 | Epitaxial substrate and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3139688A JP2779556B2 (en) | 1991-05-15 | 1991-05-15 | Epitaxial substrate and method for manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05121319A true JPH05121319A (en) | 1993-05-18 |
JP2779556B2 JP2779556B2 (en) | 1998-07-23 |
Family
ID=15251113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3139688A Expired - Lifetime JP2779556B2 (en) | 1991-05-15 | 1991-05-15 | Epitaxial substrate and method for manufacturing the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2779556B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0959154A1 (en) * | 1998-05-22 | 1999-11-24 | Shin-Etsu Handotai Company Limited | A method for producing an epitaxial silicon single crystal wafer and the epitaxial single crystal wafer |
WO2001086710A1 (en) * | 2000-05-09 | 2001-11-15 | Shin-Etsu Handotai Co., Ltd. | Method of producing silicon epitaxial wafers |
KR20030033187A (en) * | 2001-10-18 | 2003-05-01 | 주식회사 실트론 | Method of fabricating an epitexial wafer for semiconductor |
JP2004224694A (en) * | 1998-10-14 | 2004-08-12 | Memc Electron Materials Inc | Epitaxial silicon wafer not substantially having crystal growth transfer defect |
KR100500394B1 (en) * | 2002-12-09 | 2005-07-07 | 주식회사 실트론 | Manufacturing method of Epitaxial silicon wafer |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60247935A (en) * | 1984-05-23 | 1985-12-07 | Toshiba Ceramics Co Ltd | Manufacture of semiconductor wafer |
JPS6385085A (en) * | 1986-09-29 | 1988-04-15 | Nec Corp | Method for growing silicon single crystal |
-
1991
- 1991-05-15 JP JP3139688A patent/JP2779556B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60247935A (en) * | 1984-05-23 | 1985-12-07 | Toshiba Ceramics Co Ltd | Manufacture of semiconductor wafer |
JPS6385085A (en) * | 1986-09-29 | 1988-04-15 | Nec Corp | Method for growing silicon single crystal |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0959154A1 (en) * | 1998-05-22 | 1999-11-24 | Shin-Etsu Handotai Company Limited | A method for producing an epitaxial silicon single crystal wafer and the epitaxial single crystal wafer |
US6162708A (en) * | 1998-05-22 | 2000-12-19 | Shin-Etsu Handotai Co., Ltd. | Method for producing an epitaxial silicon single crystal wafer and the epitaxial silicon single crystal wafer |
JP2004224694A (en) * | 1998-10-14 | 2004-08-12 | Memc Electron Materials Inc | Epitaxial silicon wafer not substantially having crystal growth transfer defect |
WO2001086710A1 (en) * | 2000-05-09 | 2001-11-15 | Shin-Etsu Handotai Co., Ltd. | Method of producing silicon epitaxial wafers |
US6544899B2 (en) | 2000-05-09 | 2003-04-08 | Shin-Etsu Handotai Co. | Process for manufacturing silicon epitaxial wafer |
KR20030033187A (en) * | 2001-10-18 | 2003-05-01 | 주식회사 실트론 | Method of fabricating an epitexial wafer for semiconductor |
KR100500394B1 (en) * | 2002-12-09 | 2005-07-07 | 주식회사 실트론 | Manufacturing method of Epitaxial silicon wafer |
Also Published As
Publication number | Publication date |
---|---|
JP2779556B2 (en) | 1998-07-23 |
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