JPH05120158A - Back-up memory circuit - Google Patents

Abstract

PURPOSE:To cope with the high speed operation of a CPU by deciding the output signal supplied to a back-up RAM based on a chip selection signal and a control signal of a low or high level. CONSTITUTION:An OR circuit 4 decides the output signal which is applied to a back-up RAM 3 based on the OR between a control signal and a chip selection signal. That is, a control signal of a low level is outputted from a comparator 1 with application of a power supply. At the same time, a chip selection signal of a low level is outputted from a programmable logic device PLD 2. The OR secured between both signals is set at a low level. Therefore the output signal supplied to the RAM 3 is identical with a chip selection signal of a low level. Meanwhile a control signal of a high level is outputted from the comparator 1 when the power supply is turned off. Thus the PLD 2 does not work and therefore the OR is set at a high level. As a result, a signal of a high level is supplied to the RAM 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a backup memory circuit for storing data, and more particularly to a backup memory circuit for outputting a chip select signal of a backup RAM by PLD.

[0002]

2. Description of the Related Art Conventionally, in a control device including an NC device and a microcomputer, a backup RAM driven by a battery for storing data when the power is off.
Was often used. In these memory circuits for backup, a chip select signal for activating the backup RAM is output by a decoder composed of CMOS gates.

[0003]

However, since the conventional CMOS gate operates slowly, it is difficult to cope with the recent increase in the CPU speed. Moreover, in order to support high-mix low-volume production, there is an increasing demand year after year to easily change the specifications of the decoder. However, since the CMOS gate has a fixed function, internal pattern connection is required to change the specifications. There is an inconvenience that it is necessary to change the work and it cannot be done easily.

In order to solve such a problem, the CMO
PLD (Programmable) instead of S gate
Although it is considered to use a Logic Device), it is difficult to realize it because there is no PLD that operates in the vicinity of the battery voltage of 3V in practice.

An object of the present invention is to provide a backup memory circuit in which a chip select signal for a backup RAM is output by a PLD.

[0006]

In order to solve the above problems, in a backup memory circuit according to the present invention, two types of control signals, low or high, are output by comparing the device power supply voltage with the backup power supply voltage. And a PLD that outputs a low-level chip select signal, and a logic circuit that determines an output signal to the backup RAM based on the chip select signal and a low or high control signal.

[0007]

The comparator circuit compares the device power supply voltage with the backup power supply voltage, outputs a high level control signal when the device power supply voltage is lower than the backup power supply voltage, and the device power supply voltage is greater than or equal to the backup power supply voltage. When this is the case, a low level control signal is output. When the power is turned on, since the low level chip select signal is input to the logic circuit as well as the low level control signal, the low level chip select signal is supplied as an output signal to the backup RAM by the logical sum. On the other hand, when the power is off, the PLD does not operate, so the chip select signal is not output and only the high level control signal is input to the logic circuit. Therefore, a high level output signal is supplied to the backup RAM by the logical sum.

Therefore, when the power is turned on, the backup RAM is activated by the low level chip select signal, and when the power is turned off, the data in the backup RAM is held by the high level output signal.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a backup memory circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of the backup memory circuit. This circuit compares a device power supply voltage Vcc with a backup power supply (battery) voltage Vcb and outputs a low or high level control signal, and a PL which outputs a chip select signal.
A backup RA is generated by the logical sum of D2 and the chip select signal and a low or high level control signal.
It is composed of an OR circuit 4 which determines an output signal to M3.

Comparator 1, backup RAM
3, the OR circuit 4 has a backup power supply voltage Vcb (3V)
PLD2 is driven by the device power supply voltage Vcc (5
Driven by V). Therefore, the PLD 2 is activated when the power is turned on and does not operate when the power is turned off.

In the circuit of FIG. 1, the comparator 1 has V
Comparing cc and Vcb, when Vcc ≧ Vcb, the output is “low”, and when Vcc <Vcb, the output is “high”. That is, a low level signal is output when the power is turned on, and a high level signal is output when the power is turned off. Then, these signals (a in the figure) are added as control signals to the OR circuit 4 in the next stage. When the power is turned on, a low level chip select signal (b in the figure) is output from the PLD 2 and added to the OR circuit 4.

In the OR circuit 4, the backup RA is calculated by the logical sum of the control signal and the chip select signal.
Determine the output signal to M3. That is, when the power is turned on (Vcc ≧ Vcb), the comparator 1 outputs the low-level control signal and the PLD 2 also outputs the low-level chip select signal.
The logical sum of the two signals is "low". As a result, the output signal (c in the figure) supplied to the backup RAM 3 becomes a low level chip select signal. On the contrary,
When the power is off (Vcc <Vcb), the comparator 1
Outputs a high level control signal from P
Since the LD2 does not operate, the logical sum becomes "high". As a result, the output signal (c in the figure) supplied to the backup RAM 3 becomes a high level signal.

According to the above circuit configuration, since the chip select signal is supplied to the backup RAM 3 when the power is turned on, a predetermined backup RAM can be activated. At this time, data can be written in the backup RAM 3. Further, since the high-level signal is supplied to the backup RAM 3 when the power is turned off, the data cannot be written and the internal data can be held.

In this embodiment, an OR circuit is used as a logic circuit.
Although a circuit is used, another circuit may be used as long as an equivalent function can be obtained.

[0016]

As described above, in the backup memory circuit according to the present invention, the power is turned on / off.
A low or high control signal is output corresponding to F, and a chip select signal is output from the PLD in response to power ON, and a backup R is performed based on the chip select signal and a low or high control signal.
Since the output signal to the AM is decided, the conventional CM
The backup RAM chip select signal realized by the OS gate can be realized by the PLD. Therefore, it becomes possible to sufficiently cope with the speedup of the CPU,
Various specifications can be changed easily.

Since the PLD is driven by the device power supply voltage, stable operation can be obtained. In addition, since the high-level signal is supplied to the backup RAM even when the device power supply voltage is turned off, it is possible to prevent data destruction due to writing or the like.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a backup memory circuit.

[Explanation of symbols]

1 ... Comparator, 2 ... PLD, 3 ... Backup RA
M, 4 ... OR circuit

Claims (1)

[Claims] 1. A comparison circuit for comparing a device power supply voltage with a backup power supply voltage and outputting a first or second control signal, a PLD for outputting a chip select signal, and the first or second control signal. And a logic circuit that determines an output signal to the backup RAM based on a chip select signal.